2012-04-16 01:29:19 +04:00
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/*
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* QEMU MIPS CPU
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*
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* Copyright (c) 2012 SUSE LINUX Products GmbH
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see
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* <http://www.gnu.org/licenses/lgpl-2.1.html>
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*/
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2016-01-18 20:35:00 +03:00
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#include "qemu/osdep.h"
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2020-10-12 12:58:04 +03:00
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#include "qemu/cutils.h"
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2020-12-07 01:29:33 +03:00
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#include "qemu/qemu-print.h"
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include/qemu/osdep.h: Don't include qapi/error.h
Commit 57cb38b included qapi/error.h into qemu/osdep.h to get the
Error typedef. Since then, we've moved to include qemu/osdep.h
everywhere. Its file comment explains: "To avoid getting into
possible circular include dependencies, this file should not include
any other QEMU headers, with the exceptions of config-host.h,
compiler.h, os-posix.h and os-win32.h, all of which are doing a
similar job to this file and are under similar constraints."
qapi/error.h doesn't do a similar job, and it doesn't adhere to
similar constraints: it includes qapi-types.h. That's in excess of
100KiB of crap most .c files don't actually need.
Add the typedef to qemu/typedefs.h, and include that instead of
qapi/error.h. Include qapi/error.h in .c files that need it and don't
get it now. Include qapi-types.h in qom/object.h for uint16List.
Update scripts/clean-includes accordingly. Update it further to match
reality: replace config.h by config-target.h, add sysemu/os-posix.h,
sysemu/os-win32.h. Update the list of includes in the qemu/osdep.h
comment quoted above similarly.
This reduces the number of objects depending on qapi/error.h from "all
of them" to less than a third. Unfortunately, the number depending on
qapi-types.h shrinks only a little. More work is needed for that one.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
[Fix compilation without the spice devel packages. - Paolo]
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-03-14 11:01:28 +03:00
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#include "qapi/error.h"
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2012-04-16 01:29:19 +04:00
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#include "cpu.h"
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2017-09-20 22:49:30 +03:00
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#include "internal.h"
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2014-06-18 02:10:33 +04:00
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#include "kvm_mips.h"
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2019-05-23 17:35:07 +03:00
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#include "qemu/module.h"
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2014-06-18 02:10:33 +04:00
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#include "sysemu/kvm.h"
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2020-10-12 12:58:04 +03:00
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#include "sysemu/qtest.h"
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2016-03-15 15:18:37 +03:00
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#include "exec/exec-all.h"
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2020-10-12 12:57:53 +03:00
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#include "hw/qdev-properties.h"
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2020-10-12 12:57:54 +03:00
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#include "hw/qdev-clock.h"
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2020-12-07 01:29:33 +03:00
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#include "hw/semihosting/semihost.h"
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2020-12-07 00:07:34 +03:00
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#include "qapi/qapi-commands-machine-target.h"
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2012-04-16 01:29:19 +04:00
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2020-12-07 01:12:23 +03:00
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#if !defined(CONFIG_USER_ONLY)
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/* Called for updates to CP0_Status. */
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void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc)
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{
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int32_t tcstatus, *tcst;
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uint32_t v = cpu->CP0_Status;
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uint32_t cu, mx, asid, ksu;
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uint32_t mask = ((1 << CP0TCSt_TCU3)
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| (1 << CP0TCSt_TCU2)
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| (1 << CP0TCSt_TCU1)
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| (1 << CP0TCSt_TCU0)
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| (1 << CP0TCSt_TMX)
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| (3 << CP0TCSt_TKSU)
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| (0xff << CP0TCSt_TASID));
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cu = (v >> CP0St_CU0) & 0xf;
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mx = (v >> CP0St_MX) & 0x1;
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ksu = (v >> CP0St_KSU) & 0x3;
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asid = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
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tcstatus = cu << CP0TCSt_TCU0;
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tcstatus |= mx << CP0TCSt_TMX;
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tcstatus |= ksu << CP0TCSt_TKSU;
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tcstatus |= asid;
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if (tc == cpu->current_tc) {
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tcst = &cpu->active_tc.CP0_TCStatus;
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} else {
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tcst = &cpu->tcs[tc].CP0_TCStatus;
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}
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*tcst &= ~mask;
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*tcst |= tcstatus;
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compute_hflags(cpu);
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}
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void cpu_mips_store_status(CPUMIPSState *env, target_ulong val)
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{
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uint32_t mask = env->CP0_Status_rw_bitmask;
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target_ulong old = env->CP0_Status;
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if (env->insn_flags & ISA_MIPS_R6) {
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bool has_supervisor = extract32(mask, CP0St_KSU, 2) == 0x3;
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#if defined(TARGET_MIPS64)
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uint32_t ksux = (1 << CP0St_KX) & val;
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ksux |= (ksux >> 1) & val; /* KX = 0 forces SX to be 0 */
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ksux |= (ksux >> 1) & val; /* SX = 0 forces UX to be 0 */
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val = (val & ~(7 << CP0St_UX)) | ksux;
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#endif
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if (has_supervisor && extract32(val, CP0St_KSU, 2) == 0x3) {
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mask &= ~(3 << CP0St_KSU);
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}
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mask &= ~(((1 << CP0St_SR) | (1 << CP0St_NMI)) & val);
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}
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env->CP0_Status = (old & ~mask) | (val & mask);
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#if defined(TARGET_MIPS64)
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if ((env->CP0_Status ^ old) & (old & (7 << CP0St_UX))) {
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/* Access to at least one of the 64-bit segments has been disabled */
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tlb_flush(env_cpu(env));
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}
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#endif
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if (ase_mt_available(env)) {
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sync_c0_status(env, env, env->current_tc);
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} else {
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compute_hflags(env);
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}
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}
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void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val)
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{
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uint32_t mask = 0x00C00300;
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uint32_t old = env->CP0_Cause;
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int i;
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if (env->insn_flags & ISA_MIPS_R2) {
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mask |= 1 << CP0Ca_DC;
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}
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if (env->insn_flags & ISA_MIPS_R6) {
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mask &= ~((1 << CP0Ca_WP) & val);
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}
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env->CP0_Cause = (env->CP0_Cause & ~mask) | (val & mask);
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if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) {
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if (env->CP0_Cause & (1 << CP0Ca_DC)) {
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cpu_mips_stop_count(env);
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} else {
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cpu_mips_start_count(env);
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}
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}
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/* Set/reset software interrupts */
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for (i = 0 ; i < 2 ; i++) {
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if ((old ^ env->CP0_Cause) & (1 << (CP0Ca_IP + i))) {
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cpu_mips_soft_irq(env, i, env->CP0_Cause & (1 << (CP0Ca_IP + i)));
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}
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}
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}
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#endif /* !CONFIG_USER_ONLY */
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static const char * const excp_names[EXCP_LAST + 1] = {
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[EXCP_RESET] = "reset",
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[EXCP_SRESET] = "soft reset",
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[EXCP_DSS] = "debug single step",
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[EXCP_DINT] = "debug interrupt",
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[EXCP_NMI] = "non-maskable interrupt",
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[EXCP_MCHECK] = "machine check",
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[EXCP_EXT_INTERRUPT] = "interrupt",
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[EXCP_DFWATCH] = "deferred watchpoint",
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[EXCP_DIB] = "debug instruction breakpoint",
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[EXCP_IWATCH] = "instruction fetch watchpoint",
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[EXCP_AdEL] = "address error load",
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[EXCP_AdES] = "address error store",
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[EXCP_TLBF] = "TLB refill",
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[EXCP_IBE] = "instruction bus error",
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[EXCP_DBp] = "debug breakpoint",
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[EXCP_SYSCALL] = "syscall",
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[EXCP_BREAK] = "break",
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[EXCP_CpU] = "coprocessor unusable",
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[EXCP_RI] = "reserved instruction",
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[EXCP_OVERFLOW] = "arithmetic overflow",
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[EXCP_TRAP] = "trap",
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[EXCP_FPE] = "floating point",
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[EXCP_DDBS] = "debug data break store",
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[EXCP_DWATCH] = "data watchpoint",
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[EXCP_LTLBL] = "TLB modify",
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[EXCP_TLBL] = "TLB load",
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[EXCP_TLBS] = "TLB store",
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[EXCP_DBE] = "data bus error",
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[EXCP_DDBL] = "debug data break load",
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[EXCP_THREAD] = "thread",
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[EXCP_MDMX] = "MDMX",
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[EXCP_C2E] = "precise coprocessor 2",
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[EXCP_CACHE] = "cache error",
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[EXCP_TLBXI] = "TLB execute-inhibit",
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[EXCP_TLBRI] = "TLB read-inhibit",
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[EXCP_MSADIS] = "MSA disabled",
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[EXCP_MSAFPE] = "MSA floating point",
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};
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const char *mips_exception_name(int32_t exception)
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{
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if (exception < 0 || exception > EXCP_LAST) {
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return "unknown";
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}
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return excp_names[exception];
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}
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void cpu_set_exception_base(int vp_index, target_ulong address)
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{
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MIPSCPU *vp = MIPS_CPU(qemu_get_cpu(vp_index));
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vp->env.exception_base = address;
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}
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target_ulong exception_resume_pc(CPUMIPSState *env)
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{
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target_ulong bad_pc;
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target_ulong isa_mode;
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isa_mode = !!(env->hflags & MIPS_HFLAG_M16);
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bad_pc = env->active_tc.PC | isa_mode;
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if (env->hflags & MIPS_HFLAG_BMASK) {
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/*
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* If the exception was raised from a delay slot, come back to
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* the jump.
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*/
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bad_pc -= (env->hflags & MIPS_HFLAG_B16 ? 2 : 4);
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}
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return bad_pc;
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}
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bool mips_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
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{
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if (interrupt_request & CPU_INTERRUPT_HARD) {
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MIPSCPU *cpu = MIPS_CPU(cs);
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CPUMIPSState *env = &cpu->env;
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if (cpu_mips_hw_interrupts_enabled(env) &&
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cpu_mips_hw_interrupts_pending(env)) {
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/* Raise it */
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cs->exception_index = EXCP_EXT_INTERRUPT;
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env->error_code = 0;
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mips_cpu_do_interrupt(cs);
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return true;
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}
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}
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return false;
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}
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void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env,
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uint32_t exception,
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int error_code,
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uintptr_t pc)
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{
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CPUState *cs = env_cpu(env);
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qemu_log_mask(CPU_LOG_INT, "%s: %d (%s) %d\n",
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__func__, exception, mips_exception_name(exception),
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error_code);
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cs->exception_index = exception;
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env->error_code = error_code;
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cpu_loop_exit_restore(cs, pc);
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}
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|
|
2013-06-21 21:09:18 +04:00
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static void mips_cpu_set_pc(CPUState *cs, vaddr value)
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{
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MIPSCPU *cpu = MIPS_CPU(cs);
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CPUMIPSState *env = &cpu->env;
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env->active_tc.PC = value & ~(target_ulong)1;
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if (value & 1) {
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env->hflags |= MIPS_HFLAG_M16;
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} else {
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env->hflags &= ~(MIPS_HFLAG_M16);
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}
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}
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|
|
2020-10-29 22:30:01 +03:00
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|
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static void mips_cpu_synchronize_from_tb(CPUState *cs,
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|
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const TranslationBlock *tb)
|
2013-06-28 21:31:32 +04:00
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{
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MIPSCPU *cpu = MIPS_CPU(cs);
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CPUMIPSState *env = &cpu->env;
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env->active_tc.PC = tb->pc;
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env->hflags &= ~MIPS_HFLAG_BMASK;
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env->hflags |= tb->flags & MIPS_HFLAG_BMASK;
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}
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|
2013-08-25 20:53:55 +04:00
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static bool mips_cpu_has_work(CPUState *cs)
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{
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MIPSCPU *cpu = MIPS_CPU(cs);
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CPUMIPSState *env = &cpu->env;
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bool has_work = false;
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|
|
|
2019-08-19 15:07:46 +03:00
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|
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/*
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|
|
|
* Prior to MIPS Release 6 it is implementation dependent if non-enabled
|
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* interrupts wake-up the CPU, however most of the implementations only
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* check for interrupts that can be taken.
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*/
|
2013-08-25 20:53:55 +04:00
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if ((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
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|
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cpu_mips_hw_interrupts_pending(env)) {
|
2015-09-14 15:58:24 +03:00
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|
if (cpu_mips_hw_interrupts_enabled(env) ||
|
2020-12-16 14:34:42 +03:00
|
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(env->insn_flags & ISA_MIPS_R6)) {
|
2015-09-14 15:58:23 +03:00
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has_work = true;
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}
|
2013-08-25 20:53:55 +04:00
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}
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|
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/* MIPS-MT has the ability to halt the CPU. */
|
2020-12-02 20:49:00 +03:00
|
|
|
if (ase_mt_available(env)) {
|
2019-08-19 15:07:46 +03:00
|
|
|
/*
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* The QEMU model will issue an _WAKE request whenever the CPUs
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* should be woken up.
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*/
|
2013-08-25 20:53:55 +04:00
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|
if (cs->interrupt_request & CPU_INTERRUPT_WAKE) {
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has_work = true;
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}
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if (!mips_vpe_active(env)) {
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has_work = false;
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|
}
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|
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}
|
2016-02-03 15:31:07 +03:00
|
|
|
/* MIPS Release 6 has the ability to halt the CPU. */
|
|
|
|
if (env->CP0_Config5 & (1 << CP0C5_VP)) {
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|
|
if (cs->interrupt_request & CPU_INTERRUPT_WAKE) {
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|
|
has_work = true;
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|
|
}
|
|
|
|
if (!mips_vp_active(env)) {
|
|
|
|
has_work = false;
|
|
|
|
}
|
|
|
|
}
|
2013-08-25 20:53:55 +04:00
|
|
|
return has_work;
|
|
|
|
}
|
|
|
|
|
2020-12-07 01:52:07 +03:00
|
|
|
#include "cpu-defs.c.inc"
|
2020-12-07 01:29:33 +03:00
|
|
|
|
2020-12-14 17:07:13 +03:00
|
|
|
static void mips_cpu_reset(DeviceState *dev)
|
2020-12-07 01:29:33 +03:00
|
|
|
{
|
2020-12-14 17:07:13 +03:00
|
|
|
CPUState *cs = CPU(dev);
|
|
|
|
MIPSCPU *cpu = MIPS_CPU(cs);
|
|
|
|
MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(cpu);
|
|
|
|
CPUMIPSState *env = &cpu->env;
|
|
|
|
|
|
|
|
mcc->parent_reset(dev);
|
|
|
|
|
|
|
|
memset(env, 0, offsetof(CPUMIPSState, end_reset_fields));
|
2020-12-07 01:29:33 +03:00
|
|
|
|
|
|
|
/* Reset registers to their default values */
|
|
|
|
env->CP0_PRid = env->cpu_model->CP0_PRid;
|
|
|
|
env->CP0_Config0 = env->cpu_model->CP0_Config0;
|
|
|
|
#ifdef TARGET_WORDS_BIGENDIAN
|
|
|
|
env->CP0_Config0 |= (1 << CP0C0_BE);
|
|
|
|
#endif
|
|
|
|
env->CP0_Config1 = env->cpu_model->CP0_Config1;
|
|
|
|
env->CP0_Config2 = env->cpu_model->CP0_Config2;
|
|
|
|
env->CP0_Config3 = env->cpu_model->CP0_Config3;
|
|
|
|
env->CP0_Config4 = env->cpu_model->CP0_Config4;
|
|
|
|
env->CP0_Config4_rw_bitmask = env->cpu_model->CP0_Config4_rw_bitmask;
|
|
|
|
env->CP0_Config5 = env->cpu_model->CP0_Config5;
|
|
|
|
env->CP0_Config5_rw_bitmask = env->cpu_model->CP0_Config5_rw_bitmask;
|
|
|
|
env->CP0_Config6 = env->cpu_model->CP0_Config6;
|
|
|
|
env->CP0_Config6_rw_bitmask = env->cpu_model->CP0_Config6_rw_bitmask;
|
|
|
|
env->CP0_Config7 = env->cpu_model->CP0_Config7;
|
|
|
|
env->CP0_Config7_rw_bitmask = env->cpu_model->CP0_Config7_rw_bitmask;
|
|
|
|
env->CP0_LLAddr_rw_bitmask = env->cpu_model->CP0_LLAddr_rw_bitmask
|
|
|
|
<< env->cpu_model->CP0_LLAddr_shift;
|
|
|
|
env->CP0_LLAddr_shift = env->cpu_model->CP0_LLAddr_shift;
|
|
|
|
env->SYNCI_Step = env->cpu_model->SYNCI_Step;
|
|
|
|
env->CCRes = env->cpu_model->CCRes;
|
|
|
|
env->CP0_Status_rw_bitmask = env->cpu_model->CP0_Status_rw_bitmask;
|
|
|
|
env->CP0_TCStatus_rw_bitmask = env->cpu_model->CP0_TCStatus_rw_bitmask;
|
|
|
|
env->CP0_SRSCtl = env->cpu_model->CP0_SRSCtl;
|
|
|
|
env->current_tc = 0;
|
|
|
|
env->SEGBITS = env->cpu_model->SEGBITS;
|
|
|
|
env->SEGMask = (target_ulong)((1ULL << env->cpu_model->SEGBITS) - 1);
|
|
|
|
#if defined(TARGET_MIPS64)
|
|
|
|
if (env->cpu_model->insn_flags & ISA_MIPS3) {
|
|
|
|
env->SEGMask |= 3ULL << 62;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
env->PABITS = env->cpu_model->PABITS;
|
|
|
|
env->CP0_SRSConf0_rw_bitmask = env->cpu_model->CP0_SRSConf0_rw_bitmask;
|
|
|
|
env->CP0_SRSConf0 = env->cpu_model->CP0_SRSConf0;
|
|
|
|
env->CP0_SRSConf1_rw_bitmask = env->cpu_model->CP0_SRSConf1_rw_bitmask;
|
|
|
|
env->CP0_SRSConf1 = env->cpu_model->CP0_SRSConf1;
|
|
|
|
env->CP0_SRSConf2_rw_bitmask = env->cpu_model->CP0_SRSConf2_rw_bitmask;
|
|
|
|
env->CP0_SRSConf2 = env->cpu_model->CP0_SRSConf2;
|
|
|
|
env->CP0_SRSConf3_rw_bitmask = env->cpu_model->CP0_SRSConf3_rw_bitmask;
|
|
|
|
env->CP0_SRSConf3 = env->cpu_model->CP0_SRSConf3;
|
|
|
|
env->CP0_SRSConf4_rw_bitmask = env->cpu_model->CP0_SRSConf4_rw_bitmask;
|
|
|
|
env->CP0_SRSConf4 = env->cpu_model->CP0_SRSConf4;
|
|
|
|
env->CP0_PageGrain_rw_bitmask = env->cpu_model->CP0_PageGrain_rw_bitmask;
|
|
|
|
env->CP0_PageGrain = env->cpu_model->CP0_PageGrain;
|
|
|
|
env->CP0_EBaseWG_rw_bitmask = env->cpu_model->CP0_EBaseWG_rw_bitmask;
|
|
|
|
env->active_fpu.fcr0 = env->cpu_model->CP1_fcr0;
|
|
|
|
env->active_fpu.fcr31_rw_bitmask = env->cpu_model->CP1_fcr31_rw_bitmask;
|
|
|
|
env->active_fpu.fcr31 = env->cpu_model->CP1_fcr31;
|
|
|
|
env->msair = env->cpu_model->MSAIR;
|
|
|
|
env->insn_flags = env->cpu_model->insn_flags;
|
|
|
|
|
|
|
|
#if defined(CONFIG_USER_ONLY)
|
|
|
|
env->CP0_Status = (MIPS_HFLAG_UM << CP0St_KSU);
|
|
|
|
# ifdef TARGET_MIPS64
|
|
|
|
/* Enable 64-bit register mode. */
|
|
|
|
env->CP0_Status |= (1 << CP0St_PX);
|
|
|
|
# endif
|
|
|
|
# ifdef TARGET_ABI_MIPSN64
|
|
|
|
/* Enable 64-bit address mode. */
|
|
|
|
env->CP0_Status |= (1 << CP0St_UX);
|
|
|
|
# endif
|
|
|
|
/*
|
|
|
|
* Enable access to the CPUNum, SYNCI_Step, CC, and CCRes RDHWR
|
|
|
|
* hardware registers.
|
|
|
|
*/
|
|
|
|
env->CP0_HWREna |= 0x0000000F;
|
|
|
|
if (env->CP0_Config1 & (1 << CP0C1_FP)) {
|
|
|
|
env->CP0_Status |= (1 << CP0St_CU1);
|
|
|
|
}
|
|
|
|
if (env->CP0_Config3 & (1 << CP0C3_DSPP)) {
|
|
|
|
env->CP0_Status |= (1 << CP0St_MX);
|
|
|
|
}
|
|
|
|
# if defined(TARGET_MIPS64)
|
|
|
|
/* For MIPS64, init FR bit to 1 if FPU unit is there and bit is writable. */
|
|
|
|
if ((env->CP0_Config1 & (1 << CP0C1_FP)) &&
|
|
|
|
(env->CP0_Status_rw_bitmask & (1 << CP0St_FR))) {
|
|
|
|
env->CP0_Status |= (1 << CP0St_FR);
|
|
|
|
}
|
|
|
|
# endif
|
|
|
|
#else /* !CONFIG_USER_ONLY */
|
|
|
|
if (env->hflags & MIPS_HFLAG_BMASK) {
|
|
|
|
/*
|
|
|
|
* If the exception was raised from a delay slot,
|
|
|
|
* come back to the jump.
|
|
|
|
*/
|
|
|
|
env->CP0_ErrorEPC = (env->active_tc.PC
|
|
|
|
- (env->hflags & MIPS_HFLAG_B16 ? 2 : 4));
|
|
|
|
} else {
|
|
|
|
env->CP0_ErrorEPC = env->active_tc.PC;
|
|
|
|
}
|
|
|
|
env->active_tc.PC = env->exception_base;
|
|
|
|
env->CP0_Random = env->tlb->nb_tlb - 1;
|
|
|
|
env->tlb->tlb_in_use = env->tlb->nb_tlb;
|
|
|
|
env->CP0_Wired = 0;
|
|
|
|
env->CP0_GlobalNumber = (cs->cpu_index & 0xFF) << CP0GN_VPId;
|
|
|
|
env->CP0_EBase = (cs->cpu_index & 0x3FF);
|
|
|
|
if (mips_um_ksegs_enabled()) {
|
|
|
|
env->CP0_EBase |= 0x40000000;
|
|
|
|
} else {
|
|
|
|
env->CP0_EBase |= (int32_t)0x80000000;
|
|
|
|
}
|
|
|
|
if (env->CP0_Config3 & (1 << CP0C3_CMGCR)) {
|
|
|
|
env->CP0_CMGCRBase = 0x1fbf8000 >> 4;
|
|
|
|
}
|
|
|
|
env->CP0_EntryHi_ASID_mask = (env->CP0_Config5 & (1 << CP0C5_MI)) ?
|
|
|
|
0x0 : (env->CP0_Config4 & (1 << CP0C4_AE)) ? 0x3ff : 0xff;
|
|
|
|
env->CP0_Status = (1 << CP0St_BEV) | (1 << CP0St_ERL);
|
|
|
|
/*
|
|
|
|
* Vectored interrupts not implemented, timer on int 7,
|
|
|
|
* no performance counters.
|
|
|
|
*/
|
|
|
|
env->CP0_IntCtl = 0xe0000000;
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; i < 7; i++) {
|
|
|
|
env->CP0_WatchLo[i] = 0;
|
|
|
|
env->CP0_WatchHi[i] = 0x80000000;
|
|
|
|
}
|
|
|
|
env->CP0_WatchLo[7] = 0;
|
|
|
|
env->CP0_WatchHi[7] = 0;
|
|
|
|
}
|
|
|
|
/* Count register increments in debug mode, EJTAG version 1 */
|
|
|
|
env->CP0_Debug = (1 << CP0DB_CNT) | (0x1 << CP0DB_VER);
|
|
|
|
|
|
|
|
cpu_mips_store_count(env, 1);
|
|
|
|
|
|
|
|
if (ase_mt_available(env)) {
|
|
|
|
int i;
|
|
|
|
|
|
|
|
/* Only TC0 on VPE 0 starts as active. */
|
|
|
|
for (i = 0; i < ARRAY_SIZE(env->tcs); i++) {
|
|
|
|
env->tcs[i].CP0_TCBind = cs->cpu_index << CP0TCBd_CurVPE;
|
|
|
|
env->tcs[i].CP0_TCHalt = 1;
|
|
|
|
}
|
|
|
|
env->active_tc.CP0_TCHalt = 1;
|
|
|
|
cs->halted = 1;
|
|
|
|
|
|
|
|
if (cs->cpu_index == 0) {
|
|
|
|
/* VPE0 starts up enabled. */
|
|
|
|
env->mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP);
|
|
|
|
env->CP0_VPEConf0 |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
|
|
|
|
|
|
|
|
/* TC0 starts up unhalted. */
|
|
|
|
cs->halted = 0;
|
|
|
|
env->active_tc.CP0_TCHalt = 0;
|
|
|
|
env->tcs[0].CP0_TCHalt = 0;
|
|
|
|
/* With thread 0 active. */
|
|
|
|
env->active_tc.CP0_TCStatus = (1 << CP0TCSt_A);
|
|
|
|
env->tcs[0].CP0_TCStatus = (1 << CP0TCSt_A);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Configure default legacy segmentation control. We use this regardless of
|
|
|
|
* whether segmentation control is presented to the guest.
|
|
|
|
*/
|
|
|
|
/* KSeg3 (seg0 0xE0000000..0xFFFFFFFF) */
|
|
|
|
env->CP0_SegCtl0 = (CP0SC_AM_MK << CP0SC_AM);
|
|
|
|
/* KSeg2 (seg1 0xC0000000..0xDFFFFFFF) */
|
|
|
|
env->CP0_SegCtl0 |= ((CP0SC_AM_MSK << CP0SC_AM)) << 16;
|
|
|
|
/* KSeg1 (seg2 0xA0000000..0x9FFFFFFF) */
|
|
|
|
env->CP0_SegCtl1 = (0 << CP0SC_PA) | (CP0SC_AM_UK << CP0SC_AM) |
|
|
|
|
(2 << CP0SC_C);
|
|
|
|
/* KSeg0 (seg3 0x80000000..0x9FFFFFFF) */
|
|
|
|
env->CP0_SegCtl1 |= ((0 << CP0SC_PA) | (CP0SC_AM_UK << CP0SC_AM) |
|
|
|
|
(3 << CP0SC_C)) << 16;
|
|
|
|
/* USeg (seg4 0x40000000..0x7FFFFFFF) */
|
|
|
|
env->CP0_SegCtl2 = (2 << CP0SC_PA) | (CP0SC_AM_MUSK << CP0SC_AM) |
|
|
|
|
(1 << CP0SC_EU) | (2 << CP0SC_C);
|
|
|
|
/* USeg (seg5 0x00000000..0x3FFFFFFF) */
|
|
|
|
env->CP0_SegCtl2 |= ((0 << CP0SC_PA) | (CP0SC_AM_MUSK << CP0SC_AM) |
|
|
|
|
(1 << CP0SC_EU) | (2 << CP0SC_C)) << 16;
|
|
|
|
/* XKPhys (note, SegCtl2.XR = 0, so XAM won't be used) */
|
|
|
|
env->CP0_SegCtl1 |= (CP0SC_AM_UK << CP0SC1_XAM);
|
|
|
|
#endif /* !CONFIG_USER_ONLY */
|
2020-12-16 14:34:42 +03:00
|
|
|
if ((env->insn_flags & ISA_MIPS_R6) &&
|
2020-12-07 01:29:33 +03:00
|
|
|
(env->active_fpu.fcr0 & (1 << FCR0_F64))) {
|
|
|
|
/* Status.FR = 0 mode in 64-bit FPU not allowed in R6 */
|
|
|
|
env->CP0_Status |= (1 << CP0St_FR);
|
|
|
|
}
|
|
|
|
|
2020-12-16 14:34:42 +03:00
|
|
|
if (env->insn_flags & ISA_MIPS_R6) {
|
2020-12-07 01:29:33 +03:00
|
|
|
/* PTW = 1 */
|
|
|
|
env->CP0_PWSize = 0x40;
|
|
|
|
/* GDI = 12 */
|
|
|
|
/* UDI = 12 */
|
|
|
|
/* MDI = 12 */
|
|
|
|
/* PRI = 12 */
|
|
|
|
/* PTEI = 2 */
|
|
|
|
env->CP0_PWField = 0x0C30C302;
|
|
|
|
} else {
|
|
|
|
/* GDI = 0 */
|
|
|
|
/* UDI = 0 */
|
|
|
|
/* MDI = 0 */
|
|
|
|
/* PRI = 0 */
|
|
|
|
/* PTEI = 2 */
|
|
|
|
env->CP0_PWField = 0x02;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (env->CP0_Config3 & (1 << CP0C3_ISA) & (1 << (CP0C3_ISA + 1))) {
|
|
|
|
/* microMIPS on reset when Config3.ISA is 3 */
|
|
|
|
env->hflags |= MIPS_HFLAG_M16;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* MSA */
|
|
|
|
if (env->CP0_Config3 & (1 << CP0C3_MSAP)) {
|
|
|
|
msa_reset(env);
|
|
|
|
}
|
|
|
|
|
|
|
|
compute_hflags(env);
|
|
|
|
restore_fp_status(env);
|
|
|
|
restore_pamask(env);
|
|
|
|
cs->exception_index = EXCP_NONE;
|
|
|
|
|
|
|
|
if (semihosting_get_argc()) {
|
|
|
|
/* UHI interface can be used to obtain argc and argv */
|
|
|
|
env->active_tc.gpr[4] = -1;
|
|
|
|
}
|
2014-06-18 02:10:33 +04:00
|
|
|
|
|
|
|
#ifndef CONFIG_USER_ONLY
|
|
|
|
if (kvm_enabled()) {
|
|
|
|
kvm_mips_reset_vcpu(cpu);
|
|
|
|
}
|
|
|
|
#endif
|
2012-04-16 01:29:19 +04:00
|
|
|
}
|
|
|
|
|
2019-08-19 15:07:46 +03:00
|
|
|
static void mips_cpu_disas_set_info(CPUState *s, disassemble_info *info)
|
|
|
|
{
|
2018-10-24 18:41:49 +03:00
|
|
|
MIPSCPU *cpu = MIPS_CPU(s);
|
|
|
|
CPUMIPSState *env = &cpu->env;
|
|
|
|
|
|
|
|
if (!(env->insn_flags & ISA_NANOMIPS32)) {
|
2015-07-12 05:00:04 +03:00
|
|
|
#ifdef TARGET_WORDS_BIGENDIAN
|
2018-10-24 18:41:49 +03:00
|
|
|
info->print_insn = print_insn_big_mips;
|
2015-07-12 05:00:04 +03:00
|
|
|
#else
|
2018-10-24 18:41:49 +03:00
|
|
|
info->print_insn = print_insn_little_mips;
|
2015-07-12 05:00:04 +03:00
|
|
|
#endif
|
2018-10-24 18:41:49 +03:00
|
|
|
} else {
|
|
|
|
#if defined(CONFIG_NANOMIPS_DIS)
|
|
|
|
info->print_insn = print_insn_nanomips;
|
|
|
|
#endif
|
|
|
|
}
|
2015-07-12 05:00:04 +03:00
|
|
|
}
|
|
|
|
|
2020-10-12 12:57:51 +03:00
|
|
|
/*
|
2020-10-12 12:57:53 +03:00
|
|
|
* Since commit 6af0bf9c7c3 this model assumes a CPU clocked at 200MHz.
|
2020-10-12 12:57:51 +03:00
|
|
|
*/
|
|
|
|
#define CPU_FREQ_HZ_DEFAULT 200000000
|
|
|
|
#define CP0_COUNT_RATE_DEFAULT 2
|
|
|
|
|
|
|
|
static void mips_cp0_period_set(MIPSCPU *cpu)
|
|
|
|
{
|
|
|
|
CPUMIPSState *env = &cpu->env;
|
|
|
|
|
2020-12-15 18:09:27 +03:00
|
|
|
env->cp0_count_ns = clock_ticks_to_ns(MIPS_CPU(cpu)->clock,
|
|
|
|
cpu->cp0_count_rate);
|
2020-10-12 12:57:54 +03:00
|
|
|
assert(env->cp0_count_ns);
|
2020-10-12 12:57:51 +03:00
|
|
|
}
|
|
|
|
|
2013-01-16 06:48:37 +04:00
|
|
|
static void mips_cpu_realizefn(DeviceState *dev, Error **errp)
|
|
|
|
{
|
2013-07-27 04:53:25 +04:00
|
|
|
CPUState *cs = CPU(dev);
|
2017-09-20 22:49:32 +03:00
|
|
|
MIPSCPU *cpu = MIPS_CPU(dev);
|
2020-12-07 01:49:07 +03:00
|
|
|
CPUMIPSState *env = &cpu->env;
|
2013-01-16 06:48:37 +04:00
|
|
|
MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(dev);
|
2016-10-20 14:26:03 +03:00
|
|
|
Error *local_err = NULL;
|
|
|
|
|
2020-10-12 12:57:54 +03:00
|
|
|
if (!clock_get(cpu->clock)) {
|
2020-10-12 12:58:04 +03:00
|
|
|
#ifndef CONFIG_USER_ONLY
|
|
|
|
if (!qtest_enabled()) {
|
|
|
|
g_autofree char *cpu_freq_str = freq_to_str(CPU_FREQ_HZ_DEFAULT);
|
|
|
|
|
|
|
|
warn_report("CPU input clock is not connected to any output clock, "
|
|
|
|
"using default frequency of %s.", cpu_freq_str);
|
|
|
|
}
|
|
|
|
#endif
|
2020-10-12 12:57:54 +03:00
|
|
|
/* Initialize the frequency in case the clock remains unconnected. */
|
|
|
|
clock_set_hz(cpu->clock, CPU_FREQ_HZ_DEFAULT);
|
|
|
|
}
|
2020-10-12 12:57:51 +03:00
|
|
|
mips_cp0_period_set(cpu);
|
|
|
|
|
2016-10-20 14:26:03 +03:00
|
|
|
cpu_exec_realizefn(cs, &local_err);
|
|
|
|
if (local_err != NULL) {
|
|
|
|
error_propagate(errp, local_err);
|
|
|
|
return;
|
|
|
|
}
|
2013-01-16 06:48:37 +04:00
|
|
|
|
2020-12-07 01:49:07 +03:00
|
|
|
env->exception_base = (int32_t)0xBFC00000;
|
|
|
|
|
|
|
|
#ifndef CONFIG_USER_ONLY
|
|
|
|
mmu_init(env, env->cpu_model);
|
|
|
|
#endif
|
|
|
|
fpu_init(env, env->cpu_model);
|
|
|
|
mvp_init(env);
|
2017-09-20 22:49:32 +03:00
|
|
|
|
2013-07-27 04:53:25 +04:00
|
|
|
cpu_reset(cs);
|
|
|
|
qemu_init_vcpu(cs);
|
2013-01-16 06:48:37 +04:00
|
|
|
|
|
|
|
mcc->parent_realize(dev, errp);
|
|
|
|
}
|
|
|
|
|
2012-04-16 04:37:56 +04:00
|
|
|
static void mips_cpu_initfn(Object *obj)
|
|
|
|
{
|
|
|
|
MIPSCPU *cpu = MIPS_CPU(obj);
|
|
|
|
CPUMIPSState *env = &cpu->env;
|
2017-09-20 22:49:33 +03:00
|
|
|
MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(obj);
|
2012-04-16 04:37:56 +04:00
|
|
|
|
2019-03-29 00:26:22 +03:00
|
|
|
cpu_set_cpustate_pointers(cpu);
|
2020-10-12 12:57:54 +03:00
|
|
|
cpu->clock = qdev_init_clock_in(DEVICE(obj), "clk-in", NULL, cpu);
|
2017-09-20 22:49:33 +03:00
|
|
|
env->cpu_model = mcc->cpu_def;
|
2012-04-16 04:37:56 +04:00
|
|
|
}
|
|
|
|
|
2017-09-20 22:49:33 +03:00
|
|
|
static char *mips_cpu_type_name(const char *cpu_model)
|
|
|
|
{
|
2017-10-05 16:51:10 +03:00
|
|
|
return g_strdup_printf(MIPS_CPU_TYPE_NAME("%s"), cpu_model);
|
2017-09-20 22:49:33 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
static ObjectClass *mips_cpu_class_by_name(const char *cpu_model)
|
|
|
|
{
|
|
|
|
ObjectClass *oc;
|
|
|
|
char *typename;
|
|
|
|
|
|
|
|
typename = mips_cpu_type_name(cpu_model);
|
|
|
|
oc = object_class_by_name(typename);
|
|
|
|
g_free(typename);
|
|
|
|
return oc;
|
|
|
|
}
|
|
|
|
|
2020-10-12 12:57:53 +03:00
|
|
|
static Property mips_cpu_properties[] = {
|
|
|
|
/* CP0 timer running at half the clock of the CPU */
|
|
|
|
DEFINE_PROP_UINT32("cp0-count-rate", MIPSCPU, cp0_count_rate,
|
|
|
|
CP0_COUNT_RATE_DEFAULT),
|
|
|
|
DEFINE_PROP_END_OF_LIST()
|
|
|
|
};
|
|
|
|
|
2012-04-16 01:29:19 +04:00
|
|
|
static void mips_cpu_class_init(ObjectClass *c, void *data)
|
|
|
|
{
|
|
|
|
MIPSCPUClass *mcc = MIPS_CPU_CLASS(c);
|
|
|
|
CPUClass *cc = CPU_CLASS(c);
|
2013-01-16 06:48:37 +04:00
|
|
|
DeviceClass *dc = DEVICE_CLASS(c);
|
|
|
|
|
2018-01-14 05:04:12 +03:00
|
|
|
device_class_set_parent_realize(dc, mips_cpu_realizefn,
|
|
|
|
&mcc->parent_realize);
|
cpu: Use DeviceClass reset instead of a special CPUClass reset
The CPUClass has a 'reset' method. This is a legacy from when
TYPE_CPU used not to inherit from TYPE_DEVICE. We don't need it any
more, as we can simply use the TYPE_DEVICE reset. The 'cpu_reset()'
function is kept as the API which most places use to reset a CPU; it
is now a wrapper which calls device_cold_reset() and then the
tracepoint function.
This change should not cause CPU objects to be reset more often
than they are at the moment, because:
* nobody is directly calling device_cold_reset() or
qdev_reset_all() on CPU objects
* no CPU object is on a qbus, so they will not be reset either
by somebody calling qbus_reset_all()/bus_cold_reset(), or
by the main "reset sysbus and everything in the qbus tree"
reset that most devices are reset by
Note that this does not change the need for each machine or whatever
to use qemu_register_reset() to arrange to call cpu_reset() -- that
is necessary because CPU objects are not on any qbus, so they don't
get reset when the qbus tree rooted at the sysbus bus is reset, and
this isn't being changed here.
All the changes to the files under target/ were made using the
included Coccinelle script, except:
(1) the deletion of the now-inaccurate and not terribly useful
"CPUClass::reset" comments was done with a perl one-liner afterwards:
perl -n -i -e '/ CPUClass::reset/ or print' target/*/*.c
(2) this bit of the s390 change was done by hand, because the
Coccinelle script is not sophisticated enough to handle the
parent_reset call being inside another function:
| @@ -96,8 +96,9 @@ static void s390_cpu_reset(CPUState *s, cpu_reset_type type)
| S390CPU *cpu = S390_CPU(s);
| S390CPUClass *scc = S390_CPU_GET_CLASS(cpu);
| CPUS390XState *env = &cpu->env;
|+ DeviceState *dev = DEVICE(s);
|
|- scc->parent_reset(s);
|+ scc->parent_reset(dev);
| cpu->env.sigp_order = 0;
| s390_cpu_set_state(S390_CPU_STATE_STOPPED, cpu);
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20200303100511.5498-1-peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2020-03-03 13:05:11 +03:00
|
|
|
device_class_set_parent_reset(dc, mips_cpu_reset, &mcc->parent_reset);
|
2020-10-12 12:57:53 +03:00
|
|
|
device_class_set_props(dc, mips_cpu_properties);
|
2013-02-02 13:57:51 +04:00
|
|
|
|
2017-09-20 22:49:33 +03:00
|
|
|
cc->class_by_name = mips_cpu_class_by_name;
|
2013-08-25 20:53:55 +04:00
|
|
|
cc->has_work = mips_cpu_has_work;
|
2013-02-02 13:57:51 +04:00
|
|
|
cc->do_interrupt = mips_cpu_do_interrupt;
|
2014-09-13 20:45:29 +04:00
|
|
|
cc->cpu_exec_interrupt = mips_cpu_exec_interrupt;
|
2013-05-27 03:33:50 +04:00
|
|
|
cc->dump_state = mips_cpu_dump_state;
|
2013-06-21 21:09:18 +04:00
|
|
|
cc->set_pc = mips_cpu_set_pc;
|
2013-06-28 21:31:32 +04:00
|
|
|
cc->synchronize_from_tb = mips_cpu_synchronize_from_tb;
|
2013-06-29 06:18:45 +04:00
|
|
|
cc->gdb_read_register = mips_cpu_gdb_read_register;
|
|
|
|
cc->gdb_write_register = mips_cpu_gdb_write_register;
|
2019-04-02 12:22:13 +03:00
|
|
|
#ifndef CONFIG_USER_ONLY
|
2019-08-02 19:04:57 +03:00
|
|
|
cc->do_transaction_failed = mips_cpu_do_transaction_failed;
|
2014-03-28 21:14:58 +04:00
|
|
|
cc->do_unaligned_access = mips_cpu_do_unaligned_access;
|
2013-06-29 20:55:54 +04:00
|
|
|
cc->get_phys_page_debug = mips_cpu_get_phys_page_debug;
|
2015-02-20 16:07:44 +03:00
|
|
|
cc->vmsd = &vmstate_mips_cpu;
|
2013-06-29 20:55:54 +04:00
|
|
|
#endif
|
2015-07-12 05:00:04 +03:00
|
|
|
cc->disas_set_info = mips_cpu_disas_set_info;
|
2017-10-26 16:58:14 +03:00
|
|
|
#ifdef CONFIG_TCG
|
2017-10-16 05:02:42 +03:00
|
|
|
cc->tcg_initialize = mips_tcg_init;
|
2019-04-02 12:22:13 +03:00
|
|
|
cc->tlb_fill = mips_cpu_tlb_fill;
|
2017-10-26 16:58:14 +03:00
|
|
|
#endif
|
2013-06-29 01:18:47 +04:00
|
|
|
|
|
|
|
cc->gdb_num_core_regs = 73;
|
2014-09-12 22:04:17 +04:00
|
|
|
cc->gdb_stop_before_watchpoint = true;
|
2012-04-16 01:29:19 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
static const TypeInfo mips_cpu_type_info = {
|
|
|
|
.name = TYPE_MIPS_CPU,
|
|
|
|
.parent = TYPE_CPU,
|
|
|
|
.instance_size = sizeof(MIPSCPU),
|
2012-04-16 04:37:56 +04:00
|
|
|
.instance_init = mips_cpu_initfn,
|
2017-09-20 22:49:33 +03:00
|
|
|
.abstract = true,
|
2012-04-16 01:29:19 +04:00
|
|
|
.class_size = sizeof(MIPSCPUClass),
|
|
|
|
.class_init = mips_cpu_class_init,
|
|
|
|
};
|
|
|
|
|
2017-09-20 22:49:33 +03:00
|
|
|
static void mips_cpu_cpudef_class_init(ObjectClass *oc, void *data)
|
|
|
|
{
|
|
|
|
MIPSCPUClass *mcc = MIPS_CPU_CLASS(oc);
|
|
|
|
mcc->cpu_def = data;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void mips_register_cpudef_type(const struct mips_def_t *def)
|
|
|
|
{
|
|
|
|
char *typename = mips_cpu_type_name(def->name);
|
|
|
|
TypeInfo ti = {
|
|
|
|
.name = typename,
|
|
|
|
.parent = TYPE_MIPS_CPU,
|
|
|
|
.class_init = mips_cpu_cpudef_class_init,
|
|
|
|
.class_data = (void *)def,
|
|
|
|
};
|
|
|
|
|
|
|
|
type_register(&ti);
|
|
|
|
g_free(typename);
|
|
|
|
}
|
|
|
|
|
2012-04-16 01:29:19 +04:00
|
|
|
static void mips_cpu_register_types(void)
|
|
|
|
{
|
2017-09-20 22:49:33 +03:00
|
|
|
int i;
|
|
|
|
|
2012-04-16 01:29:19 +04:00
|
|
|
type_register_static(&mips_cpu_type_info);
|
2017-09-20 22:49:33 +03:00
|
|
|
for (i = 0; i < mips_defs_number; i++) {
|
|
|
|
mips_register_cpudef_type(&mips_defs[i]);
|
|
|
|
}
|
2012-04-16 01:29:19 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
type_init(mips_cpu_register_types)
|
2020-10-12 12:57:55 +03:00
|
|
|
|
2020-12-07 00:07:34 +03:00
|
|
|
static void mips_cpu_add_definition(gpointer data, gpointer user_data)
|
|
|
|
{
|
|
|
|
ObjectClass *oc = data;
|
|
|
|
CpuDefinitionInfoList **cpu_list = user_data;
|
|
|
|
CpuDefinitionInfo *info;
|
|
|
|
const char *typename;
|
|
|
|
|
|
|
|
typename = object_class_get_name(oc);
|
|
|
|
info = g_malloc0(sizeof(*info));
|
|
|
|
info->name = g_strndup(typename,
|
|
|
|
strlen(typename) - strlen("-" TYPE_MIPS_CPU));
|
|
|
|
info->q_typename = g_strdup(typename);
|
|
|
|
|
2020-11-13 04:13:37 +03:00
|
|
|
QAPI_LIST_PREPEND(*cpu_list, info);
|
2020-12-07 00:07:34 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
|
|
|
|
{
|
|
|
|
CpuDefinitionInfoList *cpu_list = NULL;
|
|
|
|
GSList *list;
|
|
|
|
|
|
|
|
list = object_class_get_list(TYPE_MIPS_CPU, false);
|
|
|
|
g_slist_foreach(list, mips_cpu_add_definition, &cpu_list);
|
|
|
|
g_slist_free(list);
|
|
|
|
|
|
|
|
return cpu_list;
|
|
|
|
}
|
|
|
|
|
2020-10-12 12:57:55 +03:00
|
|
|
/* Could be used by generic CPU object */
|
|
|
|
MIPSCPU *mips_cpu_create_with_clock(const char *cpu_type, Clock *cpu_refclk)
|
|
|
|
{
|
|
|
|
DeviceState *cpu;
|
|
|
|
|
|
|
|
cpu = DEVICE(object_new(cpu_type));
|
|
|
|
qdev_connect_clock_in(cpu, "clk-in", cpu_refclk);
|
|
|
|
qdev_realize(cpu, NULL, &error_abort);
|
|
|
|
|
|
|
|
return MIPS_CPU(cpu);
|
|
|
|
}
|
2020-12-08 00:33:22 +03:00
|
|
|
|
|
|
|
bool cpu_supports_isa(const CPUMIPSState *env, uint64_t isa_mask)
|
|
|
|
{
|
|
|
|
return (env->cpu_model->insn_flags & isa_mask) != 0;
|
|
|
|
}
|
2020-12-07 00:03:35 +03:00
|
|
|
|
|
|
|
bool cpu_type_supports_isa(const char *cpu_type, uint64_t isa)
|
|
|
|
{
|
|
|
|
const MIPSCPUClass *mcc = MIPS_CPU_CLASS(object_class_by_name(cpu_type));
|
|
|
|
return (mcc->cpu_def->insn_flags & isa) != 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool cpu_type_supports_cps_smp(const char *cpu_type)
|
|
|
|
{
|
|
|
|
const MIPSCPUClass *mcc = MIPS_CPU_CLASS(object_class_by_name(cpu_type));
|
|
|
|
return (mcc->cpu_def->CP0_Config3 & (1 << CP0C3_CMGCR)) != 0;
|
|
|
|
}
|