target/mips: Move cpu definitions, reset() and realize() to cpu.c
Nothing TCG specific there, move to common cpu code. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201206233949.3783184-16-f4bug@amsat.org>
This commit is contained in:
Philippe Mathieu-Daudé
parent
a10b453a52
commit
c20cf02bbd
@ -20,6 +20,7 @@
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#include "qemu/osdep.h"
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#include "qemu/cutils.h"
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#include "qemu/qemu-print.h"
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#include "qapi/error.h"
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#include "cpu.h"
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#include "internal.h"
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@ -30,6 +31,7 @@
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#include "exec/exec-all.h"
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#include "hw/qdev-properties.h"
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#include "hw/qdev-clock.h"
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#include "hw/semihosting/semihost.h"
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#include "qapi/qapi-commands-machine-target.h"
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static void mips_cpu_set_pc(CPUState *cs, vaddr value)
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@ -100,6 +102,247 @@ static bool mips_cpu_has_work(CPUState *cs)
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return has_work;
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}
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#include "translate_init.c.inc"
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static void cpu_mips_realize_env(CPUMIPSState *env)
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{
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env->exception_base = (int32_t)0xBFC00000;
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#ifndef CONFIG_USER_ONLY
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mmu_init(env, env->cpu_model);
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#endif
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fpu_init(env, env->cpu_model);
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mvp_init(env);
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}
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/* TODO QOM'ify CPU reset and remove */
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static void cpu_state_reset(CPUMIPSState *env)
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{
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CPUState *cs = env_cpu(env);
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/* Reset registers to their default values */
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env->CP0_PRid = env->cpu_model->CP0_PRid;
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env->CP0_Config0 = env->cpu_model->CP0_Config0;
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#ifdef TARGET_WORDS_BIGENDIAN
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env->CP0_Config0 |= (1 << CP0C0_BE);
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#endif
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env->CP0_Config1 = env->cpu_model->CP0_Config1;
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env->CP0_Config2 = env->cpu_model->CP0_Config2;
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env->CP0_Config3 = env->cpu_model->CP0_Config3;
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env->CP0_Config4 = env->cpu_model->CP0_Config4;
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env->CP0_Config4_rw_bitmask = env->cpu_model->CP0_Config4_rw_bitmask;
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env->CP0_Config5 = env->cpu_model->CP0_Config5;
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env->CP0_Config5_rw_bitmask = env->cpu_model->CP0_Config5_rw_bitmask;
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env->CP0_Config6 = env->cpu_model->CP0_Config6;
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env->CP0_Config6_rw_bitmask = env->cpu_model->CP0_Config6_rw_bitmask;
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env->CP0_Config7 = env->cpu_model->CP0_Config7;
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env->CP0_Config7_rw_bitmask = env->cpu_model->CP0_Config7_rw_bitmask;
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env->CP0_LLAddr_rw_bitmask = env->cpu_model->CP0_LLAddr_rw_bitmask
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<< env->cpu_model->CP0_LLAddr_shift;
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env->CP0_LLAddr_shift = env->cpu_model->CP0_LLAddr_shift;
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env->SYNCI_Step = env->cpu_model->SYNCI_Step;
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env->CCRes = env->cpu_model->CCRes;
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env->CP0_Status_rw_bitmask = env->cpu_model->CP0_Status_rw_bitmask;
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env->CP0_TCStatus_rw_bitmask = env->cpu_model->CP0_TCStatus_rw_bitmask;
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env->CP0_SRSCtl = env->cpu_model->CP0_SRSCtl;
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env->current_tc = 0;
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env->SEGBITS = env->cpu_model->SEGBITS;
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env->SEGMask = (target_ulong)((1ULL << env->cpu_model->SEGBITS) - 1);
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#if defined(TARGET_MIPS64)
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if (env->cpu_model->insn_flags & ISA_MIPS3) {
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env->SEGMask |= 3ULL << 62;
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}
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#endif
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env->PABITS = env->cpu_model->PABITS;
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env->CP0_SRSConf0_rw_bitmask = env->cpu_model->CP0_SRSConf0_rw_bitmask;
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env->CP0_SRSConf0 = env->cpu_model->CP0_SRSConf0;
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env->CP0_SRSConf1_rw_bitmask = env->cpu_model->CP0_SRSConf1_rw_bitmask;
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env->CP0_SRSConf1 = env->cpu_model->CP0_SRSConf1;
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env->CP0_SRSConf2_rw_bitmask = env->cpu_model->CP0_SRSConf2_rw_bitmask;
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env->CP0_SRSConf2 = env->cpu_model->CP0_SRSConf2;
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env->CP0_SRSConf3_rw_bitmask = env->cpu_model->CP0_SRSConf3_rw_bitmask;
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env->CP0_SRSConf3 = env->cpu_model->CP0_SRSConf3;
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env->CP0_SRSConf4_rw_bitmask = env->cpu_model->CP0_SRSConf4_rw_bitmask;
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env->CP0_SRSConf4 = env->cpu_model->CP0_SRSConf4;
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env->CP0_PageGrain_rw_bitmask = env->cpu_model->CP0_PageGrain_rw_bitmask;
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env->CP0_PageGrain = env->cpu_model->CP0_PageGrain;
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env->CP0_EBaseWG_rw_bitmask = env->cpu_model->CP0_EBaseWG_rw_bitmask;
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env->active_fpu.fcr0 = env->cpu_model->CP1_fcr0;
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env->active_fpu.fcr31_rw_bitmask = env->cpu_model->CP1_fcr31_rw_bitmask;
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env->active_fpu.fcr31 = env->cpu_model->CP1_fcr31;
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env->msair = env->cpu_model->MSAIR;
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env->insn_flags = env->cpu_model->insn_flags;
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#if defined(CONFIG_USER_ONLY)
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env->CP0_Status = (MIPS_HFLAG_UM << CP0St_KSU);
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# ifdef TARGET_MIPS64
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/* Enable 64-bit register mode. */
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env->CP0_Status |= (1 << CP0St_PX);
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# endif
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# ifdef TARGET_ABI_MIPSN64
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/* Enable 64-bit address mode. */
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env->CP0_Status |= (1 << CP0St_UX);
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# endif
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/*
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* Enable access to the CPUNum, SYNCI_Step, CC, and CCRes RDHWR
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* hardware registers.
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*/
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env->CP0_HWREna |= 0x0000000F;
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if (env->CP0_Config1 & (1 << CP0C1_FP)) {
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env->CP0_Status |= (1 << CP0St_CU1);
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}
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if (env->CP0_Config3 & (1 << CP0C3_DSPP)) {
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env->CP0_Status |= (1 << CP0St_MX);
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}
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# if defined(TARGET_MIPS64)
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/* For MIPS64, init FR bit to 1 if FPU unit is there and bit is writable. */
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if ((env->CP0_Config1 & (1 << CP0C1_FP)) &&
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(env->CP0_Status_rw_bitmask & (1 << CP0St_FR))) {
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env->CP0_Status |= (1 << CP0St_FR);
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}
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# endif
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#else /* !CONFIG_USER_ONLY */
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if (env->hflags & MIPS_HFLAG_BMASK) {
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/*
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* If the exception was raised from a delay slot,
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* come back to the jump.
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*/
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env->CP0_ErrorEPC = (env->active_tc.PC
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- (env->hflags & MIPS_HFLAG_B16 ? 2 : 4));
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} else {
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env->CP0_ErrorEPC = env->active_tc.PC;
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}
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env->active_tc.PC = env->exception_base;
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env->CP0_Random = env->tlb->nb_tlb - 1;
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env->tlb->tlb_in_use = env->tlb->nb_tlb;
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env->CP0_Wired = 0;
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env->CP0_GlobalNumber = (cs->cpu_index & 0xFF) << CP0GN_VPId;
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env->CP0_EBase = (cs->cpu_index & 0x3FF);
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if (mips_um_ksegs_enabled()) {
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env->CP0_EBase |= 0x40000000;
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} else {
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env->CP0_EBase |= (int32_t)0x80000000;
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}
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if (env->CP0_Config3 & (1 << CP0C3_CMGCR)) {
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env->CP0_CMGCRBase = 0x1fbf8000 >> 4;
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}
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env->CP0_EntryHi_ASID_mask = (env->CP0_Config5 & (1 << CP0C5_MI)) ?
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0x0 : (env->CP0_Config4 & (1 << CP0C4_AE)) ? 0x3ff : 0xff;
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env->CP0_Status = (1 << CP0St_BEV) | (1 << CP0St_ERL);
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/*
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* Vectored interrupts not implemented, timer on int 7,
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* no performance counters.
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*/
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env->CP0_IntCtl = 0xe0000000;
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{
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int i;
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for (i = 0; i < 7; i++) {
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env->CP0_WatchLo[i] = 0;
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env->CP0_WatchHi[i] = 0x80000000;
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}
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env->CP0_WatchLo[7] = 0;
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env->CP0_WatchHi[7] = 0;
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}
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/* Count register increments in debug mode, EJTAG version 1 */
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env->CP0_Debug = (1 << CP0DB_CNT) | (0x1 << CP0DB_VER);
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cpu_mips_store_count(env, 1);
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if (ase_mt_available(env)) {
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int i;
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/* Only TC0 on VPE 0 starts as active. */
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for (i = 0; i < ARRAY_SIZE(env->tcs); i++) {
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env->tcs[i].CP0_TCBind = cs->cpu_index << CP0TCBd_CurVPE;
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env->tcs[i].CP0_TCHalt = 1;
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}
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env->active_tc.CP0_TCHalt = 1;
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cs->halted = 1;
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if (cs->cpu_index == 0) {
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/* VPE0 starts up enabled. */
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env->mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP);
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env->CP0_VPEConf0 |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
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/* TC0 starts up unhalted. */
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cs->halted = 0;
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env->active_tc.CP0_TCHalt = 0;
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env->tcs[0].CP0_TCHalt = 0;
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/* With thread 0 active. */
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env->active_tc.CP0_TCStatus = (1 << CP0TCSt_A);
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env->tcs[0].CP0_TCStatus = (1 << CP0TCSt_A);
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}
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}
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/*
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* Configure default legacy segmentation control. We use this regardless of
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* whether segmentation control is presented to the guest.
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*/
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/* KSeg3 (seg0 0xE0000000..0xFFFFFFFF) */
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env->CP0_SegCtl0 = (CP0SC_AM_MK << CP0SC_AM);
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/* KSeg2 (seg1 0xC0000000..0xDFFFFFFF) */
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env->CP0_SegCtl0 |= ((CP0SC_AM_MSK << CP0SC_AM)) << 16;
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/* KSeg1 (seg2 0xA0000000..0x9FFFFFFF) */
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env->CP0_SegCtl1 = (0 << CP0SC_PA) | (CP0SC_AM_UK << CP0SC_AM) |
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(2 << CP0SC_C);
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/* KSeg0 (seg3 0x80000000..0x9FFFFFFF) */
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env->CP0_SegCtl1 |= ((0 << CP0SC_PA) | (CP0SC_AM_UK << CP0SC_AM) |
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(3 << CP0SC_C)) << 16;
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/* USeg (seg4 0x40000000..0x7FFFFFFF) */
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env->CP0_SegCtl2 = (2 << CP0SC_PA) | (CP0SC_AM_MUSK << CP0SC_AM) |
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(1 << CP0SC_EU) | (2 << CP0SC_C);
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/* USeg (seg5 0x00000000..0x3FFFFFFF) */
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env->CP0_SegCtl2 |= ((0 << CP0SC_PA) | (CP0SC_AM_MUSK << CP0SC_AM) |
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(1 << CP0SC_EU) | (2 << CP0SC_C)) << 16;
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/* XKPhys (note, SegCtl2.XR = 0, so XAM won't be used) */
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env->CP0_SegCtl1 |= (CP0SC_AM_UK << CP0SC1_XAM);
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#endif /* !CONFIG_USER_ONLY */
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if ((env->insn_flags & ISA_MIPS32R6) &&
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(env->active_fpu.fcr0 & (1 << FCR0_F64))) {
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/* Status.FR = 0 mode in 64-bit FPU not allowed in R6 */
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env->CP0_Status |= (1 << CP0St_FR);
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}
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if (env->insn_flags & ISA_MIPS32R6) {
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/* PTW = 1 */
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env->CP0_PWSize = 0x40;
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/* GDI = 12 */
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/* UDI = 12 */
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/* MDI = 12 */
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/* PRI = 12 */
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/* PTEI = 2 */
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env->CP0_PWField = 0x0C30C302;
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} else {
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/* GDI = 0 */
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/* UDI = 0 */
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/* MDI = 0 */
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/* PRI = 0 */
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/* PTEI = 2 */
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env->CP0_PWField = 0x02;
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}
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if (env->CP0_Config3 & (1 << CP0C3_ISA) & (1 << (CP0C3_ISA + 1))) {
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/* microMIPS on reset when Config3.ISA is 3 */
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env->hflags |= MIPS_HFLAG_M16;
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}
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/* MSA */
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if (env->CP0_Config3 & (1 << CP0C3_MSAP)) {
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msa_reset(env);
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}
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compute_hflags(env);
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restore_fp_status(env);
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restore_pamask(env);
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cs->exception_index = EXCP_NONE;
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if (semihosting_get_argc()) {
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/* UHI interface can be used to obtain argc and argv */
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env->active_tc.gpr[4] = -1;
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}
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}
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static void mips_cpu_reset(DeviceState *dev)
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{
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CPUState *s = CPU(dev);
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@ -207,10 +207,6 @@ static inline bool cpu_mips_hw_interrupts_pending(CPUMIPSState *env)
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void mips_tcg_init(void);
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/* TODO QOM'ify CPU reset and remove */
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void cpu_state_reset(CPUMIPSState *s);
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void cpu_mips_realize_env(CPUMIPSState *env);
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/* cp0_timer.c */
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uint32_t cpu_mips_get_count(CPUMIPSState *env);
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void cpu_mips_store_count(CPUMIPSState *env, uint32_t value);
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@ -31753,246 +31753,6 @@ void mips_tcg_init(void)
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#endif
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}
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#include "translate_init.c.inc"
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void cpu_mips_realize_env(CPUMIPSState *env)
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{
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env->exception_base = (int32_t)0xBFC00000;
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#ifndef CONFIG_USER_ONLY
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mmu_init(env, env->cpu_model);
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#endif
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fpu_init(env, env->cpu_model);
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mvp_init(env);
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}
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void cpu_state_reset(CPUMIPSState *env)
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{
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CPUState *cs = env_cpu(env);
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/* Reset registers to their default values */
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env->CP0_PRid = env->cpu_model->CP0_PRid;
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env->CP0_Config0 = env->cpu_model->CP0_Config0;
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#ifdef TARGET_WORDS_BIGENDIAN
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env->CP0_Config0 |= (1 << CP0C0_BE);
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#endif
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env->CP0_Config1 = env->cpu_model->CP0_Config1;
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env->CP0_Config2 = env->cpu_model->CP0_Config2;
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env->CP0_Config3 = env->cpu_model->CP0_Config3;
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env->CP0_Config4 = env->cpu_model->CP0_Config4;
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env->CP0_Config4_rw_bitmask = env->cpu_model->CP0_Config4_rw_bitmask;
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env->CP0_Config5 = env->cpu_model->CP0_Config5;
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env->CP0_Config5_rw_bitmask = env->cpu_model->CP0_Config5_rw_bitmask;
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env->CP0_Config6 = env->cpu_model->CP0_Config6;
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env->CP0_Config6_rw_bitmask = env->cpu_model->CP0_Config6_rw_bitmask;
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env->CP0_Config7 = env->cpu_model->CP0_Config7;
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env->CP0_Config7_rw_bitmask = env->cpu_model->CP0_Config7_rw_bitmask;
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env->CP0_LLAddr_rw_bitmask = env->cpu_model->CP0_LLAddr_rw_bitmask
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<< env->cpu_model->CP0_LLAddr_shift;
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env->CP0_LLAddr_shift = env->cpu_model->CP0_LLAddr_shift;
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env->SYNCI_Step = env->cpu_model->SYNCI_Step;
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env->CCRes = env->cpu_model->CCRes;
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env->CP0_Status_rw_bitmask = env->cpu_model->CP0_Status_rw_bitmask;
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env->CP0_TCStatus_rw_bitmask = env->cpu_model->CP0_TCStatus_rw_bitmask;
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env->CP0_SRSCtl = env->cpu_model->CP0_SRSCtl;
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env->current_tc = 0;
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env->SEGBITS = env->cpu_model->SEGBITS;
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env->SEGMask = (target_ulong)((1ULL << env->cpu_model->SEGBITS) - 1);
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#if defined(TARGET_MIPS64)
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if (env->cpu_model->insn_flags & ISA_MIPS3) {
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env->SEGMask |= 3ULL << 62;
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}
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#endif
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env->PABITS = env->cpu_model->PABITS;
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env->CP0_SRSConf0_rw_bitmask = env->cpu_model->CP0_SRSConf0_rw_bitmask;
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env->CP0_SRSConf0 = env->cpu_model->CP0_SRSConf0;
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env->CP0_SRSConf1_rw_bitmask = env->cpu_model->CP0_SRSConf1_rw_bitmask;
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env->CP0_SRSConf1 = env->cpu_model->CP0_SRSConf1;
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env->CP0_SRSConf2_rw_bitmask = env->cpu_model->CP0_SRSConf2_rw_bitmask;
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env->CP0_SRSConf2 = env->cpu_model->CP0_SRSConf2;
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env->CP0_SRSConf3_rw_bitmask = env->cpu_model->CP0_SRSConf3_rw_bitmask;
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env->CP0_SRSConf3 = env->cpu_model->CP0_SRSConf3;
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env->CP0_SRSConf4_rw_bitmask = env->cpu_model->CP0_SRSConf4_rw_bitmask;
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env->CP0_SRSConf4 = env->cpu_model->CP0_SRSConf4;
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env->CP0_PageGrain_rw_bitmask = env->cpu_model->CP0_PageGrain_rw_bitmask;
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env->CP0_PageGrain = env->cpu_model->CP0_PageGrain;
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env->CP0_EBaseWG_rw_bitmask = env->cpu_model->CP0_EBaseWG_rw_bitmask;
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env->active_fpu.fcr0 = env->cpu_model->CP1_fcr0;
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env->active_fpu.fcr31_rw_bitmask = env->cpu_model->CP1_fcr31_rw_bitmask;
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env->active_fpu.fcr31 = env->cpu_model->CP1_fcr31;
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env->msair = env->cpu_model->MSAIR;
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env->insn_flags = env->cpu_model->insn_flags;
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#if defined(CONFIG_USER_ONLY)
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env->CP0_Status = (MIPS_HFLAG_UM << CP0St_KSU);
|
||||
# ifdef TARGET_MIPS64
|
||||
/* Enable 64-bit register mode. */
|
||||
env->CP0_Status |= (1 << CP0St_PX);
|
||||
# endif
|
||||
# ifdef TARGET_ABI_MIPSN64
|
||||
/* Enable 64-bit address mode. */
|
||||
env->CP0_Status |= (1 << CP0St_UX);
|
||||
# endif
|
||||
/*
|
||||
* Enable access to the CPUNum, SYNCI_Step, CC, and CCRes RDHWR
|
||||
* hardware registers.
|
||||
*/
|
||||
env->CP0_HWREna |= 0x0000000F;
|
||||
if (env->CP0_Config1 & (1 << CP0C1_FP)) {
|
||||
env->CP0_Status |= (1 << CP0St_CU1);
|
||||
}
|
||||
if (env->CP0_Config3 & (1 << CP0C3_DSPP)) {
|
||||
env->CP0_Status |= (1 << CP0St_MX);
|
||||
}
|
||||
# if defined(TARGET_MIPS64)
|
||||
/* For MIPS64, init FR bit to 1 if FPU unit is there and bit is writable. */
|
||||
if ((env->CP0_Config1 & (1 << CP0C1_FP)) &&
|
||||
(env->CP0_Status_rw_bitmask & (1 << CP0St_FR))) {
|
||||
env->CP0_Status |= (1 << CP0St_FR);
|
||||
}
|
||||
# endif
|
||||
#else
|
||||
if (env->hflags & MIPS_HFLAG_BMASK) {
|
||||
/*
|
||||
* If the exception was raised from a delay slot,
|
||||
* come back to the jump.
|
||||
*/
|
||||
env->CP0_ErrorEPC = (env->active_tc.PC
|
||||
- (env->hflags & MIPS_HFLAG_B16 ? 2 : 4));
|
||||
} else {
|
||||
env->CP0_ErrorEPC = env->active_tc.PC;
|
||||
}
|
||||
env->active_tc.PC = env->exception_base;
|
||||
env->CP0_Random = env->tlb->nb_tlb - 1;
|
||||
env->tlb->tlb_in_use = env->tlb->nb_tlb;
|
||||
env->CP0_Wired = 0;
|
||||
env->CP0_GlobalNumber = (cs->cpu_index & 0xFF) << CP0GN_VPId;
|
||||
env->CP0_EBase = (cs->cpu_index & 0x3FF);
|
||||
if (mips_um_ksegs_enabled()) {
|
||||
env->CP0_EBase |= 0x40000000;
|
||||
} else {
|
||||
env->CP0_EBase |= (int32_t)0x80000000;
|
||||
}
|
||||
if (env->CP0_Config3 & (1 << CP0C3_CMGCR)) {
|
||||
env->CP0_CMGCRBase = 0x1fbf8000 >> 4;
|
||||
}
|
||||
env->CP0_EntryHi_ASID_mask = (env->CP0_Config5 & (1 << CP0C5_MI)) ?
|
||||
0x0 : (env->CP0_Config4 & (1 << CP0C4_AE)) ? 0x3ff : 0xff;
|
||||
env->CP0_Status = (1 << CP0St_BEV) | (1 << CP0St_ERL);
|
||||
/*
|
||||
* Vectored interrupts not implemented, timer on int 7,
|
||||
* no performance counters.
|
||||
*/
|
||||
env->CP0_IntCtl = 0xe0000000;
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < 7; i++) {
|
||||
env->CP0_WatchLo[i] = 0;
|
||||
env->CP0_WatchHi[i] = 0x80000000;
|
||||
}
|
||||
env->CP0_WatchLo[7] = 0;
|
||||
env->CP0_WatchHi[7] = 0;
|
||||
}
|
||||
/* Count register increments in debug mode, EJTAG version 1 */
|
||||
env->CP0_Debug = (1 << CP0DB_CNT) | (0x1 << CP0DB_VER);
|
||||
|
||||
cpu_mips_store_count(env, 1);
|
||||
|
||||
if (ase_mt_available(env)) {
|
||||
int i;
|
||||
|
||||
/* Only TC0 on VPE 0 starts as active. */
|
||||
for (i = 0; i < ARRAY_SIZE(env->tcs); i++) {
|
||||
env->tcs[i].CP0_TCBind = cs->cpu_index << CP0TCBd_CurVPE;
|
||||
env->tcs[i].CP0_TCHalt = 1;
|
||||
}
|
||||
env->active_tc.CP0_TCHalt = 1;
|
||||
cs->halted = 1;
|
||||
|
||||
if (cs->cpu_index == 0) {
|
||||
/* VPE0 starts up enabled. */
|
||||
env->mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP);
|
||||
env->CP0_VPEConf0 |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
|
||||
|
||||
/* TC0 starts up unhalted. */
|
||||
cs->halted = 0;
|
||||
env->active_tc.CP0_TCHalt = 0;
|
||||
env->tcs[0].CP0_TCHalt = 0;
|
||||
/* With thread 0 active. */
|
||||
env->active_tc.CP0_TCStatus = (1 << CP0TCSt_A);
|
||||
env->tcs[0].CP0_TCStatus = (1 << CP0TCSt_A);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Configure default legacy segmentation control. We use this regardless of
|
||||
* whether segmentation control is presented to the guest.
|
||||
*/
|
||||
/* KSeg3 (seg0 0xE0000000..0xFFFFFFFF) */
|
||||
env->CP0_SegCtl0 = (CP0SC_AM_MK << CP0SC_AM);
|
||||
/* KSeg2 (seg1 0xC0000000..0xDFFFFFFF) */
|
||||
env->CP0_SegCtl0 |= ((CP0SC_AM_MSK << CP0SC_AM)) << 16;
|
||||
/* KSeg1 (seg2 0xA0000000..0x9FFFFFFF) */
|
||||
env->CP0_SegCtl1 = (0 << CP0SC_PA) | (CP0SC_AM_UK << CP0SC_AM) |
|
||||
(2 << CP0SC_C);
|
||||
/* KSeg0 (seg3 0x80000000..0x9FFFFFFF) */
|
||||
env->CP0_SegCtl1 |= ((0 << CP0SC_PA) | (CP0SC_AM_UK << CP0SC_AM) |
|
||||
(3 << CP0SC_C)) << 16;
|
||||
/* USeg (seg4 0x40000000..0x7FFFFFFF) */
|
||||
env->CP0_SegCtl2 = (2 << CP0SC_PA) | (CP0SC_AM_MUSK << CP0SC_AM) |
|
||||
(1 << CP0SC_EU) | (2 << CP0SC_C);
|
||||
/* USeg (seg5 0x00000000..0x3FFFFFFF) */
|
||||
env->CP0_SegCtl2 |= ((0 << CP0SC_PA) | (CP0SC_AM_MUSK << CP0SC_AM) |
|
||||
(1 << CP0SC_EU) | (2 << CP0SC_C)) << 16;
|
||||
/* XKPhys (note, SegCtl2.XR = 0, so XAM won't be used) */
|
||||
env->CP0_SegCtl1 |= (CP0SC_AM_UK << CP0SC1_XAM);
|
||||
#endif
|
||||
if ((env->insn_flags & ISA_MIPS32R6) &&
|
||||
(env->active_fpu.fcr0 & (1 << FCR0_F64))) {
|
||||
/* Status.FR = 0 mode in 64-bit FPU not allowed in R6 */
|
||||
env->CP0_Status |= (1 << CP0St_FR);
|
||||
}
|
||||
|
||||
if (env->insn_flags & ISA_MIPS32R6) {
|
||||
/* PTW = 1 */
|
||||
env->CP0_PWSize = 0x40;
|
||||
/* GDI = 12 */
|
||||
/* UDI = 12 */
|
||||
/* MDI = 12 */
|
||||
/* PRI = 12 */
|
||||
/* PTEI = 2 */
|
||||
env->CP0_PWField = 0x0C30C302;
|
||||
} else {
|
||||
/* GDI = 0 */
|
||||
/* UDI = 0 */
|
||||
/* MDI = 0 */
|
||||
/* PRI = 0 */
|
||||
/* PTEI = 2 */
|
||||
env->CP0_PWField = 0x02;
|
||||
}
|
||||
|
||||
if (env->CP0_Config3 & (1 << CP0C3_ISA) & (1 << (CP0C3_ISA + 1))) {
|
||||
/* microMIPS on reset when Config3.ISA is 3 */
|
||||
env->hflags |= MIPS_HFLAG_M16;
|
||||
}
|
||||
|
||||
/* MSA */
|
||||
if (env->CP0_Config3 & (1 << CP0C3_MSAP)) {
|
||||
msa_reset(env);
|
||||
}
|
||||
|
||||
compute_hflags(env);
|
||||
restore_fp_status(env);
|
||||
restore_pamask(env);
|
||||
cs->exception_index = EXCP_NONE;
|
||||
|
||||
if (semihosting_get_argc()) {
|
||||
/* UHI interface can be used to obtain argc and argv */
|
||||
env->active_tc.gpr[4] = -1;
|
||||
}
|
||||
}
|
||||
|
||||
void restore_state_to_opc(CPUMIPSState *env, TranslationBlock *tb,
|
||||
target_ulong *data)
|
||||
{
|
||||
|
||||
Loading…
Reference in New Issue
Block a user