2021-02-08 08:46:10 +03:00
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#!/usr/bin/env python3
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##
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Hexagon (target/hexagon) Remove gen_log_predicated_reg_write[_pair]
We assign the instruction destination register to hex_new_value[num]
instead of a TCG temp that gets copied back to hex_new_value[num].
We introduce new functions get_result_gpr[_pair] to facilitate getting
the proper destination register.
Since we preload hex_new_value for predicated instructions, we don't
need the check for slot_cancelled. So, we call gen_log_reg_write instead.
We update the helper function generation and gen_tcg.h to maintain the
disable-hexagon-idef-parser configuration.
Here is a simple example of the differences in the TCG code generated:
IN:
0x00400094: 0xf900c102 { if (P0) R2 = and(R0,R1) }
BEFORE
---- 00400094
mov_i32 slot_cancelled,$0x0
mov_i32 new_r2,r2
mov_i32 loc2,$0x0
and_i32 tmp0,p0,$0x1
brcond_i32 tmp0,$0x0,eq,$L1
and_i32 tmp0,r0,r1
mov_i32 loc2,tmp0
br $L2
set_label $L1
or_i32 slot_cancelled,slot_cancelled,$0x8
set_label $L2
and_i32 tmp0,slot_cancelled,$0x8
movcond_i32 new_r2,tmp0,$0x0,loc2,new_r2,eq
mov_i32 r2,new_r2
AFTER
---- 00400094
mov_i32 slot_cancelled,$0x0
mov_i32 new_r2,r2
and_i32 tmp0,p0,$0x1
brcond_i32 tmp0,$0x0,eq,$L1
and_i32 tmp0,r0,r1
mov_i32 new_r2,tmp0
br $L2
set_label $L1
or_i32 slot_cancelled,slot_cancelled,$0x8
set_label $L2
mov_i32 r2,new_r2
We'll remove the unnecessary manipulation of slot_cancelled in a
subsequent patch.
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Message-Id: <20230307025828.1612809-13-tsimpson@quicinc.com>
2023-03-07 05:58:26 +03:00
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## Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved.
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2021-02-08 08:46:10 +03:00
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; either version 2 of the License, or
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## (at your option) any later version.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, see <http://www.gnu.org/licenses/>.
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##
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import sys
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import re
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import string
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2023-03-20 12:25:33 +03:00
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behdict = {} # tag ->behavior
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semdict = {} # tag -> semantics
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attribdict = {} # tag -> attributes
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macros = {} # macro -> macro information...
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attribinfo = {} # Register information and misc
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tags = [] # list of all tags
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overrides = {} # tags with helper overrides
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idef_parser_enabled = {} # tags enabled for idef-parser
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2023-05-24 17:41:47 +03:00
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def bad_register(regtype, regid):
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raise Exception(f"Bad register parse: regtype '{regtype}' regid '{regid}'")
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# We should do this as a hash for performance,
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# but to keep order let's keep it as a list.
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def uniquify(seq):
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seen = set()
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seen_add = seen.add
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return [x for x in seq if x not in seen and not seen_add(x)]
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2023-03-20 12:25:33 +03:00
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regre = re.compile(r"((?<!DUP)[MNORCPQXSGVZA])([stuvwxyzdefg]+)([.]?[LlHh]?)(\d+S?)")
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2021-02-08 08:46:10 +03:00
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immre = re.compile(r"[#]([rRsSuUm])(\d+)(?:[:](\d+))?")
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2023-03-20 12:25:33 +03:00
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reg_or_immre = re.compile(
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r"(((?<!DUP)[MNRCOPQXSGVZA])([stuvwxyzdefg]+)"
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+ "([.]?[LlHh]?)(\d+S?))|([#]([rRsSuUm])(\d+)[:]?(\d+)?)"
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)
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relimmre = re.compile(r"[#]([rR])(\d+)(?:[:](\d+))?")
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absimmre = re.compile(r"[#]([sSuUm])(\d+)(?:[:](\d+))?")
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finished_macros = set()
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2023-03-20 12:25:33 +03:00
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def expand_macro_attribs(macro, allmac_re):
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if macro.key not in finished_macros:
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# Get a list of all things that might be macros
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l = allmac_re.findall(macro.beh)
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for submacro in l:
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if not submacro:
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continue
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if not macros[submacro]:
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2023-03-20 12:25:32 +03:00
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raise Exception(f"Couldn't find macro: <{l}>")
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macro.attribs |= expand_macro_attribs(macros[submacro], allmac_re)
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finished_macros.add(macro.key)
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return macro.attribs
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2023-03-20 12:25:33 +03:00
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2021-02-08 08:46:10 +03:00
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# When qemu needs an attribute that isn't in the imported files,
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# we'll add it here.
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def add_qemu_macro_attrib(name, attrib):
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macros[name].attribs.add(attrib)
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2023-03-20 12:25:33 +03:00
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immextre = re.compile(r"f(MUST_)?IMMEXT[(]([UuSsRr])")
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2022-11-08 19:29:01 +03:00
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def is_cond_jump(tag):
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if tag == "J2_rte":
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return False
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2023-03-20 12:25:33 +03:00
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if "A_HWLOOP0_END" in attribdict[tag] or "A_HWLOOP1_END" in attribdict[tag]:
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2022-11-08 19:29:01 +03:00
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return False
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2023-03-20 12:25:33 +03:00
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return re.compile(r"(if.*fBRANCH)|(if.*fJUMPR)").search(semdict[tag]) != None
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2022-11-08 19:29:01 +03:00
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def is_cond_call(tag):
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return re.compile(r"(if.*fCALL)").search(semdict[tag]) != None
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def calculate_attribs():
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add_qemu_macro_attrib("fREAD_PC", "A_IMPLICIT_READS_PC")
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add_qemu_macro_attrib("fTRAP", "A_IMPLICIT_READS_PC")
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add_qemu_macro_attrib("fWRITE_P0", "A_WRITES_PRED_REG")
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add_qemu_macro_attrib("fWRITE_P1", "A_WRITES_PRED_REG")
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add_qemu_macro_attrib("fWRITE_P2", "A_WRITES_PRED_REG")
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add_qemu_macro_attrib("fWRITE_P3", "A_WRITES_PRED_REG")
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add_qemu_macro_attrib("fSET_OVERFLOW", "A_IMPLICIT_WRITES_USR")
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add_qemu_macro_attrib("fSET_LPCFG", "A_IMPLICIT_WRITES_USR")
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add_qemu_macro_attrib("fLOAD", "A_SCALAR_LOAD")
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add_qemu_macro_attrib("fSTORE", "A_SCALAR_STORE")
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2023-04-28 02:00:01 +03:00
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add_qemu_macro_attrib('fLSBNEW0', 'A_IMPLICIT_READS_P0')
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add_qemu_macro_attrib('fLSBNEW0NOT', 'A_IMPLICIT_READS_P0')
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add_qemu_macro_attrib('fREAD_P0', 'A_IMPLICIT_READS_P0')
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add_qemu_macro_attrib('fLSBNEW1', 'A_IMPLICIT_READS_P1')
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add_qemu_macro_attrib('fLSBNEW1NOT', 'A_IMPLICIT_READS_P1')
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add_qemu_macro_attrib('fREAD_P3', 'A_IMPLICIT_READS_P3')
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2021-02-08 08:46:10 +03:00
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# Recurse down macros, find attributes from sub-macros
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macroValues = list(macros.values())
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allmacros_restr = "|".join(set([m.re.pattern for m in macroValues]))
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allmacros_re = re.compile(allmacros_restr)
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for macro in macroValues:
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expand_macro_attribs(macro, allmacros_re)
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# Append attributes to all instructions
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for tag in tags:
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for macname in allmacros_re.findall(semdict[tag]):
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if not macname:
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continue
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macro = macros[macname]
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attribdict[tag] |= set(macro.attribs)
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# Figure out which instructions write predicate registers
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tagregs = get_tagregs()
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for tag in tags:
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regs = tagregs[tag]
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for regtype, regid in regs:
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if regtype == "P" and is_written(regid):
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2023-03-20 12:25:33 +03:00
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attribdict[tag].add("A_WRITES_PRED_REG")
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2022-11-08 19:29:01 +03:00
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# Mark conditional jumps and calls
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# Not all instructions are properly marked with A_CONDEXEC
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for tag in tags:
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if is_cond_jump(tag) or is_cond_call(tag):
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attribdict[tag].add("A_CONDEXEC")
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2021-02-08 08:46:10 +03:00
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def SEMANTICS(tag, beh, sem):
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# print tag,beh,sem
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behdict[tag] = beh
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semdict[tag] = sem
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attribdict[tag] = set()
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tags.append(tag) # dicts have no order, this is for order
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def ATTRIBUTES(tag, attribstring):
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attribstring = attribstring.replace("ATTRIBS", "").replace("(", "").replace(")", "")
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if not attribstring:
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return
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attribs = attribstring.split(",")
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for attrib in attribs:
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attribdict[tag].add(attrib.strip())
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2023-03-20 12:25:33 +03:00
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class Macro(object):
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__slots__ = ["key", "name", "beh", "attribs", "re"]
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def __init__(self, name, beh, attribs):
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self.key = name
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self.name = name
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self.beh = beh
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self.attribs = set(attribs)
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self.re = re.compile("\\b" + name + "\\b")
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2023-03-20 12:25:33 +03:00
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def MACROATTRIB(macname, beh, attribstring):
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attribstring = attribstring.replace("(", "").replace(")", "")
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if attribstring:
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attribs = attribstring.split(",")
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else:
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attribs = []
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2023-03-20 12:25:33 +03:00
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macros[macname] = Macro(macname, beh, attribs)
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2023-05-24 17:41:47 +03:00
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def compute_tag_regs(tag, full):
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tagregs = regre.findall(behdict[tag])
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if not full:
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tagregs = map(lambda reg: reg[:2], tagregs)
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return uniquify(tagregs)
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2021-02-08 08:46:10 +03:00
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def compute_tag_immediates(tag):
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return uniquify(immre.findall(behdict[tag]))
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2023-03-20 12:25:33 +03:00
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2021-02-08 08:46:10 +03:00
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##
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## tagregs is the main data structure we'll use
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## tagregs[tag] will contain the registers used by an instruction
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## Within each entry, we'll use the regtype and regid fields
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## regtype can be one of the following
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## C control register
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## N new register value
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## P predicate register
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## R GPR register
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## M modifier register
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2021-05-19 00:45:18 +03:00
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## Q HVX predicate vector
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## V HVX vector register
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## O HVX new vector register
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## regid can be one of the following
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## d, e destination register
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## dd destination register pair
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## s, t, u, v, w source register
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## ss, tt, uu, vv source register pair
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## x, y read-write register
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## xx, yy read-write register pair
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##
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2023-05-24 17:41:47 +03:00
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def get_tagregs(full=False):
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compute_func = lambda tag: compute_tag_regs(tag, full)
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return dict(zip(tags, list(map(compute_func, tags))))
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def get_tagimms():
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return dict(zip(tags, list(map(compute_tag_immediates, tags))))
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def is_pair(regid):
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return len(regid) == 2
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def is_single(regid):
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return len(regid) == 1
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def is_written(regid):
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return regid[0] in "dexy"
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2023-03-20 12:25:33 +03:00
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def is_writeonly(regid):
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return regid[0] in "de"
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def is_read(regid):
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return regid[0] in "stuvwxy"
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def is_readwrite(regid):
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return regid[0] in "xy"
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def is_scalar_reg(regtype):
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return regtype in "RPC"
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2021-05-19 00:45:18 +03:00
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def is_hvx_reg(regtype):
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return regtype in "VQ"
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def is_old_val(regtype, regid, tag):
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return regtype + regid + "V" in semdict[tag]
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def is_new_val(regtype, regid, tag):
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return regtype + regid + "N" in semdict[tag]
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def need_slot(tag):
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if (
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2023-04-28 02:00:11 +03:00
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"A_CVI_SCATTER" not in attribdict[tag]
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and "A_CVI_GATHER" not in attribdict[tag]
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and ("A_STORE" in attribdict[tag]
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|
or "A_LOAD" in attribdict[tag])
|
2023-03-20 12:25:33 +03:00
|
|
|
):
|
2021-02-08 08:46:10 +03:00
|
|
|
return 1
|
|
|
|
else:
|
|
|
|
return 0
|
|
|
|
|
2023-03-20 12:25:33 +03:00
|
|
|
|
2021-02-08 08:46:10 +03:00
|
|
|
def need_part1(tag):
|
|
|
|
return re.compile(r"fPART1").search(semdict[tag])
|
|
|
|
|
2023-03-20 12:25:33 +03:00
|
|
|
|
2021-02-08 08:46:10 +03:00
|
|
|
def need_ea(tag):
|
|
|
|
return re.compile(r"\bEA\b").search(semdict[tag])
|
|
|
|
|
2023-03-20 12:25:33 +03:00
|
|
|
|
2022-11-08 19:29:00 +03:00
|
|
|
def need_PC(tag):
|
2023-03-20 12:25:33 +03:00
|
|
|
return "A_IMPLICIT_READS_PC" in attribdict[tag]
|
|
|
|
|
2022-11-08 19:29:00 +03:00
|
|
|
|
2022-11-08 19:29:01 +03:00
|
|
|
def helper_needs_next_PC(tag):
|
2023-03-20 12:25:33 +03:00
|
|
|
return "A_CALL" in attribdict[tag]
|
|
|
|
|
2022-11-08 19:29:01 +03:00
|
|
|
|
2022-11-08 19:28:59 +03:00
|
|
|
def need_pkt_has_multi_cof(tag):
|
2023-03-20 12:25:33 +03:00
|
|
|
return "A_COF" in attribdict[tag]
|
|
|
|
|
2022-11-08 19:28:59 +03:00
|
|
|
|
Hexagon (target/hexagon) Short-circuit packet register writes
In certain cases, we can avoid the overhead of writing to hex_new_value
and write directly to hex_gpr. We add need_commit field to DisasContext
indicating if the end-of-packet commit is needed. If it is not needed,
get_result_gpr() and get_result_gpr_pair() can return hex_gpr.
We pass the ctx->need_commit to helpers when needed.
Finally, we can early-exit from gen_reg_writes during packet commit.
There are a few instructions whose semantics write to the result before
reading all the inputs. Therefore, the idef-parser generated code is
incompatible with short-circuit. We tell idef-parser to skip them.
For debugging purposes, we add a cpu property to turn off short-circuit.
When the short-circuit property is false, we skip the analysis and force
the end-of-packet commit.
Here's a simple example of the TCG generated for
0x004000b4: 0x7800c020 { R0 = #0x1 }
BEFORE:
---- 004000b4
movi_i32 new_r0,$0x1
mov_i32 r0,new_r0
AFTER:
---- 004000b4
movi_i32 r0,$0x1
This patch reintroduces a use of check_for_attrib, so we remove the
G_GNUC_UNUSED added earlier in this series.
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Brian Cain <bcain@quicinc.com>
Message-Id: <20230427230012.3800327-12-tsimpson@quicinc.com>
2023-04-28 02:00:02 +03:00
|
|
|
def need_pkt_need_commit(tag):
|
|
|
|
return 'A_IMPLICIT_WRITES_USR' in attribdict[tag]
|
|
|
|
|
Hexagon (target/hexagon) Remove gen_log_predicated_reg_write[_pair]
We assign the instruction destination register to hex_new_value[num]
instead of a TCG temp that gets copied back to hex_new_value[num].
We introduce new functions get_result_gpr[_pair] to facilitate getting
the proper destination register.
Since we preload hex_new_value for predicated instructions, we don't
need the check for slot_cancelled. So, we call gen_log_reg_write instead.
We update the helper function generation and gen_tcg.h to maintain the
disable-hexagon-idef-parser configuration.
Here is a simple example of the differences in the TCG code generated:
IN:
0x00400094: 0xf900c102 { if (P0) R2 = and(R0,R1) }
BEFORE
---- 00400094
mov_i32 slot_cancelled,$0x0
mov_i32 new_r2,r2
mov_i32 loc2,$0x0
and_i32 tmp0,p0,$0x1
brcond_i32 tmp0,$0x0,eq,$L1
and_i32 tmp0,r0,r1
mov_i32 loc2,tmp0
br $L2
set_label $L1
or_i32 slot_cancelled,slot_cancelled,$0x8
set_label $L2
and_i32 tmp0,slot_cancelled,$0x8
movcond_i32 new_r2,tmp0,$0x0,loc2,new_r2,eq
mov_i32 r2,new_r2
AFTER
---- 00400094
mov_i32 slot_cancelled,$0x0
mov_i32 new_r2,r2
and_i32 tmp0,p0,$0x1
brcond_i32 tmp0,$0x0,eq,$L1
and_i32 tmp0,r0,r1
mov_i32 new_r2,tmp0
br $L2
set_label $L1
or_i32 slot_cancelled,slot_cancelled,$0x8
set_label $L2
mov_i32 r2,new_r2
We'll remove the unnecessary manipulation of slot_cancelled in a
subsequent patch.
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Message-Id: <20230307025828.1612809-13-tsimpson@quicinc.com>
2023-03-07 05:58:26 +03:00
|
|
|
def need_condexec_reg(tag, regs):
|
2023-03-20 12:25:33 +03:00
|
|
|
if "A_CONDEXEC" in attribdict[tag]:
|
2023-05-24 17:41:47 +03:00
|
|
|
for regtype, regid in regs:
|
Hexagon (target/hexagon) Remove gen_log_predicated_reg_write[_pair]
We assign the instruction destination register to hex_new_value[num]
instead of a TCG temp that gets copied back to hex_new_value[num].
We introduce new functions get_result_gpr[_pair] to facilitate getting
the proper destination register.
Since we preload hex_new_value for predicated instructions, we don't
need the check for slot_cancelled. So, we call gen_log_reg_write instead.
We update the helper function generation and gen_tcg.h to maintain the
disable-hexagon-idef-parser configuration.
Here is a simple example of the differences in the TCG code generated:
IN:
0x00400094: 0xf900c102 { if (P0) R2 = and(R0,R1) }
BEFORE
---- 00400094
mov_i32 slot_cancelled,$0x0
mov_i32 new_r2,r2
mov_i32 loc2,$0x0
and_i32 tmp0,p0,$0x1
brcond_i32 tmp0,$0x0,eq,$L1
and_i32 tmp0,r0,r1
mov_i32 loc2,tmp0
br $L2
set_label $L1
or_i32 slot_cancelled,slot_cancelled,$0x8
set_label $L2
and_i32 tmp0,slot_cancelled,$0x8
movcond_i32 new_r2,tmp0,$0x0,loc2,new_r2,eq
mov_i32 r2,new_r2
AFTER
---- 00400094
mov_i32 slot_cancelled,$0x0
mov_i32 new_r2,r2
and_i32 tmp0,p0,$0x1
brcond_i32 tmp0,$0x0,eq,$L1
and_i32 tmp0,r0,r1
mov_i32 new_r2,tmp0
br $L2
set_label $L1
or_i32 slot_cancelled,slot_cancelled,$0x8
set_label $L2
mov_i32 r2,new_r2
We'll remove the unnecessary manipulation of slot_cancelled in a
subsequent patch.
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Message-Id: <20230307025828.1612809-13-tsimpson@quicinc.com>
2023-03-07 05:58:26 +03:00
|
|
|
if is_writeonly(regid) and not is_hvx_reg(regtype):
|
|
|
|
return True
|
|
|
|
return False
|
|
|
|
|
2023-03-20 12:25:33 +03:00
|
|
|
|
2021-02-08 08:46:10 +03:00
|
|
|
def skip_qemu_helper(tag):
|
|
|
|
return tag in overrides.keys()
|
|
|
|
|
2023-03-20 12:25:33 +03:00
|
|
|
|
2021-05-19 00:45:18 +03:00
|
|
|
def is_tmp_result(tag):
|
2023-03-20 12:25:33 +03:00
|
|
|
return "A_CVI_TMP" in attribdict[tag] or "A_CVI_TMP_DST" in attribdict[tag]
|
|
|
|
|
2021-05-19 00:45:18 +03:00
|
|
|
|
|
|
|
def is_new_result(tag):
|
2023-03-20 12:25:33 +03:00
|
|
|
return "A_CVI_NEW" in attribdict[tag]
|
|
|
|
|
2021-05-19 00:45:18 +03:00
|
|
|
|
2022-09-23 20:38:30 +03:00
|
|
|
def is_idef_parser_enabled(tag):
|
|
|
|
return tag in idef_parser_enabled
|
|
|
|
|
2023-03-20 12:25:33 +03:00
|
|
|
|
2021-02-08 08:46:10 +03:00
|
|
|
def imm_name(immlett):
|
2023-03-20 12:25:32 +03:00
|
|
|
return f"{immlett}iV"
|
2021-02-08 08:46:10 +03:00
|
|
|
|
2023-03-20 12:25:33 +03:00
|
|
|
|
2021-02-08 08:46:10 +03:00
|
|
|
def read_semantics_file(name):
|
|
|
|
eval_line = ""
|
2023-03-20 12:25:33 +03:00
|
|
|
for line in open(name, "rt").readlines():
|
2021-02-08 08:46:10 +03:00
|
|
|
if not line.startswith("#"):
|
|
|
|
eval_line += line
|
|
|
|
if line.endswith("\\\n"):
|
|
|
|
eval_line.rstrip("\\\n")
|
|
|
|
else:
|
|
|
|
eval(eval_line.strip())
|
|
|
|
eval_line = ""
|
|
|
|
|
2023-03-20 12:25:33 +03:00
|
|
|
|
2021-02-08 08:46:10 +03:00
|
|
|
def read_attribs_file(name):
|
2023-03-20 12:25:33 +03:00
|
|
|
attribre = re.compile(
|
|
|
|
r"DEF_ATTRIB\(([A-Za-z0-9_]+), ([^,]*), "
|
|
|
|
+ r'"([A-Za-z0-9_\.]*)", "([A-Za-z0-9_\.]*)"\)'
|
|
|
|
)
|
|
|
|
for line in open(name, "rt").readlines():
|
2021-02-08 08:46:10 +03:00
|
|
|
if not attribre.match(line):
|
|
|
|
continue
|
2023-03-20 12:25:33 +03:00
|
|
|
(attrib_base, descr, rreg, wreg) = attribre.findall(line)[0]
|
|
|
|
attrib_base = "A_" + attrib_base
|
|
|
|
attribinfo[attrib_base] = {"rreg": rreg, "wreg": wreg, "descr": descr}
|
|
|
|
|
2021-02-08 08:46:10 +03:00
|
|
|
|
|
|
|
def read_overrides_file(name):
|
|
|
|
overridere = re.compile("#define fGEN_TCG_([A-Za-z0-9_]+)\(.*")
|
2023-03-20 12:25:33 +03:00
|
|
|
for line in open(name, "rt").readlines():
|
2021-02-08 08:46:10 +03:00
|
|
|
if not overridere.match(line):
|
|
|
|
continue
|
|
|
|
tag = overridere.findall(line)[0]
|
|
|
|
overrides[tag] = True
|
2022-09-23 20:38:30 +03:00
|
|
|
|
2023-03-20 12:25:33 +03:00
|
|
|
|
2022-09-23 20:38:30 +03:00
|
|
|
def read_idef_parser_enabled_file(name):
|
|
|
|
global idef_parser_enabled
|
|
|
|
with open(name, "r") as idef_parser_enabled_file:
|
|
|
|
lines = idef_parser_enabled_file.read().strip().split("\n")
|
|
|
|
idef_parser_enabled = set(lines)
|