2020-10-23 18:07:31 +03:00
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/*
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* Generic Virtual-Device Fuzzing Target
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*
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* Copyright Red Hat Inc., 2020
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*
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* Authors:
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* Alexander Bulekov <alxndr@bu.edu>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*/
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#include "qemu/osdep.h"
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#include <wordexp.h>
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#include "hw/core/cpu.h"
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2022-03-30 12:39:05 +03:00
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#include "tests/qtest/libqtest.h"
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2020-12-21 21:12:03 +03:00
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#include "tests/qtest/libqos/pci-pc.h"
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2020-10-23 18:07:31 +03:00
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#include "fuzz.h"
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#include "string.h"
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#include "exec/memory.h"
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#include "exec/ramblock.h"
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#include "hw/qdev-core.h"
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2020-10-23 18:07:32 +03:00
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#include "hw/pci/pci.h"
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2022-12-22 13:03:28 +03:00
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#include "hw/pci/pci_device.h"
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2020-10-23 18:07:33 +03:00
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#include "hw/boards.h"
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2020-10-23 18:07:44 +03:00
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#include "generic_fuzz_configs.h"
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2021-03-15 17:05:11 +03:00
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#include "hw/mem/sparse-mem.h"
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2020-10-23 18:07:31 +03:00
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2023-02-05 07:29:44 +03:00
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static void pci_enum(gpointer pcidev, gpointer bus);
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2020-10-23 18:07:31 +03:00
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/*
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* SEPARATOR is used to separate "operations" in the fuzz input
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*/
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#define SEPARATOR "FUZZ"
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enum cmds {
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OP_IN,
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OP_OUT,
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OP_READ,
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OP_WRITE,
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2020-10-23 18:07:32 +03:00
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OP_PCI_READ,
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OP_PCI_WRITE,
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2020-10-23 18:07:37 +03:00
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OP_DISABLE_PCI,
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2020-10-23 18:07:33 +03:00
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OP_ADD_DMA_PATTERN,
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OP_CLEAR_DMA_PATTERNS,
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2020-10-23 18:07:31 +03:00
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OP_CLOCK_STEP,
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};
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#define USEC_IN_SEC 1000000000
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2020-10-23 18:07:33 +03:00
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#define MAX_DMA_FILL_SIZE 0x10000
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2020-10-23 18:07:32 +03:00
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#define PCI_HOST_BRIDGE_CFG 0xcf8
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#define PCI_HOST_BRIDGE_DATA 0xcfc
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2020-10-23 18:07:31 +03:00
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typedef struct {
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ram_addr_t addr;
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ram_addr_t size; /* The number of bytes until the end of the I/O region */
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} address_range;
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static bool qtest_log_enabled;
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2021-03-15 17:05:11 +03:00
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MemoryRegion *sparse_mem_mr;
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2020-10-23 18:07:33 +03:00
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/*
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* A pattern used to populate a DMA region or perform a memwrite. This is
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* useful for e.g. populating tables of unique addresses.
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* Example {.index = 1; .stride = 2; .len = 3; .data = "\x00\x01\x02"}
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* Renders as: 00 01 02 00 03 02 00 05 02 00 07 02 ...
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*/
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typedef struct {
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uint8_t index; /* Index of a byte to increment by stride */
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uint8_t stride; /* Increment each index'th byte by this amount */
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size_t len;
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const uint8_t *data;
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} pattern;
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/* Avoid filling the same DMA region between MMIO/PIO commands ? */
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static bool avoid_double_fetches;
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static QTestState *qts_global; /* Need a global for the DMA callback */
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2020-10-23 18:07:31 +03:00
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/*
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* List of memory regions that are children of QOM objects specified by the
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* user for fuzzing.
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*/
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static GHashTable *fuzzable_memoryregions;
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2020-10-23 18:07:32 +03:00
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static GPtrArray *fuzzable_pci_devices;
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2020-10-23 18:07:31 +03:00
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struct get_io_cb_info {
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int index;
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int found;
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address_range result;
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};
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2021-03-18 20:48:19 +03:00
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static bool get_io_address_cb(Int128 start, Int128 size,
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2021-03-18 20:48:21 +03:00
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const MemoryRegion *mr,
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hwaddr offset_in_region,
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void *opaque)
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{
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2020-10-23 18:07:31 +03:00
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struct get_io_cb_info *info = opaque;
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if (g_hash_table_lookup(fuzzable_memoryregions, mr)) {
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if (info->index == 0) {
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info->result.addr = (ram_addr_t)start;
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info->result.size = (ram_addr_t)size;
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info->found = 1;
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2021-03-18 20:48:19 +03:00
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return true;
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2020-10-23 18:07:31 +03:00
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}
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info->index--;
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}
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2021-03-18 20:48:19 +03:00
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return false;
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2020-10-23 18:07:31 +03:00
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}
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2020-10-23 18:07:33 +03:00
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/*
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* List of dma regions populated since the last fuzzing command. Used to ensure
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* that we only write to each DMA address once, to avoid race conditions when
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* building reproducers.
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*/
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static GArray *dma_regions;
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static GArray *dma_patterns;
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static int dma_pattern_index;
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2020-10-23 18:07:37 +03:00
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static bool pci_disabled;
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2020-10-23 18:07:33 +03:00
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/*
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* Allocate a block of memory and populate it with a pattern.
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*/
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static void *pattern_alloc(pattern p, size_t len)
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{
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int i;
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uint8_t *buf = g_malloc(len);
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uint8_t sum = 0;
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for (i = 0; i < len; ++i) {
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buf[i] = p.data[i % p.len];
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if ((i % p.len) == p.index) {
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buf[i] += sum;
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sum += p.stride;
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}
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}
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return buf;
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}
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2022-06-13 23:26:32 +03:00
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static int fuzz_memory_access_size(MemoryRegion *mr, unsigned l, hwaddr addr)
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2020-10-23 18:07:33 +03:00
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{
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unsigned access_size_max = mr->ops->valid.max_access_size;
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/*
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* Regions are assumed to support 1-4 byte accesses unless
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* otherwise specified.
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*/
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if (access_size_max == 0) {
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access_size_max = 4;
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}
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/* Bound the maximum access by the alignment of the address. */
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if (!mr->ops->impl.unaligned) {
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unsigned align_size_max = addr & -addr;
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if (align_size_max != 0 && align_size_max < access_size_max) {
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access_size_max = align_size_max;
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}
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}
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/* Don't attempt accesses larger than the maximum. */
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if (l > access_size_max) {
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l = access_size_max;
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}
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l = pow2floor(l);
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return l;
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}
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/*
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* Call-back for functions that perform DMA reads from guest memory. Confirm
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* that the region has not already been populated since the last loop in
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* generic_fuzz(), avoiding potential race-conditions, which we don't have
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* a good way for reproducing right now.
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*/
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2021-01-20 09:02:55 +03:00
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void fuzz_dma_read_cb(size_t addr, size_t len, MemoryRegion *mr)
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2020-10-23 18:07:33 +03:00
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{
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/* Are we in the generic-fuzzer or are we using another fuzz-target? */
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if (!qts_global) {
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return;
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}
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/*
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* Return immediately if:
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* - We have no DMA patterns defined
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* - The length of the DMA read request is zero
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* - The DMA read is hitting an MR other than the machine's main RAM
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* - The DMA request hits past the bounds of our RAM
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*/
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if (dma_patterns->len == 0
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|| len == 0
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2021-03-15 17:05:11 +03:00
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|| (mr != current_machine->ram && mr != sparse_mem_mr)) {
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2020-10-23 18:07:33 +03:00
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return;
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}
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/*
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* If we overlap with any existing dma_regions, split the range and only
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* populate the non-overlapping parts.
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*/
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address_range region;
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bool double_fetch = false;
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for (int i = 0;
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i < dma_regions->len && (avoid_double_fetches || qtest_log_enabled);
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++i) {
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region = g_array_index(dma_regions, address_range, i);
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if (addr < region.addr + region.size && addr + len > region.addr) {
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double_fetch = true;
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if (addr < region.addr
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&& avoid_double_fetches) {
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2021-01-20 09:02:55 +03:00
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fuzz_dma_read_cb(addr, region.addr - addr, mr);
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2020-10-23 18:07:33 +03:00
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}
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if (addr + len > region.addr + region.size
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&& avoid_double_fetches) {
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fuzz_dma_read_cb(region.addr + region.size,
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2021-01-20 09:02:55 +03:00
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addr + len - (region.addr + region.size), mr);
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2020-10-23 18:07:33 +03:00
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}
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return;
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}
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}
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/* Cap the length of the DMA access to something reasonable */
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len = MIN(len, MAX_DMA_FILL_SIZE);
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address_range ar = {addr, len};
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g_array_append_val(dma_regions, ar);
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pattern p = g_array_index(dma_patterns, pattern, dma_pattern_index);
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2020-10-29 20:28:58 +03:00
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void *buf_base = pattern_alloc(p, ar.size);
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void *buf = buf_base;
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2020-10-23 18:07:33 +03:00
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hwaddr l, addr1;
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MemoryRegion *mr1;
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while (len > 0) {
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l = len;
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mr1 = address_space_translate(first_cpu->as,
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addr, &addr1, &l, true,
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MEMTXATTRS_UNSPECIFIED);
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2021-07-13 18:00:34 +03:00
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/*
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* If mr1 isn't RAM, address_space_translate doesn't update l. Use
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2022-06-13 23:26:32 +03:00
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* fuzz_memory_access_size to identify the number of bytes that it
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* is safe to write without accidentally writing to another
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* MemoryRegion.
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2021-07-13 18:00:34 +03:00
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*/
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if (!memory_region_is_ram(mr1)) {
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2022-06-13 23:26:32 +03:00
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l = fuzz_memory_access_size(mr1, l, addr1);
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2021-07-13 18:00:34 +03:00
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}
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if (memory_region_is_ram(mr1) ||
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memory_region_is_romd(mr1) ||
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mr1 == sparse_mem_mr) {
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2020-10-23 18:07:33 +03:00
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/* ROM/RAM case */
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2020-10-29 20:28:58 +03:00
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if (qtest_log_enabled) {
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/*
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* With QTEST_LOG, use a normal, slow QTest memwrite. Prefix the log
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* that will be written by qtest.c with a DMA tag, so we can reorder
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* the resulting QTest trace so the DMA fills precede the last PIO/MMIO
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* command.
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*/
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fprintf(stderr, "[DMA] ");
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if (double_fetch) {
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fprintf(stderr, "[DOUBLE-FETCH] ");
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}
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fflush(stderr);
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}
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qtest_memwrite(qts_global, addr, buf, l);
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2020-10-23 18:07:33 +03:00
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}
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len -= l;
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buf += l;
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addr += l;
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}
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2020-10-29 20:28:58 +03:00
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g_free(buf_base);
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2020-10-23 18:07:33 +03:00
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/* Increment the index of the pattern for the next DMA access */
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dma_pattern_index = (dma_pattern_index + 1) % dma_patterns->len;
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}
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2020-10-23 18:07:31 +03:00
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/*
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* Here we want to convert a fuzzer-provided [io-region-index, offset] to
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* a physical address. To do this, we iterate over all of the matched
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* MemoryRegions. Check whether each region exists within the particular io
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* space. Return the absolute address of the offset within the index'th region
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* that is a subregion of the io_space and the distance until the end of the
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* memory region.
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*/
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static bool get_io_address(address_range *result, AddressSpace *as,
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uint8_t index,
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uint32_t offset) {
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FlatView *view;
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view = as->current_map;
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g_assert(view);
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struct get_io_cb_info cb_info = {};
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cb_info.index = index;
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/*
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* Loop around the FlatView until we match "index" number of
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* fuzzable_memoryregions, or until we know that there are no matching
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* memory_regions.
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*/
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do {
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flatview_for_each_range(view, get_io_address_cb , &cb_info);
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} while (cb_info.index != index && !cb_info.found);
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*result = cb_info.result;
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2020-10-29 20:29:00 +03:00
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if (result->size) {
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offset = offset % result->size;
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result->addr += offset;
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result->size -= offset;
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}
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2020-10-23 18:07:31 +03:00
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return cb_info.found;
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}
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static bool get_pio_address(address_range *result,
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uint8_t index, uint16_t offset)
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{
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/*
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* PIO BARs can be set past the maximum port address (0xFFFF). Thus, result
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* can contain an addr that extends past the PIO space. When we pass this
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* address to qtest_in/qtest_out, it is cast to a uint16_t, so we might end
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* up fuzzing a completely different MemoryRegion/Device. Therefore, check
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* that the address here is within the PIO space limits.
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*/
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bool found = get_io_address(result, &address_space_io, index, offset);
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return result->addr <= 0xFFFF ? found : false;
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}
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static bool get_mmio_address(address_range *result,
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uint8_t index, uint32_t offset)
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{
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|
|
return get_io_address(result, &address_space_memory, index, offset);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void op_in(QTestState *s, const unsigned char * data, size_t len)
|
|
|
|
{
|
|
|
|
enum Sizes {Byte, Word, Long, end_sizes};
|
|
|
|
struct {
|
|
|
|
uint8_t size;
|
|
|
|
uint8_t base;
|
|
|
|
uint16_t offset;
|
|
|
|
} a;
|
|
|
|
address_range abs;
|
|
|
|
|
|
|
|
if (len < sizeof(a)) {
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
memcpy(&a, data, sizeof(a));
|
|
|
|
if (get_pio_address(&abs, a.base, a.offset) == 0) {
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
switch (a.size %= end_sizes) {
|
|
|
|
case Byte:
|
|
|
|
qtest_inb(s, abs.addr);
|
|
|
|
break;
|
|
|
|
case Word:
|
|
|
|
if (abs.size >= 2) {
|
|
|
|
qtest_inw(s, abs.addr);
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case Long:
|
|
|
|
if (abs.size >= 4) {
|
|
|
|
qtest_inl(s, abs.addr);
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void op_out(QTestState *s, const unsigned char * data, size_t len)
|
|
|
|
{
|
|
|
|
enum Sizes {Byte, Word, Long, end_sizes};
|
|
|
|
struct {
|
|
|
|
uint8_t size;
|
|
|
|
uint8_t base;
|
|
|
|
uint16_t offset;
|
|
|
|
uint32_t value;
|
|
|
|
} a;
|
|
|
|
address_range abs;
|
|
|
|
|
|
|
|
if (len < sizeof(a)) {
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
memcpy(&a, data, sizeof(a));
|
|
|
|
|
|
|
|
if (get_pio_address(&abs, a.base, a.offset) == 0) {
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
switch (a.size %= end_sizes) {
|
|
|
|
case Byte:
|
|
|
|
qtest_outb(s, abs.addr, a.value & 0xFF);
|
|
|
|
break;
|
|
|
|
case Word:
|
|
|
|
if (abs.size >= 2) {
|
|
|
|
qtest_outw(s, abs.addr, a.value & 0xFFFF);
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case Long:
|
|
|
|
if (abs.size >= 4) {
|
|
|
|
qtest_outl(s, abs.addr, a.value);
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void op_read(QTestState *s, const unsigned char * data, size_t len)
|
|
|
|
{
|
|
|
|
enum Sizes {Byte, Word, Long, Quad, end_sizes};
|
|
|
|
struct {
|
|
|
|
uint8_t size;
|
|
|
|
uint8_t base;
|
|
|
|
uint32_t offset;
|
|
|
|
} a;
|
|
|
|
address_range abs;
|
|
|
|
|
|
|
|
if (len < sizeof(a)) {
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
memcpy(&a, data, sizeof(a));
|
|
|
|
|
|
|
|
if (get_mmio_address(&abs, a.base, a.offset) == 0) {
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
switch (a.size %= end_sizes) {
|
|
|
|
case Byte:
|
|
|
|
qtest_readb(s, abs.addr);
|
|
|
|
break;
|
|
|
|
case Word:
|
|
|
|
if (abs.size >= 2) {
|
|
|
|
qtest_readw(s, abs.addr);
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case Long:
|
|
|
|
if (abs.size >= 4) {
|
|
|
|
qtest_readl(s, abs.addr);
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case Quad:
|
|
|
|
if (abs.size >= 8) {
|
|
|
|
qtest_readq(s, abs.addr);
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void op_write(QTestState *s, const unsigned char * data, size_t len)
|
|
|
|
{
|
|
|
|
enum Sizes {Byte, Word, Long, Quad, end_sizes};
|
|
|
|
struct {
|
|
|
|
uint8_t size;
|
|
|
|
uint8_t base;
|
|
|
|
uint32_t offset;
|
|
|
|
uint64_t value;
|
|
|
|
} a;
|
|
|
|
address_range abs;
|
|
|
|
|
|
|
|
if (len < sizeof(a)) {
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
memcpy(&a, data, sizeof(a));
|
|
|
|
|
|
|
|
if (get_mmio_address(&abs, a.base, a.offset) == 0) {
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
switch (a.size %= end_sizes) {
|
|
|
|
case Byte:
|
|
|
|
qtest_writeb(s, abs.addr, a.value & 0xFF);
|
|
|
|
break;
|
|
|
|
case Word:
|
|
|
|
if (abs.size >= 2) {
|
|
|
|
qtest_writew(s, abs.addr, a.value & 0xFFFF);
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case Long:
|
|
|
|
if (abs.size >= 4) {
|
|
|
|
qtest_writel(s, abs.addr, a.value & 0xFFFFFFFF);
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case Quad:
|
|
|
|
if (abs.size >= 8) {
|
|
|
|
qtest_writeq(s, abs.addr, a.value);
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2020-10-23 18:07:32 +03:00
|
|
|
static void op_pci_read(QTestState *s, const unsigned char * data, size_t len)
|
|
|
|
{
|
|
|
|
enum Sizes {Byte, Word, Long, end_sizes};
|
|
|
|
struct {
|
|
|
|
uint8_t size;
|
|
|
|
uint8_t base;
|
|
|
|
uint8_t offset;
|
|
|
|
} a;
|
2020-10-23 18:07:37 +03:00
|
|
|
if (len < sizeof(a) || fuzzable_pci_devices->len == 0 || pci_disabled) {
|
2020-10-23 18:07:32 +03:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
memcpy(&a, data, sizeof(a));
|
|
|
|
PCIDevice *dev = g_ptr_array_index(fuzzable_pci_devices,
|
|
|
|
a.base % fuzzable_pci_devices->len);
|
|
|
|
int devfn = dev->devfn;
|
|
|
|
qtest_outl(s, PCI_HOST_BRIDGE_CFG, (1U << 31) | (devfn << 8) | a.offset);
|
|
|
|
switch (a.size %= end_sizes) {
|
|
|
|
case Byte:
|
|
|
|
qtest_inb(s, PCI_HOST_BRIDGE_DATA);
|
|
|
|
break;
|
|
|
|
case Word:
|
|
|
|
qtest_inw(s, PCI_HOST_BRIDGE_DATA);
|
|
|
|
break;
|
|
|
|
case Long:
|
|
|
|
qtest_inl(s, PCI_HOST_BRIDGE_DATA);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void op_pci_write(QTestState *s, const unsigned char * data, size_t len)
|
|
|
|
{
|
|
|
|
enum Sizes {Byte, Word, Long, end_sizes};
|
|
|
|
struct {
|
|
|
|
uint8_t size;
|
|
|
|
uint8_t base;
|
|
|
|
uint8_t offset;
|
|
|
|
uint32_t value;
|
|
|
|
} a;
|
2020-10-23 18:07:37 +03:00
|
|
|
if (len < sizeof(a) || fuzzable_pci_devices->len == 0 || pci_disabled) {
|
2020-10-23 18:07:32 +03:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
memcpy(&a, data, sizeof(a));
|
|
|
|
PCIDevice *dev = g_ptr_array_index(fuzzable_pci_devices,
|
|
|
|
a.base % fuzzable_pci_devices->len);
|
|
|
|
int devfn = dev->devfn;
|
|
|
|
qtest_outl(s, PCI_HOST_BRIDGE_CFG, (1U << 31) | (devfn << 8) | a.offset);
|
|
|
|
switch (a.size %= end_sizes) {
|
|
|
|
case Byte:
|
|
|
|
qtest_outb(s, PCI_HOST_BRIDGE_DATA, a.value & 0xFF);
|
|
|
|
break;
|
|
|
|
case Word:
|
|
|
|
qtest_outw(s, PCI_HOST_BRIDGE_DATA, a.value & 0xFFFF);
|
|
|
|
break;
|
|
|
|
case Long:
|
|
|
|
qtest_outl(s, PCI_HOST_BRIDGE_DATA, a.value & 0xFFFFFFFF);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2020-10-23 18:07:33 +03:00
|
|
|
static void op_add_dma_pattern(QTestState *s,
|
|
|
|
const unsigned char *data, size_t len)
|
|
|
|
{
|
|
|
|
struct {
|
|
|
|
/*
|
|
|
|
* index and stride can be used to increment the index-th byte of the
|
|
|
|
* pattern by the value stride, for each loop of the pattern.
|
|
|
|
*/
|
|
|
|
uint8_t index;
|
|
|
|
uint8_t stride;
|
|
|
|
} a;
|
|
|
|
|
|
|
|
if (len < sizeof(a) + 1) {
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
memcpy(&a, data, sizeof(a));
|
|
|
|
pattern p = {a.index, a.stride, len - sizeof(a), data + sizeof(a)};
|
|
|
|
p.index = a.index % p.len;
|
|
|
|
g_array_append_val(dma_patterns, p);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void op_clear_dma_patterns(QTestState *s,
|
|
|
|
const unsigned char *data, size_t len)
|
|
|
|
{
|
|
|
|
g_array_set_size(dma_patterns, 0);
|
|
|
|
dma_pattern_index = 0;
|
|
|
|
}
|
|
|
|
|
2020-10-23 18:07:31 +03:00
|
|
|
static void op_clock_step(QTestState *s, const unsigned char *data, size_t len)
|
|
|
|
{
|
|
|
|
qtest_clock_step_next(s);
|
|
|
|
}
|
|
|
|
|
2020-10-23 18:07:37 +03:00
|
|
|
static void op_disable_pci(QTestState *s, const unsigned char *data, size_t len)
|
|
|
|
{
|
|
|
|
pci_disabled = true;
|
|
|
|
}
|
|
|
|
|
2020-10-23 18:07:31 +03:00
|
|
|
/*
|
|
|
|
* Here, we interpret random bytes from the fuzzer, as a sequence of commands.
|
|
|
|
* Some commands can be variable-width, so we use a separator, SEPARATOR, to
|
|
|
|
* specify the boundaries between commands. SEPARATOR is used to separate
|
|
|
|
* "operations" in the fuzz input. Why use a separator, instead of just using
|
|
|
|
* the operations' length to identify operation boundaries?
|
|
|
|
* 1. This is a simple way to support variable-length operations
|
|
|
|
* 2. This adds "stability" to the input.
|
|
|
|
* For example take the input "AbBcgDefg", where there is no separator and
|
|
|
|
* Opcodes are capitalized.
|
|
|
|
* Simply, by removing the first byte, we end up with a very different
|
|
|
|
* sequence:
|
|
|
|
* BbcGdefg...
|
|
|
|
* By adding a separator, we avoid this problem:
|
|
|
|
* Ab SEP Bcg SEP Defg -> B SEP Bcg SEP Defg
|
|
|
|
* Since B uses two additional bytes as operands, the first "B" will be
|
|
|
|
* ignored. The fuzzer actively tries to reduce inputs, so such unused
|
|
|
|
* bytes are likely to be pruned, eventually.
|
|
|
|
*
|
|
|
|
* SEPARATOR is trivial for the fuzzer to discover when using ASan. Optionally,
|
|
|
|
* SEPARATOR can be manually specified as a dictionary value (see libfuzzer's
|
|
|
|
* -dict), though this should not be necessary.
|
|
|
|
*
|
|
|
|
* As a result, the stream of bytes is converted into a sequence of commands.
|
|
|
|
* In a simplified example where SEPARATOR is 0xFF:
|
|
|
|
* 00 01 02 FF 03 04 05 06 FF 01 FF ...
|
|
|
|
* becomes this sequence of commands:
|
|
|
|
* 00 01 02 -> op00 (0102) -> in (0102, 2)
|
|
|
|
* 03 04 05 06 -> op03 (040506) -> write (040506, 3)
|
|
|
|
* 01 -> op01 (-,0) -> out (-,0)
|
|
|
|
* ...
|
|
|
|
*
|
|
|
|
* Note here that it is the job of the individual opcode functions to check
|
|
|
|
* that enough data was provided. I.e. in the last command out (,0), out needs
|
|
|
|
* to check that there is not enough data provided to select an address/value
|
|
|
|
* for the operation.
|
|
|
|
*/
|
|
|
|
static void generic_fuzz(QTestState *s, const unsigned char *Data, size_t Size)
|
|
|
|
{
|
|
|
|
void (*ops[]) (QTestState *s, const unsigned char* , size_t) = {
|
|
|
|
[OP_IN] = op_in,
|
|
|
|
[OP_OUT] = op_out,
|
|
|
|
[OP_READ] = op_read,
|
|
|
|
[OP_WRITE] = op_write,
|
2020-10-23 18:07:32 +03:00
|
|
|
[OP_PCI_READ] = op_pci_read,
|
|
|
|
[OP_PCI_WRITE] = op_pci_write,
|
2020-10-23 18:07:37 +03:00
|
|
|
[OP_DISABLE_PCI] = op_disable_pci,
|
2020-10-23 18:07:33 +03:00
|
|
|
[OP_ADD_DMA_PATTERN] = op_add_dma_pattern,
|
|
|
|
[OP_CLEAR_DMA_PATTERNS] = op_clear_dma_patterns,
|
2020-10-23 18:07:31 +03:00
|
|
|
[OP_CLOCK_STEP] = op_clock_step,
|
|
|
|
};
|
|
|
|
const unsigned char *cmd = Data;
|
|
|
|
const unsigned char *nextcmd;
|
|
|
|
size_t cmd_len;
|
|
|
|
uint8_t op;
|
|
|
|
|
2023-02-05 07:29:44 +03:00
|
|
|
op_clear_dma_patterns(s, NULL, 0);
|
|
|
|
pci_disabled = false;
|
2020-10-23 18:07:31 +03:00
|
|
|
|
2023-02-05 07:29:44 +03:00
|
|
|
QPCIBus *pcibus = qpci_new_pc(s, NULL);
|
|
|
|
g_ptr_array_foreach(fuzzable_pci_devices, pci_enum, pcibus);
|
|
|
|
qpci_free_pc(pcibus);
|
2021-07-13 18:00:35 +03:00
|
|
|
|
2023-02-05 07:29:44 +03:00
|
|
|
while (cmd && Size) {
|
|
|
|
/* Get the length until the next command or end of input */
|
|
|
|
nextcmd = memmem(cmd, Size, SEPARATOR, strlen(SEPARATOR));
|
|
|
|
cmd_len = nextcmd ? nextcmd - cmd : Size;
|
2020-10-23 18:07:31 +03:00
|
|
|
|
2023-02-05 07:29:44 +03:00
|
|
|
if (cmd_len > 0) {
|
|
|
|
/* Interpret the first byte of the command as an opcode */
|
|
|
|
op = *cmd % (sizeof(ops) / sizeof((ops)[0]));
|
|
|
|
ops[op](s, cmd + 1, cmd_len - 1);
|
2020-10-23 18:07:31 +03:00
|
|
|
|
2023-02-05 07:29:44 +03:00
|
|
|
/* Run the main loop */
|
|
|
|
flush_events(s);
|
2020-10-23 18:07:31 +03:00
|
|
|
}
|
2023-02-05 07:29:44 +03:00
|
|
|
/* Advance to the next command */
|
|
|
|
cmd = nextcmd ? nextcmd + sizeof(SEPARATOR) - 1 : nextcmd;
|
|
|
|
Size = Size - (cmd_len + sizeof(SEPARATOR) - 1);
|
|
|
|
g_array_set_size(dma_regions, 0);
|
2020-10-23 18:07:31 +03:00
|
|
|
}
|
2023-02-05 07:29:44 +03:00
|
|
|
fuzz_reset(s);
|
2020-10-23 18:07:31 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
static void usage(void)
|
|
|
|
{
|
|
|
|
printf("Please specify the following environment variables:\n");
|
|
|
|
printf("QEMU_FUZZ_ARGS= the command line arguments passed to qemu\n");
|
|
|
|
printf("QEMU_FUZZ_OBJECTS= "
|
|
|
|
"a space separated list of QOM type names for objects to fuzz\n");
|
2020-10-23 18:07:33 +03:00
|
|
|
printf("Optionally: QEMU_AVOID_DOUBLE_FETCH= "
|
|
|
|
"Try to avoid racy DMA double fetch bugs? %d by default\n",
|
|
|
|
avoid_double_fetches);
|
2020-10-23 18:07:31 +03:00
|
|
|
exit(0);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int locate_fuzz_memory_regions(Object *child, void *opaque)
|
|
|
|
{
|
|
|
|
MemoryRegion *mr;
|
|
|
|
if (object_dynamic_cast(child, TYPE_MEMORY_REGION)) {
|
|
|
|
mr = MEMORY_REGION(child);
|
|
|
|
if ((memory_region_is_ram(mr) ||
|
|
|
|
memory_region_is_ram_device(mr) ||
|
|
|
|
memory_region_is_rom(mr)) == false) {
|
|
|
|
/*
|
|
|
|
* We don't want duplicate pointers to the same MemoryRegion, so
|
|
|
|
* try to remove copies of the pointer, before adding it.
|
|
|
|
*/
|
|
|
|
g_hash_table_insert(fuzzable_memoryregions, mr, (gpointer)true);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int locate_fuzz_objects(Object *child, void *opaque)
|
|
|
|
{
|
2021-07-13 18:00:36 +03:00
|
|
|
GString *type_name;
|
|
|
|
GString *path_name;
|
2020-10-23 18:07:31 +03:00
|
|
|
char *pattern = opaque;
|
2021-07-13 18:00:36 +03:00
|
|
|
|
|
|
|
type_name = g_string_new(object_get_typename(child));
|
|
|
|
g_string_ascii_down(type_name);
|
|
|
|
if (g_pattern_match_simple(pattern, type_name->str)) {
|
2020-10-23 18:07:31 +03:00
|
|
|
/* Find and save ptrs to any child MemoryRegions */
|
|
|
|
object_child_foreach_recursive(child, locate_fuzz_memory_regions, NULL);
|
|
|
|
|
2020-10-23 18:07:32 +03:00
|
|
|
/*
|
|
|
|
* We matched an object. If its a PCI device, store a pointer to it so
|
|
|
|
* we can map BARs and fuzz its config space.
|
|
|
|
*/
|
|
|
|
if (object_dynamic_cast(OBJECT(child), TYPE_PCI_DEVICE)) {
|
|
|
|
/*
|
|
|
|
* Don't want duplicate pointers to the same PCIDevice, so remove
|
|
|
|
* copies of the pointer, before adding it.
|
|
|
|
*/
|
|
|
|
g_ptr_array_remove_fast(fuzzable_pci_devices, PCI_DEVICE(child));
|
|
|
|
g_ptr_array_add(fuzzable_pci_devices, PCI_DEVICE(child));
|
|
|
|
}
|
2020-10-23 18:07:31 +03:00
|
|
|
} else if (object_dynamic_cast(OBJECT(child), TYPE_MEMORY_REGION)) {
|
2021-07-13 18:00:36 +03:00
|
|
|
path_name = g_string_new(object_get_canonical_path_component(child));
|
|
|
|
g_string_ascii_down(path_name);
|
|
|
|
if (g_pattern_match_simple(pattern, path_name->str)) {
|
2020-10-23 18:07:31 +03:00
|
|
|
MemoryRegion *mr;
|
|
|
|
mr = MEMORY_REGION(child);
|
|
|
|
if ((memory_region_is_ram(mr) ||
|
|
|
|
memory_region_is_ram_device(mr) ||
|
|
|
|
memory_region_is_rom(mr)) == false) {
|
|
|
|
g_hash_table_insert(fuzzable_memoryregions, mr, (gpointer)true);
|
|
|
|
}
|
|
|
|
}
|
2021-07-13 18:00:36 +03:00
|
|
|
g_string_free(path_name, true);
|
2020-10-23 18:07:31 +03:00
|
|
|
}
|
2021-07-13 18:00:36 +03:00
|
|
|
g_string_free(type_name, true);
|
2020-10-23 18:07:31 +03:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2020-12-21 21:12:03 +03:00
|
|
|
|
|
|
|
static void pci_enum(gpointer pcidev, gpointer bus)
|
|
|
|
{
|
|
|
|
PCIDevice *dev = pcidev;
|
|
|
|
QPCIDevice *qdev;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
qdev = qpci_device_find(bus, dev->devfn);
|
|
|
|
g_assert(qdev != NULL);
|
|
|
|
for (i = 0; i < 6; i++) {
|
|
|
|
if (dev->io_regions[i].size) {
|
|
|
|
qpci_iomap(qdev, i, NULL);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
qpci_device_enable(qdev);
|
|
|
|
g_free(qdev);
|
|
|
|
}
|
|
|
|
|
2020-10-23 18:07:31 +03:00
|
|
|
static void generic_pre_fuzz(QTestState *s)
|
|
|
|
{
|
|
|
|
GHashTableIter iter;
|
|
|
|
MemoryRegion *mr;
|
|
|
|
char **result;
|
2021-07-13 18:00:36 +03:00
|
|
|
GString *name_pattern;
|
2020-10-23 18:07:31 +03:00
|
|
|
|
|
|
|
if (!getenv("QEMU_FUZZ_OBJECTS")) {
|
|
|
|
usage();
|
|
|
|
}
|
|
|
|
if (getenv("QTEST_LOG")) {
|
|
|
|
qtest_log_enabled = 1;
|
|
|
|
}
|
2020-10-23 18:07:33 +03:00
|
|
|
if (getenv("QEMU_AVOID_DOUBLE_FETCH")) {
|
|
|
|
avoid_double_fetches = 1;
|
|
|
|
}
|
|
|
|
qts_global = s;
|
|
|
|
|
2021-03-15 17:05:11 +03:00
|
|
|
/*
|
|
|
|
* Create a special device that we can use to back DMA buffers at very
|
|
|
|
* high memory addresses
|
|
|
|
*/
|
|
|
|
sparse_mem_mr = sparse_mem_init(0, UINT64_MAX);
|
|
|
|
|
2020-10-23 18:07:33 +03:00
|
|
|
dma_regions = g_array_new(false, false, sizeof(address_range));
|
|
|
|
dma_patterns = g_array_new(false, false, sizeof(pattern));
|
2020-10-23 18:07:31 +03:00
|
|
|
|
|
|
|
fuzzable_memoryregions = g_hash_table_new(NULL, NULL);
|
2020-10-23 18:07:32 +03:00
|
|
|
fuzzable_pci_devices = g_ptr_array_new();
|
2020-10-23 18:07:31 +03:00
|
|
|
|
|
|
|
result = g_strsplit(getenv("QEMU_FUZZ_OBJECTS"), " ", -1);
|
|
|
|
for (int i = 0; result[i] != NULL; i++) {
|
2021-07-13 18:00:36 +03:00
|
|
|
name_pattern = g_string_new(result[i]);
|
|
|
|
/*
|
|
|
|
* Make the pattern lowercase. We do the same for all the MemoryRegion
|
|
|
|
* and Type names so the configs are case-insensitive.
|
|
|
|
*/
|
|
|
|
g_string_ascii_down(name_pattern);
|
2020-10-23 18:07:31 +03:00
|
|
|
printf("Matching objects by name %s\n", result[i]);
|
|
|
|
object_child_foreach_recursive(qdev_get_machine(),
|
|
|
|
locate_fuzz_objects,
|
2021-07-13 18:00:36 +03:00
|
|
|
name_pattern->str);
|
|
|
|
g_string_free(name_pattern, true);
|
2020-10-23 18:07:31 +03:00
|
|
|
}
|
|
|
|
g_strfreev(result);
|
|
|
|
printf("This process will try to fuzz the following MemoryRegions:\n");
|
|
|
|
|
|
|
|
g_hash_table_iter_init(&iter, fuzzable_memoryregions);
|
|
|
|
while (g_hash_table_iter_next(&iter, (gpointer)&mr, NULL)) {
|
2021-06-12 22:58:42 +03:00
|
|
|
printf(" * %s (size 0x%" PRIx64 ")\n",
|
2020-10-23 18:07:31 +03:00
|
|
|
object_get_canonical_path_component(&(mr->parent_obj)),
|
2021-06-12 22:58:42 +03:00
|
|
|
memory_region_size(mr));
|
2020-10-23 18:07:31 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
if (!g_hash_table_size(fuzzable_memoryregions)) {
|
|
|
|
printf("No fuzzable memory regions found...\n");
|
|
|
|
exit(1);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2020-10-23 18:07:38 +03:00
|
|
|
/*
|
|
|
|
* When libfuzzer gives us two inputs to combine, return a new input with the
|
|
|
|
* following structure:
|
|
|
|
*
|
|
|
|
* Input 1 (data1)
|
|
|
|
* SEPARATOR
|
|
|
|
* Clear out the DMA Patterns
|
|
|
|
* SEPARATOR
|
|
|
|
* Disable the pci_read/write instructions
|
|
|
|
* SEPARATOR
|
|
|
|
* Input 2 (data2)
|
|
|
|
*
|
|
|
|
* The idea is to collate the core behaviors of the two inputs.
|
|
|
|
* For example:
|
|
|
|
* Input 1: maps a device's BARs, sets up three DMA patterns, and triggers
|
|
|
|
* device functionality A
|
|
|
|
* Input 2: maps a device's BARs, sets up one DMA pattern, and triggers device
|
|
|
|
* functionality B
|
|
|
|
*
|
|
|
|
* This function attempts to produce an input that:
|
|
|
|
* Ouptut: maps a device's BARs, set up three DMA patterns, triggers
|
|
|
|
* functionality A device, replaces the DMA patterns with a single
|
|
|
|
* patten, and triggers device functionality B.
|
|
|
|
*/
|
|
|
|
static size_t generic_fuzz_crossover(const uint8_t *data1, size_t size1, const
|
|
|
|
uint8_t *data2, size_t size2, uint8_t *out,
|
|
|
|
size_t max_out_size, unsigned int seed)
|
|
|
|
{
|
|
|
|
size_t copy_len = 0, size = 0;
|
|
|
|
|
|
|
|
/* Check that we have enough space for data1 and at least part of data2 */
|
|
|
|
if (max_out_size <= size1 + strlen(SEPARATOR) * 3 + 2) {
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Copy_Len in the first input */
|
|
|
|
copy_len = size1;
|
|
|
|
memcpy(out + size, data1, copy_len);
|
|
|
|
size += copy_len;
|
|
|
|
max_out_size -= copy_len;
|
|
|
|
|
|
|
|
/* Append a separator */
|
|
|
|
copy_len = strlen(SEPARATOR);
|
|
|
|
memcpy(out + size, SEPARATOR, copy_len);
|
|
|
|
size += copy_len;
|
|
|
|
max_out_size -= copy_len;
|
|
|
|
|
|
|
|
/* Clear out the DMA Patterns */
|
|
|
|
copy_len = 1;
|
|
|
|
if (copy_len) {
|
|
|
|
out[size] = OP_CLEAR_DMA_PATTERNS;
|
|
|
|
}
|
|
|
|
size += copy_len;
|
|
|
|
max_out_size -= copy_len;
|
|
|
|
|
|
|
|
/* Append a separator */
|
|
|
|
copy_len = strlen(SEPARATOR);
|
|
|
|
memcpy(out + size, SEPARATOR, copy_len);
|
|
|
|
size += copy_len;
|
|
|
|
max_out_size -= copy_len;
|
|
|
|
|
|
|
|
/* Disable PCI ops. Assume data1 took care of setting up PCI */
|
|
|
|
copy_len = 1;
|
|
|
|
if (copy_len) {
|
|
|
|
out[size] = OP_DISABLE_PCI;
|
|
|
|
}
|
|
|
|
size += copy_len;
|
|
|
|
max_out_size -= copy_len;
|
|
|
|
|
|
|
|
/* Append a separator */
|
|
|
|
copy_len = strlen(SEPARATOR);
|
|
|
|
memcpy(out + size, SEPARATOR, copy_len);
|
|
|
|
size += copy_len;
|
|
|
|
max_out_size -= copy_len;
|
|
|
|
|
|
|
|
/* Copy_Len over the second input */
|
|
|
|
copy_len = MIN(size2, max_out_size);
|
|
|
|
memcpy(out + size, data2, copy_len);
|
|
|
|
size += copy_len;
|
|
|
|
max_out_size -= copy_len;
|
|
|
|
|
|
|
|
return size;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2020-10-23 18:07:31 +03:00
|
|
|
static GString *generic_fuzz_cmdline(FuzzTarget *t)
|
|
|
|
{
|
|
|
|
GString *cmd_line = g_string_new(TARGET_NAME);
|
|
|
|
if (!getenv("QEMU_FUZZ_ARGS")) {
|
|
|
|
usage();
|
|
|
|
}
|
|
|
|
g_string_append_printf(cmd_line, " -display none \
|
|
|
|
-machine accel=qtest, \
|
|
|
|
-m 512M %s ", getenv("QEMU_FUZZ_ARGS"));
|
|
|
|
return cmd_line;
|
|
|
|
}
|
|
|
|
|
2020-10-23 18:07:44 +03:00
|
|
|
static GString *generic_fuzz_predefined_config_cmdline(FuzzTarget *t)
|
|
|
|
{
|
2021-01-18 02:09:22 +03:00
|
|
|
gchar *args;
|
2020-10-23 18:07:44 +03:00
|
|
|
const generic_fuzz_config *config;
|
|
|
|
g_assert(t->opaque);
|
|
|
|
|
|
|
|
config = t->opaque;
|
2022-08-24 12:39:39 +03:00
|
|
|
g_setenv("QEMU_AVOID_DOUBLE_FETCH", "1", 1);
|
2021-01-18 02:09:22 +03:00
|
|
|
if (config->argfunc) {
|
|
|
|
args = config->argfunc();
|
2022-08-24 12:39:39 +03:00
|
|
|
g_setenv("QEMU_FUZZ_ARGS", args, 1);
|
2021-01-18 02:09:22 +03:00
|
|
|
g_free(args);
|
|
|
|
} else {
|
|
|
|
g_assert_nonnull(config->args);
|
2022-08-24 12:39:39 +03:00
|
|
|
g_setenv("QEMU_FUZZ_ARGS", config->args, 1);
|
2021-01-18 02:09:22 +03:00
|
|
|
}
|
2022-08-24 12:39:39 +03:00
|
|
|
g_setenv("QEMU_FUZZ_OBJECTS", config->objects, 1);
|
2020-10-23 18:07:44 +03:00
|
|
|
return generic_fuzz_cmdline(t);
|
|
|
|
}
|
|
|
|
|
2020-10-23 18:07:31 +03:00
|
|
|
static void register_generic_fuzz_targets(void)
|
|
|
|
{
|
|
|
|
fuzz_add_target(&(FuzzTarget){
|
|
|
|
.name = "generic-fuzz",
|
|
|
|
.description = "Fuzz based on any qemu command-line args. ",
|
|
|
|
.get_init_cmdline = generic_fuzz_cmdline,
|
|
|
|
.pre_fuzz = generic_pre_fuzz,
|
|
|
|
.fuzz = generic_fuzz,
|
2020-10-23 18:07:38 +03:00
|
|
|
.crossover = generic_fuzz_crossover
|
2020-10-23 18:07:31 +03:00
|
|
|
});
|
2020-10-23 18:07:44 +03:00
|
|
|
|
|
|
|
GString *name;
|
|
|
|
const generic_fuzz_config *config;
|
|
|
|
|
|
|
|
for (int i = 0;
|
|
|
|
i < sizeof(predefined_configs) / sizeof(generic_fuzz_config);
|
|
|
|
i++) {
|
|
|
|
config = predefined_configs + i;
|
|
|
|
name = g_string_new("generic-fuzz");
|
|
|
|
g_string_append_printf(name, "-%s", config->name);
|
|
|
|
fuzz_add_target(&(FuzzTarget){
|
|
|
|
.name = name->str,
|
|
|
|
.description = "Predefined generic-fuzz config.",
|
|
|
|
.get_init_cmdline = generic_fuzz_predefined_config_cmdline,
|
|
|
|
.pre_fuzz = generic_pre_fuzz,
|
|
|
|
.fuzz = generic_fuzz,
|
|
|
|
.crossover = generic_fuzz_crossover,
|
|
|
|
.opaque = (void *)config
|
|
|
|
});
|
|
|
|
}
|
2020-10-23 18:07:31 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
fuzz_target_init(register_generic_fuzz_targets);
|