2012-04-02 13:39:23 +04:00
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/*
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* QEMU S/390 CPU
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*
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2012-04-02 15:31:59 +04:00
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* Copyright (c) 2009 Ulrich Hecht
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* Copyright (c) 2011 Alexander Graf
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2012-04-02 13:39:23 +04:00
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* Copyright (c) 2012 SUSE LINUX Products GmbH
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2013-01-07 09:27:14 +04:00
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* Copyright (c) 2012 IBM Corp.
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2012-04-02 13:39:23 +04:00
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see
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* <http://www.gnu.org/licenses/lgpl-2.1.html>
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2013-01-07 09:27:14 +04:00
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* Contributions after 2012-12-11 are licensed under the terms of the
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* GNU GPL, version 2 or (at your option) any later version.
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2012-04-02 13:39:23 +04:00
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*/
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2012-05-03 06:13:04 +04:00
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#include "cpu.h"
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2012-04-02 13:39:23 +04:00
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#include "qemu-common.h"
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2012-12-17 21:20:00 +04:00
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#include "qemu/timer.h"
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2014-09-30 12:57:29 +04:00
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#include "qemu/error-report.h"
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2013-01-07 09:27:14 +04:00
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#include "hw/hw.h"
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2014-09-30 12:57:29 +04:00
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#include "trace.h"
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2013-01-20 22:41:06 +04:00
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#ifndef CONFIG_USER_ONLY
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2012-12-18 11:50:59 +04:00
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#include "sysemu/arch_init.h"
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#endif
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2013-01-07 09:27:14 +04:00
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#define CR0_RESET 0xE0UL
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#define CR14_RESET 0xC2000000UL;
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2012-12-18 11:50:59 +04:00
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/* generate CPU information for cpu -? */
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void s390_cpu_list(FILE *f, fprintf_function cpu_fprintf)
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{
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#ifdef CONFIG_KVM
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(*cpu_fprintf)(f, "s390 %16s\n", "host");
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#endif
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}
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2012-04-02 13:39:23 +04:00
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2012-12-18 11:50:59 +04:00
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#ifndef CONFIG_USER_ONLY
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CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
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{
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CpuDefinitionInfoList *entry;
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CpuDefinitionInfo *info;
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info = g_malloc0(sizeof(*info));
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info->name = g_strdup("host");
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entry = g_malloc0(sizeof(*entry));
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entry->value = info;
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return entry;
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}
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#endif
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2012-04-02 13:39:23 +04:00
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2013-06-21 21:09:18 +04:00
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static void s390_cpu_set_pc(CPUState *cs, vaddr value)
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{
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S390CPU *cpu = S390_CPU(cs);
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cpu->env.psw.addr = value;
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}
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2013-08-25 20:53:55 +04:00
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static bool s390_cpu_has_work(CPUState *cs)
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{
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S390CPU *cpu = S390_CPU(cs);
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CPUS390XState *env = &cpu->env;
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return (cs->interrupt_request & CPU_INTERRUPT_HARD) &&
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(env->psw.mask & PSW_MASK_EXT);
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}
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2013-07-25 18:45:51 +04:00
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#if !defined(CONFIG_USER_ONLY)
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/* S390CPUClass::load_normal() */
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static void s390_cpu_load_normal(CPUState *s)
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{
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S390CPU *cpu = S390_CPU(s);
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2013-11-15 17:46:38 +04:00
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cpu->env.psw.addr = ldl_phys(s->as, 4) & PSW_MASK_ESA_ADDR;
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2013-07-25 18:45:51 +04:00
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cpu->env.psw.mask = PSW_MASK_32 | PSW_MASK_64;
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2014-09-30 12:57:29 +04:00
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s390_cpu_set_state(CPU_STATE_OPERATING, cpu);
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2013-07-25 18:45:51 +04:00
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}
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#endif
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s390/cpu: split CPU reset into architectured functions
s390 provides several CPU resets:
- CPU reset, clears interrupts, stop processing, clears TLB, but does
not touch registers
- initial CPU reset, like CPU reset, but also clears PSW, prefix, FPC,
timer and control registers. It does not touch gprs, fprs and acrs (!)
- Power on reset: the full monty
wire up CPUClass reset to the full monty, but provide the lesser resets
as part of S390CPUClass.
Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com>
2013-06-28 12:51:09 +04:00
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/* S390CPUClass::cpu_reset() */
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2012-04-02 13:39:23 +04:00
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static void s390_cpu_reset(CPUState *s)
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{
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S390CPU *cpu = S390_CPU(s);
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S390CPUClass *scc = S390_CPU_GET_CLASS(cpu);
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CPUS390XState *env = &cpu->env;
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2013-09-05 15:54:39 +04:00
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env->pfault_token = -1UL;
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s390/cpu: split CPU reset into architectured functions
s390 provides several CPU resets:
- CPU reset, clears interrupts, stop processing, clears TLB, but does
not touch registers
- initial CPU reset, like CPU reset, but also clears PSW, prefix, FPC,
timer and control registers. It does not touch gprs, fprs and acrs (!)
- Power on reset: the full monty
wire up CPUClass reset to the full monty, but provide the lesser resets
as part of S390CPUClass.
Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com>
2013-06-28 12:51:09 +04:00
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scc->parent_reset(s);
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2015-02-24 16:15:27 +03:00
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cpu->env.sigp_order = 0;
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2014-09-30 12:57:29 +04:00
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s390_cpu_set_state(CPU_STATE_STOPPED, cpu);
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2013-09-04 04:19:44 +04:00
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tlb_flush(s, 1);
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s390/cpu: split CPU reset into architectured functions
s390 provides several CPU resets:
- CPU reset, clears interrupts, stop processing, clears TLB, but does
not touch registers
- initial CPU reset, like CPU reset, but also clears PSW, prefix, FPC,
timer and control registers. It does not touch gprs, fprs and acrs (!)
- Power on reset: the full monty
wire up CPUClass reset to the full monty, but provide the lesser resets
as part of S390CPUClass.
Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com>
2013-06-28 12:51:09 +04:00
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}
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/* S390CPUClass::initial_reset() */
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static void s390_cpu_initial_reset(CPUState *s)
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{
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S390CPU *cpu = S390_CPU(s);
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CPUS390XState *env = &cpu->env;
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2015-06-15 18:57:05 +03:00
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int i;
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s390/cpu: split CPU reset into architectured functions
s390 provides several CPU resets:
- CPU reset, clears interrupts, stop processing, clears TLB, but does
not touch registers
- initial CPU reset, like CPU reset, but also clears PSW, prefix, FPC,
timer and control registers. It does not touch gprs, fprs and acrs (!)
- Power on reset: the full monty
wire up CPUClass reset to the full monty, but provide the lesser resets
as part of S390CPUClass.
Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com>
2013-06-28 12:51:09 +04:00
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s390_cpu_reset(s);
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/* initial reset does not touch regs,fregs and aregs */
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2013-08-26 23:22:53 +04:00
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memset(&env->fpc, 0, offsetof(CPUS390XState, cpu_num) -
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s390/cpu: split CPU reset into architectured functions
s390 provides several CPU resets:
- CPU reset, clears interrupts, stop processing, clears TLB, but does
not touch registers
- initial CPU reset, like CPU reset, but also clears PSW, prefix, FPC,
timer and control registers. It does not touch gprs, fprs and acrs (!)
- Power on reset: the full monty
wire up CPUClass reset to the full monty, but provide the lesser resets
as part of S390CPUClass.
Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com>
2013-06-28 12:51:09 +04:00
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offsetof(CPUS390XState, fpc));
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/* architectured initial values for CR 0 and 14 */
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env->cregs[0] = CR0_RESET;
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env->cregs[14] = CR14_RESET;
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2013-09-05 15:54:39 +04:00
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2015-06-13 01:46:03 +03:00
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/* architectured initial value for Breaking-Event-Address register */
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env->gbea = 1;
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2013-09-05 15:54:39 +04:00
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env->pfault_token = -1UL;
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2015-06-15 18:57:04 +03:00
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env->ext_index = -1;
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2015-06-15 18:57:05 +03:00
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for (i = 0; i < ARRAY_SIZE(env->io_index); i++) {
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env->io_index[i] = -1;
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}
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2014-02-12 12:56:35 +04:00
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2015-05-25 02:47:26 +03:00
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/* tininess for underflow is detected before rounding */
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set_float_detect_tininess(float_tininess_before_rounding,
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&env->fpu_status);
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2014-02-12 12:56:35 +04:00
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/* Reset state inside the kernel that we cannot access yet from QEMU. */
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if (kvm_enabled()) {
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2014-09-30 12:57:31 +04:00
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kvm_s390_reset_vcpu(cpu);
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2014-02-12 12:56:35 +04:00
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}
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2015-06-15 18:57:06 +03:00
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tlb_flush(s, 1);
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s390/cpu: split CPU reset into architectured functions
s390 provides several CPU resets:
- CPU reset, clears interrupts, stop processing, clears TLB, but does
not touch registers
- initial CPU reset, like CPU reset, but also clears PSW, prefix, FPC,
timer and control registers. It does not touch gprs, fprs and acrs (!)
- Power on reset: the full monty
wire up CPUClass reset to the full monty, but provide the lesser resets
as part of S390CPUClass.
Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com>
2013-06-28 12:51:09 +04:00
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}
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/* CPUClass:reset() */
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static void s390_cpu_full_reset(CPUState *s)
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{
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S390CPU *cpu = S390_CPU(s);
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S390CPUClass *scc = S390_CPU_GET_CLASS(cpu);
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CPUS390XState *env = &cpu->env;
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2015-06-15 18:57:05 +03:00
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int i;
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s390/cpu: split CPU reset into architectured functions
s390 provides several CPU resets:
- CPU reset, clears interrupts, stop processing, clears TLB, but does
not touch registers
- initial CPU reset, like CPU reset, but also clears PSW, prefix, FPC,
timer and control registers. It does not touch gprs, fprs and acrs (!)
- Power on reset: the full monty
wire up CPUClass reset to the full monty, but provide the lesser resets
as part of S390CPUClass.
Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com>
2013-06-28 12:51:09 +04:00
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2012-04-02 13:39:23 +04:00
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scc->parent_reset(s);
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2015-02-24 16:15:27 +03:00
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cpu->env.sigp_order = 0;
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2014-09-30 12:57:29 +04:00
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s390_cpu_set_state(CPU_STATE_STOPPED, cpu);
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2012-04-02 13:39:23 +04:00
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2013-08-26 23:22:53 +04:00
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memset(env, 0, offsetof(CPUS390XState, cpu_num));
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2013-01-07 09:27:14 +04:00
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/* architectured initial values for CR 0 and 14 */
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env->cregs[0] = CR0_RESET;
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env->cregs[14] = CR14_RESET;
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2013-09-05 15:54:39 +04:00
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2015-06-13 01:46:03 +03:00
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/* architectured initial value for Breaking-Event-Address register */
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env->gbea = 1;
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2013-09-05 15:54:39 +04:00
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env->pfault_token = -1UL;
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2015-06-15 18:57:04 +03:00
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env->ext_index = -1;
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2015-06-15 18:57:05 +03:00
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for (i = 0; i < ARRAY_SIZE(env->io_index); i++) {
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env->io_index[i] = -1;
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}
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2013-09-05 15:54:39 +04:00
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2015-05-25 02:47:26 +03:00
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/* tininess for underflow is detected before rounding */
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set_float_detect_tininess(float_tininess_before_rounding,
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&env->fpu_status);
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2014-09-30 12:57:31 +04:00
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/* Reset state inside the kernel that we cannot access yet from QEMU. */
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2013-03-20 16:11:56 +04:00
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if (kvm_enabled()) {
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kvm_s390_reset_vcpu(cpu);
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}
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2013-09-04 04:19:44 +04:00
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tlb_flush(s, 1);
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2012-04-02 13:39:23 +04:00
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}
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2013-01-07 09:27:14 +04:00
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#if !defined(CONFIG_USER_ONLY)
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static void s390_cpu_machine_reset_cb(void *opaque)
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{
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S390CPU *cpu = opaque;
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2014-08-28 15:58:51 +04:00
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run_on_cpu(CPU(cpu), s390_do_cpu_full_reset, CPU(cpu));
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2013-01-07 09:27:14 +04:00
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}
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#endif
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2013-01-16 07:00:41 +04:00
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static void s390_cpu_realizefn(DeviceState *dev, Error **errp)
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{
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2013-07-27 04:53:25 +04:00
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CPUState *cs = CPU(dev);
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2013-01-16 07:00:41 +04:00
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S390CPUClass *scc = S390_CPU_GET_CLASS(dev);
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2014-08-29 17:52:16 +04:00
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s390_cpu_gdb_init(cs);
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2013-07-27 04:53:25 +04:00
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qemu_init_vcpu(cs);
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2014-08-28 15:58:52 +04:00
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#if !defined(CONFIG_USER_ONLY)
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run_on_cpu(cs, s390_do_cpu_full_reset, cs);
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#else
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2013-07-27 04:53:25 +04:00
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cpu_reset(cs);
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2014-08-28 15:58:52 +04:00
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#endif
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2013-01-16 07:00:41 +04:00
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scc->parent_realize(dev, errp);
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}
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2012-04-02 15:56:29 +04:00
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static void s390_cpu_initfn(Object *obj)
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{
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2013-01-17 15:13:41 +04:00
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CPUState *cs = CPU(obj);
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2012-04-02 15:56:29 +04:00
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S390CPU *cpu = S390_CPU(obj);
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CPUS390XState *env = &cpu->env;
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2013-01-20 01:43:32 +04:00
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static bool inited;
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2012-04-02 15:56:29 +04:00
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static int cpu_num = 0;
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#if !defined(CONFIG_USER_ONLY)
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struct tm tm;
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#endif
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2013-01-17 15:13:41 +04:00
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cs->env_ptr = env;
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2015-06-24 05:31:18 +03:00
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cpu_exec_init(cs, &error_abort);
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2012-04-02 15:56:29 +04:00
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#if !defined(CONFIG_USER_ONLY)
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2013-01-07 09:27:14 +04:00
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qemu_register_reset(s390_cpu_machine_reset_cb, cpu);
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2012-04-02 15:56:29 +04:00
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qemu_get_timedate(&tm, 0);
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env->tod_offset = TOD_UNIX_EPOCH +
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(time2tod(mktimegm(&tm)) * 1000000000ULL);
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env->tod_basetime = 0;
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2013-08-21 19:03:08 +04:00
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env->tod_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, s390x_tod_timer, cpu);
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env->cpu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, s390x_cpu_timer, cpu);
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2014-09-30 12:57:29 +04:00
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s390_cpu_set_state(CPU_STATE_STOPPED, cpu);
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2012-04-02 15:56:29 +04:00
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#endif
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env->cpu_num = cpu_num++;
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2013-01-20 01:43:32 +04:00
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if (tcg_enabled() && !inited) {
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inited = true;
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s390x_translate_init();
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}
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2012-04-02 15:56:29 +04:00
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}
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2013-01-07 10:14:16 +04:00
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static void s390_cpu_finalize(Object *obj)
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{
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#if !defined(CONFIG_USER_ONLY)
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S390CPU *cpu = S390_CPU(obj);
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qemu_unregister_reset(s390_cpu_machine_reset_cb, cpu);
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2015-03-02 19:44:24 +03:00
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g_free(cpu->irqstate);
|
2013-01-07 10:14:16 +04:00
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#endif
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}
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2014-09-30 12:57:28 +04:00
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#if !defined(CONFIG_USER_ONLY)
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2014-09-30 12:57:29 +04:00
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static bool disabled_wait(CPUState *cpu)
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{
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return cpu->halted && !(S390_CPU(cpu)->env.psw.mask &
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(PSW_MASK_IO | PSW_MASK_EXT | PSW_MASK_MCHECK));
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}
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2014-09-30 12:57:28 +04:00
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static unsigned s390_count_running_cpus(void)
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{
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CPUState *cpu;
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int nr_running = 0;
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CPU_FOREACH(cpu) {
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uint8_t state = S390_CPU(cpu)->env.cpu_state;
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if (state == CPU_STATE_OPERATING ||
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state == CPU_STATE_LOAD) {
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2014-09-30 12:57:29 +04:00
|
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if (!disabled_wait(cpu)) {
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nr_running++;
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}
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2014-09-30 12:57:28 +04:00
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}
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}
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return nr_running;
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}
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2014-09-30 12:57:29 +04:00
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unsigned int s390_cpu_halt(S390CPU *cpu)
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2014-09-30 12:57:28 +04:00
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{
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CPUState *cs = CPU(cpu);
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2014-09-30 12:57:29 +04:00
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trace_cpu_halt(cs->cpu_index);
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2014-09-30 12:57:28 +04:00
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2014-09-30 12:57:29 +04:00
|
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if (!cs->halted) {
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cs->halted = 1;
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cs->exception_index = EXCP_HLT;
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2014-09-30 12:57:28 +04:00
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}
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2014-09-30 12:57:29 +04:00
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return s390_count_running_cpus();
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2014-09-30 12:57:28 +04:00
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}
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2014-09-30 12:57:29 +04:00
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void s390_cpu_unhalt(S390CPU *cpu)
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2014-09-30 12:57:28 +04:00
|
|
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{
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CPUState *cs = CPU(cpu);
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2014-09-30 12:57:29 +04:00
|
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trace_cpu_unhalt(cs->cpu_index);
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2014-09-30 12:57:28 +04:00
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2014-09-30 12:57:29 +04:00
|
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|
if (cs->halted) {
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cs->halted = 0;
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cs->exception_index = -1;
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}
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}
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unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu)
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|
|
|
{
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|
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|
trace_cpu_set_state(CPU(cpu)->cpu_index, cpu_state);
|
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|
switch (cpu_state) {
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case CPU_STATE_STOPPED:
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case CPU_STATE_CHECK_STOP:
|
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|
|
/* halt the cpu for common infrastructure */
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|
|
s390_cpu_halt(cpu);
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|
break;
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case CPU_STATE_OPERATING:
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case CPU_STATE_LOAD:
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|
|
/* unhalt the cpu for common infrastructure */
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|
|
s390_cpu_unhalt(cpu);
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|
break;
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|
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default:
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|
|
error_report("Requested CPU state is not a valid S390 CPU state: %u",
|
|
|
|
cpu_state);
|
|
|
|
exit(1);
|
2014-09-30 12:57:28 +04:00
|
|
|
}
|
2014-09-30 12:57:30 +04:00
|
|
|
if (kvm_enabled() && cpu->env.cpu_state != cpu_state) {
|
|
|
|
kvm_s390_set_cpu_state(cpu, cpu_state);
|
|
|
|
}
|
2014-09-30 12:57:29 +04:00
|
|
|
cpu->env.cpu_state = cpu_state;
|
2014-09-30 12:57:28 +04:00
|
|
|
|
|
|
|
return s390_count_running_cpus();
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2012-04-02 13:39:23 +04:00
|
|
|
static void s390_cpu_class_init(ObjectClass *oc, void *data)
|
|
|
|
{
|
|
|
|
S390CPUClass *scc = S390_CPU_CLASS(oc);
|
|
|
|
CPUClass *cc = CPU_CLASS(scc);
|
2013-01-20 22:41:06 +04:00
|
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
2012-04-02 13:39:23 +04:00
|
|
|
|
2013-01-16 07:00:41 +04:00
|
|
|
scc->parent_realize = dc->realize;
|
|
|
|
dc->realize = s390_cpu_realizefn;
|
|
|
|
|
2012-04-02 13:39:23 +04:00
|
|
|
scc->parent_reset = cc->reset;
|
2013-07-25 18:45:51 +04:00
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
|
|
|
scc->load_normal = s390_cpu_load_normal;
|
|
|
|
#endif
|
s390/cpu: split CPU reset into architectured functions
s390 provides several CPU resets:
- CPU reset, clears interrupts, stop processing, clears TLB, but does
not touch registers
- initial CPU reset, like CPU reset, but also clears PSW, prefix, FPC,
timer and control registers. It does not touch gprs, fprs and acrs (!)
- Power on reset: the full monty
wire up CPUClass reset to the full monty, but provide the lesser resets
as part of S390CPUClass.
Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com>
2013-06-28 12:51:09 +04:00
|
|
|
scc->cpu_reset = s390_cpu_reset;
|
|
|
|
scc->initial_cpu_reset = s390_cpu_initial_reset;
|
|
|
|
cc->reset = s390_cpu_full_reset;
|
2013-08-25 20:53:55 +04:00
|
|
|
cc->has_work = s390_cpu_has_work;
|
2013-02-02 13:57:51 +04:00
|
|
|
cc->do_interrupt = s390_cpu_do_interrupt;
|
2013-05-27 03:33:50 +04:00
|
|
|
cc->dump_state = s390_cpu_dump_state;
|
2013-06-21 21:09:18 +04:00
|
|
|
cc->set_pc = s390_cpu_set_pc;
|
2013-06-29 06:18:45 +04:00
|
|
|
cc->gdb_read_register = s390_cpu_gdb_read_register;
|
|
|
|
cc->gdb_write_register = s390_cpu_gdb_write_register;
|
2013-08-26 05:01:33 +04:00
|
|
|
#ifdef CONFIG_USER_ONLY
|
|
|
|
cc->handle_mmu_fault = s390_cpu_handle_mmu_fault;
|
|
|
|
#else
|
2013-06-29 20:55:54 +04:00
|
|
|
cc->get_phys_page_debug = s390_cpu_get_phys_page_debug;
|
2014-09-30 12:58:42 +04:00
|
|
|
cc->vmsd = &vmstate_s390_cpu;
|
2013-07-10 17:26:46 +04:00
|
|
|
cc->write_elf64_note = s390_cpu_write_elf64_note;
|
|
|
|
cc->write_elf64_qemunote = s390_cpu_write_elf64_qemunote;
|
2014-09-13 20:45:19 +04:00
|
|
|
cc->cpu_exec_interrupt = s390_cpu_exec_interrupt;
|
2015-06-13 01:46:00 +03:00
|
|
|
cc->debug_excp_handler = s390x_cpu_debug_excp_handler;
|
2013-06-29 20:55:54 +04:00
|
|
|
#endif
|
2014-08-29 17:52:16 +04:00
|
|
|
cc->gdb_num_core_regs = S390_NUM_CORE_REGS;
|
|
|
|
cc->gdb_core_xml_file = "s390x-core64.xml";
|
2012-04-02 13:39:23 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
static const TypeInfo s390_cpu_type_info = {
|
|
|
|
.name = TYPE_S390_CPU,
|
|
|
|
.parent = TYPE_CPU,
|
|
|
|
.instance_size = sizeof(S390CPU),
|
2012-04-02 15:56:29 +04:00
|
|
|
.instance_init = s390_cpu_initfn,
|
2013-01-07 10:14:16 +04:00
|
|
|
.instance_finalize = s390_cpu_finalize,
|
2012-04-02 13:39:23 +04:00
|
|
|
.abstract = false,
|
|
|
|
.class_size = sizeof(S390CPUClass),
|
|
|
|
.class_init = s390_cpu_class_init,
|
|
|
|
};
|
|
|
|
|
|
|
|
static void s390_cpu_register_types(void)
|
|
|
|
{
|
|
|
|
type_register_static(&s390_cpu_type_info);
|
|
|
|
}
|
|
|
|
|
|
|
|
type_init(s390_cpu_register_types)
|