target/loongarch: Add fixed point arithmetic instruction translation
This includes:
- ADD.{W/D}, SUB.{W/D}
- ADDI.{W/D}, ADDU16ID
- ALSL.{W[U]/D}
- LU12I.W, LU32I.D LU52I.D
- SLT[U], SLT[U]I
- PCADDI, PCADDU12I, PCADDU18I, PCALAU12I
- AND, OR, NOR, XOR, ANDN, ORN
- MUL.{W/D}, MULH.{W[U]/D[U]}
- MULW.D.W[U]
- DIV.{W[U]/D[U]}, MOD.{W[U]/D[U]}
- ANDI, ORI, XORI
Signed-off-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220606124333.2060567-5-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 15:42:54 +03:00
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# SPDX-License-Identifier: GPL-2.0-or-later
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#
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# LoongArch instruction decode definitions.
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#
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# Copyright (c) 2021 Loongson Technology Corporation Limited
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#
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#
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# Fields
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#
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2022-06-06 15:42:57 +03:00
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%i14s2 10:s14 !function=shl_2
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target/loongarch: Add fixed point arithmetic instruction translation
This includes:
- ADD.{W/D}, SUB.{W/D}
- ADDI.{W/D}, ADDU16ID
- ALSL.{W[U]/D}
- LU12I.W, LU32I.D LU52I.D
- SLT[U], SLT[U]I
- PCADDI, PCADDU12I, PCADDU18I, PCALAU12I
- AND, OR, NOR, XOR, ANDN, ORN
- MUL.{W/D}, MULH.{W[U]/D[U]}
- MULW.D.W[U]
- DIV.{W[U]/D[U]}, MOD.{W[U]/D[U]}
- ANDI, ORI, XORI
Signed-off-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220606124333.2060567-5-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 15:42:54 +03:00
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%sa2p1 15:2 !function=plus_1
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2022-06-06 15:43:05 +03:00
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%offs21 0:s5 10:16 !function=shl_2
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%offs16 10:s16 !function=shl_2
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%offs26 0:s10 10:16 !function=shl_2
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target/loongarch: Add fixed point arithmetic instruction translation
This includes:
- ADD.{W/D}, SUB.{W/D}
- ADDI.{W/D}, ADDU16ID
- ALSL.{W[U]/D}
- LU12I.W, LU32I.D LU52I.D
- SLT[U], SLT[U]I
- PCADDI, PCADDU12I, PCADDU18I, PCALAU12I
- AND, OR, NOR, XOR, ANDN, ORN
- MUL.{W/D}, MULH.{W[U]/D[U]}
- MULW.D.W[U]
- DIV.{W[U]/D[U]}, MOD.{W[U]/D[U]}
- ANDI, ORI, XORI
Signed-off-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220606124333.2060567-5-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 15:42:54 +03:00
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#
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# Argument sets
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#
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2022-06-06 15:42:57 +03:00
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&i imm
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target/loongarch: Add fixed point arithmetic instruction translation
This includes:
- ADD.{W/D}, SUB.{W/D}
- ADDI.{W/D}, ADDU16ID
- ALSL.{W[U]/D}
- LU12I.W, LU32I.D LU52I.D
- SLT[U], SLT[U]I
- PCADDI, PCADDU12I, PCADDU18I, PCALAU12I
- AND, OR, NOR, XOR, ANDN, ORN
- MUL.{W/D}, MULH.{W[U]/D[U]}
- MULW.D.W[U]
- DIV.{W[U]/D[U]}, MOD.{W[U]/D[U]}
- ANDI, ORI, XORI
Signed-off-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220606124333.2060567-5-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 15:42:54 +03:00
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&r_i rd imm
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2022-06-06 15:42:56 +03:00
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&rr rd rj
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2022-06-06 15:42:59 +03:00
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&rr_jk rj rk
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target/loongarch: Add fixed point arithmetic instruction translation
This includes:
- ADD.{W/D}, SUB.{W/D}
- ADDI.{W/D}, ADDU16ID
- ALSL.{W[U]/D}
- LU12I.W, LU32I.D LU52I.D
- SLT[U], SLT[U]I
- PCADDI, PCADDU12I, PCADDU18I, PCALAU12I
- AND, OR, NOR, XOR, ANDN, ORN
- MUL.{W/D}, MULH.{W[U]/D[U]}
- MULW.D.W[U]
- DIV.{W[U]/D[U]}, MOD.{W[U]/D[U]}
- ANDI, ORI, XORI
Signed-off-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220606124333.2060567-5-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 15:42:54 +03:00
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&rrr rd rj rk
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&rr_i rd rj imm
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2022-06-06 15:42:57 +03:00
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&hint_r_i hint rj imm
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target/loongarch: Add fixed point arithmetic instruction translation
This includes:
- ADD.{W/D}, SUB.{W/D}
- ADDI.{W/D}, ADDU16ID
- ALSL.{W[U]/D}
- LU12I.W, LU32I.D LU52I.D
- SLT[U], SLT[U]I
- PCADDI, PCADDU12I, PCADDU18I, PCALAU12I
- AND, OR, NOR, XOR, ANDN, ORN
- MUL.{W/D}, MULH.{W[U]/D[U]}
- MULW.D.W[U]
- DIV.{W[U]/D[U]}, MOD.{W[U]/D[U]}
- ANDI, ORI, XORI
Signed-off-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220606124333.2060567-5-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 15:42:54 +03:00
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&rrr_sa rd rj rk sa
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2022-06-06 15:42:56 +03:00
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&rr_ms_ls rd rj ms ls
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2022-06-06 15:43:00 +03:00
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&ff fd fj
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&fff fd fj fk
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&ffff fd fj fk fa
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2022-06-06 15:43:01 +03:00
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&cff_fcond cd fj fk fcond
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2022-06-06 15:43:03 +03:00
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&fffc fd fj fk ca
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&fr fd rj
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&rf rd fj
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&fcsrd_r fcsrd rj
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&r_fcsrs rd fcsrs
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&cf cd fj
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&fc fd cj
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&cr cd rj
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&rc rd cj
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2022-06-06 15:43:04 +03:00
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&frr fd rj rk
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&fr_i fd rj imm
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2022-06-06 15:43:05 +03:00
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&r_offs rj offs
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&c_offs cj offs
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&offs offs
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&rr_offs rj rd offs
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2022-06-06 15:43:15 +03:00
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&r_csr rd csr
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&rr_csr rd rj csr
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2022-06-06 15:43:17 +03:00
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&empty
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&i_rr imm rj rk
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2022-06-06 15:43:18 +03:00
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&cop_r_i cop rj imm
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&j_i rj imm
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target/loongarch: Add fixed point arithmetic instruction translation
This includes:
- ADD.{W/D}, SUB.{W/D}
- ADDI.{W/D}, ADDU16ID
- ALSL.{W[U]/D}
- LU12I.W, LU32I.D LU52I.D
- SLT[U], SLT[U]I
- PCADDI, PCADDU12I, PCADDU18I, PCALAU12I
- AND, OR, NOR, XOR, ANDN, ORN
- MUL.{W/D}, MULH.{W[U]/D[U]}
- MULW.D.W[U]
- DIV.{W[U]/D[U]}, MOD.{W[U]/D[U]}
- ANDI, ORI, XORI
Signed-off-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220606124333.2060567-5-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 15:42:54 +03:00
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#
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# Formats
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#
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2022-06-06 15:42:57 +03:00
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@i15 .... ........ ..... imm:15 &i
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2022-06-06 15:42:56 +03:00
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@rr .... ........ ..... ..... rj:5 rd:5 &rr
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2022-06-06 15:42:59 +03:00
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@rr_jk .... ........ ..... rk:5 rj:5 ..... &rr_jk
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target/loongarch: Add fixed point arithmetic instruction translation
This includes:
- ADD.{W/D}, SUB.{W/D}
- ADDI.{W/D}, ADDU16ID
- ALSL.{W[U]/D}
- LU12I.W, LU32I.D LU52I.D
- SLT[U], SLT[U]I
- PCADDI, PCADDU12I, PCADDU18I, PCALAU12I
- AND, OR, NOR, XOR, ANDN, ORN
- MUL.{W/D}, MULH.{W[U]/D[U]}
- MULW.D.W[U]
- DIV.{W[U]/D[U]}, MOD.{W[U]/D[U]}
- ANDI, ORI, XORI
Signed-off-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220606124333.2060567-5-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 15:42:54 +03:00
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@rrr .... ........ ..... rk:5 rj:5 rd:5 &rrr
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@r_i20 .... ... imm:s20 rd:5 &r_i
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target/loongarch: Add fixed point shift instruction translation
This includes:
- SLL.W, SRL.W, SRA.W, ROTR.W
- SLLI.W, SRLI.W, SRAI.W, ROTRI.W
- SLL.D, SRL.D, SRA.D, ROTR.D
- SLLI.D, SRLI.D, SRAI.D, ROTRI.D
Signed-off-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220606124333.2060567-6-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 15:42:55 +03:00
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@rr_ui5 .... ........ ..... imm:5 rj:5 rd:5 &rr_i
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@rr_ui6 .... ........ .... imm:6 rj:5 rd:5 &rr_i
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2022-06-06 15:43:18 +03:00
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@rr_ui8 .. ........ .... imm:8 rj:5 rd:5 &rr_i
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target/loongarch: Add fixed point arithmetic instruction translation
This includes:
- ADD.{W/D}, SUB.{W/D}
- ADDI.{W/D}, ADDU16ID
- ALSL.{W[U]/D}
- LU12I.W, LU32I.D LU52I.D
- SLT[U], SLT[U]I
- PCADDI, PCADDU12I, PCADDU18I, PCALAU12I
- AND, OR, NOR, XOR, ANDN, ORN
- MUL.{W/D}, MULH.{W[U]/D[U]}
- MULW.D.W[U]
- DIV.{W[U]/D[U]}, MOD.{W[U]/D[U]}
- ANDI, ORI, XORI
Signed-off-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220606124333.2060567-5-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 15:42:54 +03:00
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@rr_i12 .... ...... imm:s12 rj:5 rd:5 &rr_i
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@rr_ui12 .... ...... imm:12 rj:5 rd:5 &rr_i
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2022-06-06 15:42:57 +03:00
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@rr_i14s2 .... .... .............. rj:5 rd:5 &rr_i imm=%i14s2
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target/loongarch: Add fixed point arithmetic instruction translation
This includes:
- ADD.{W/D}, SUB.{W/D}
- ADDI.{W/D}, ADDU16ID
- ALSL.{W[U]/D}
- LU12I.W, LU32I.D LU52I.D
- SLT[U], SLT[U]I
- PCADDI, PCADDU12I, PCADDU18I, PCALAU12I
- AND, OR, NOR, XOR, ANDN, ORN
- MUL.{W/D}, MULH.{W[U]/D[U]}
- MULW.D.W[U]
- DIV.{W[U]/D[U]}, MOD.{W[U]/D[U]}
- ANDI, ORI, XORI
Signed-off-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220606124333.2060567-5-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 15:42:54 +03:00
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@rr_i16 .... .. imm:s16 rj:5 rd:5 &rr_i
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2022-06-06 15:42:57 +03:00
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@hint_r_i12 .... ...... imm:s12 rj:5 hint:5 &hint_r_i
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target/loongarch: Add fixed point arithmetic instruction translation
This includes:
- ADD.{W/D}, SUB.{W/D}
- ADDI.{W/D}, ADDU16ID
- ALSL.{W[U]/D}
- LU12I.W, LU32I.D LU52I.D
- SLT[U], SLT[U]I
- PCADDI, PCADDU12I, PCADDU18I, PCALAU12I
- AND, OR, NOR, XOR, ANDN, ORN
- MUL.{W/D}, MULH.{W[U]/D[U]}
- MULW.D.W[U]
- DIV.{W[U]/D[U]}, MOD.{W[U]/D[U]}
- ANDI, ORI, XORI
Signed-off-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220606124333.2060567-5-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 15:42:54 +03:00
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@rrr_sa2p1 .... ........ ... .. rk:5 rj:5 rd:5 &rrr_sa sa=%sa2p1
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2022-06-06 15:42:56 +03:00
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@rrr_sa2 .... ........ ... sa:2 rk:5 rj:5 rd:5 &rrr_sa
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@rrr_sa3 .... ........ .. sa:3 rk:5 rj:5 rd:5 &rrr_sa
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@rr_2bw .... ....... ms:5 . ls:5 rj:5 rd:5 &rr_ms_ls
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@rr_2bd .... ...... ms:6 ls:6 rj:5 rd:5 &rr_ms_ls
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2022-06-06 15:43:00 +03:00
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@ff .... ........ ..... ..... fj:5 fd:5 &ff
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@fff .... ........ ..... fk:5 fj:5 fd:5 &fff
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@ffff .... ........ fa:5 fk:5 fj:5 fd:5 &ffff
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2022-06-06 15:43:01 +03:00
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@cff_fcond .... ........ fcond:5 fk:5 fj:5 .. cd:3 &cff_fcond
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2022-06-06 15:43:03 +03:00
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@fffc .... ........ .. ca:3 fk:5 fj:5 fd:5 &fffc
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@fr .... ........ ..... ..... rj:5 fd:5 &fr
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@rf .... ........ ..... ..... fj:5 rd:5 &rf
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@fcsrd_r .... ........ ..... ..... rj:5 fcsrd:5 &fcsrd_r
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@r_fcsrs .... ........ ..... ..... fcsrs:5 rd:5 &r_fcsrs
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@cf .... ........ ..... ..... fj:5 .. cd:3 &cf
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@fc .... ........ ..... ..... .. cj:3 fd:5 &fc
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@cr .... ........ ..... ..... rj:5 .. cd:3 &cr
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@rc .... ........ ..... ..... .. cj:3 rd:5 &rc
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2022-06-06 15:43:04 +03:00
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@frr .... ........ ..... rk:5 rj:5 fd:5 &frr
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@fr_i12 .... ...... imm:s12 rj:5 fd:5 &fr_i
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2022-06-06 15:43:05 +03:00
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@r_offs21 .... .. ................ rj:5 ..... &r_offs offs=%offs21
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@c_offs21 .... .. ................ .. cj:3 ..... &c_offs offs=%offs21
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@offs26 .... .. .......................... &offs offs=%offs26
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@rr_offs16 .... .. ................ rj:5 rd:5 &rr_offs offs=%offs16
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2022-06-06 15:43:15 +03:00
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@r_csr .... .... csr:14 ..... rd:5 &r_csr
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@rr_csr .... .... csr:14 rj:5 rd:5 &rr_csr
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2022-06-06 15:43:17 +03:00
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@empty .... ........ ..... ..... ..... ..... &empty
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@i_rr ...... ...... ..... rk:5 rj:5 imm:5 &i_rr
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2022-06-06 15:43:18 +03:00
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@cop_r_i .... ...... imm:s12 rj:5 cop:5 &cop_r_i
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@j_i .... ........ .. imm:8 rj:5 ..... &j_i
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target/loongarch: Add fixed point arithmetic instruction translation
This includes:
- ADD.{W/D}, SUB.{W/D}
- ADDI.{W/D}, ADDU16ID
- ALSL.{W[U]/D}
- LU12I.W, LU32I.D LU52I.D
- SLT[U], SLT[U]I
- PCADDI, PCADDU12I, PCADDU18I, PCALAU12I
- AND, OR, NOR, XOR, ANDN, ORN
- MUL.{W/D}, MULH.{W[U]/D[U]}
- MULW.D.W[U]
- DIV.{W[U]/D[U]}, MOD.{W[U]/D[U]}
- ANDI, ORI, XORI
Signed-off-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220606124333.2060567-5-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 15:42:54 +03:00
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#
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# Fixed point arithmetic operation instruction
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#
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add_w 0000 00000001 00000 ..... ..... ..... @rrr
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add_d 0000 00000001 00001 ..... ..... ..... @rrr
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sub_w 0000 00000001 00010 ..... ..... ..... @rrr
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sub_d 0000 00000001 00011 ..... ..... ..... @rrr
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slt 0000 00000001 00100 ..... ..... ..... @rrr
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sltu 0000 00000001 00101 ..... ..... ..... @rrr
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slti 0000 001000 ............ ..... ..... @rr_i12
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sltui 0000 001001 ............ ..... ..... @rr_i12
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nor 0000 00000001 01000 ..... ..... ..... @rrr
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and 0000 00000001 01001 ..... ..... ..... @rrr
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or 0000 00000001 01010 ..... ..... ..... @rrr
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xor 0000 00000001 01011 ..... ..... ..... @rrr
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orn 0000 00000001 01100 ..... ..... ..... @rrr
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andn 0000 00000001 01101 ..... ..... ..... @rrr
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mul_w 0000 00000001 11000 ..... ..... ..... @rrr
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mulh_w 0000 00000001 11001 ..... ..... ..... @rrr
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mulh_wu 0000 00000001 11010 ..... ..... ..... @rrr
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mul_d 0000 00000001 11011 ..... ..... ..... @rrr
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mulh_d 0000 00000001 11100 ..... ..... ..... @rrr
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mulh_du 0000 00000001 11101 ..... ..... ..... @rrr
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mulw_d_w 0000 00000001 11110 ..... ..... ..... @rrr
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mulw_d_wu 0000 00000001 11111 ..... ..... ..... @rrr
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div_w 0000 00000010 00000 ..... ..... ..... @rrr
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mod_w 0000 00000010 00001 ..... ..... ..... @rrr
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div_wu 0000 00000010 00010 ..... ..... ..... @rrr
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mod_wu 0000 00000010 00011 ..... ..... ..... @rrr
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div_d 0000 00000010 00100 ..... ..... ..... @rrr
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mod_d 0000 00000010 00101 ..... ..... ..... @rrr
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div_du 0000 00000010 00110 ..... ..... ..... @rrr
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mod_du 0000 00000010 00111 ..... ..... ..... @rrr
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alsl_w 0000 00000000 010 .. ..... ..... ..... @rrr_sa2p1
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alsl_wu 0000 00000000 011 .. ..... ..... ..... @rrr_sa2p1
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alsl_d 0000 00000010 110 .. ..... ..... ..... @rrr_sa2p1
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lu12i_w 0001 010 .................... ..... @r_i20
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lu32i_d 0001 011 .................... ..... @r_i20
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lu52i_d 0000 001100 ............ ..... ..... @rr_i12
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pcaddi 0001 100 .................... ..... @r_i20
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pcalau12i 0001 101 .................... ..... @r_i20
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pcaddu12i 0001 110 .................... ..... @r_i20
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pcaddu18i 0001 111 .................... ..... @r_i20
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addi_w 0000 001010 ............ ..... ..... @rr_i12
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addi_d 0000 001011 ............ ..... ..... @rr_i12
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addu16i_d 0001 00 ................ ..... ..... @rr_i16
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andi 0000 001101 ............ ..... ..... @rr_ui12
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ori 0000 001110 ............ ..... ..... @rr_ui12
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xori 0000 001111 ............ ..... ..... @rr_ui12
|
target/loongarch: Add fixed point shift instruction translation
This includes:
- SLL.W, SRL.W, SRA.W, ROTR.W
- SLLI.W, SRLI.W, SRAI.W, ROTRI.W
- SLL.D, SRL.D, SRA.D, ROTR.D
- SLLI.D, SRLI.D, SRAI.D, ROTRI.D
Signed-off-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220606124333.2060567-6-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 15:42:55 +03:00
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#
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# Fixed point shift operation instruction
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#
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sll_w 0000 00000001 01110 ..... ..... ..... @rrr
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srl_w 0000 00000001 01111 ..... ..... ..... @rrr
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sra_w 0000 00000001 10000 ..... ..... ..... @rrr
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sll_d 0000 00000001 10001 ..... ..... ..... @rrr
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srl_d 0000 00000001 10010 ..... ..... ..... @rrr
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sra_d 0000 00000001 10011 ..... ..... ..... @rrr
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rotr_w 0000 00000001 10110 ..... ..... ..... @rrr
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rotr_d 0000 00000001 10111 ..... ..... ..... @rrr
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slli_w 0000 00000100 00001 ..... ..... ..... @rr_ui5
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slli_d 0000 00000100 0001 ...... ..... ..... @rr_ui6
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srli_w 0000 00000100 01001 ..... ..... ..... @rr_ui5
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srli_d 0000 00000100 0101 ...... ..... ..... @rr_ui6
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srai_w 0000 00000100 10001 ..... ..... ..... @rr_ui5
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srai_d 0000 00000100 1001 ...... ..... ..... @rr_ui6
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rotri_w 0000 00000100 11001 ..... ..... ..... @rr_ui5
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rotri_d 0000 00000100 1101 ...... ..... ..... @rr_ui6
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2022-06-06 15:42:56 +03:00
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#
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# Fixed point bit operation instruction
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#
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ext_w_h 0000 00000000 00000 10110 ..... ..... @rr
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ext_w_b 0000 00000000 00000 10111 ..... ..... @rr
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clo_w 0000 00000000 00000 00100 ..... ..... @rr
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clz_w 0000 00000000 00000 00101 ..... ..... @rr
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cto_w 0000 00000000 00000 00110 ..... ..... @rr
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ctz_w 0000 00000000 00000 00111 ..... ..... @rr
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clo_d 0000 00000000 00000 01000 ..... ..... @rr
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clz_d 0000 00000000 00000 01001 ..... ..... @rr
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cto_d 0000 00000000 00000 01010 ..... ..... @rr
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ctz_d 0000 00000000 00000 01011 ..... ..... @rr
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revb_2h 0000 00000000 00000 01100 ..... ..... @rr
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revb_4h 0000 00000000 00000 01101 ..... ..... @rr
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revb_2w 0000 00000000 00000 01110 ..... ..... @rr
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revb_d 0000 00000000 00000 01111 ..... ..... @rr
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revh_2w 0000 00000000 00000 10000 ..... ..... @rr
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revh_d 0000 00000000 00000 10001 ..... ..... @rr
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bitrev_4b 0000 00000000 00000 10010 ..... ..... @rr
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bitrev_8b 0000 00000000 00000 10011 ..... ..... @rr
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bitrev_w 0000 00000000 00000 10100 ..... ..... @rr
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bitrev_d 0000 00000000 00000 10101 ..... ..... @rr
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bytepick_w 0000 00000000 100 .. ..... ..... ..... @rrr_sa2
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bytepick_d 0000 00000000 11 ... ..... ..... ..... @rrr_sa3
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maskeqz 0000 00000001 00110 ..... ..... ..... @rrr
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masknez 0000 00000001 00111 ..... ..... ..... @rrr
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bstrins_w 0000 0000011 ..... 0 ..... ..... ..... @rr_2bw
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bstrpick_w 0000 0000011 ..... 1 ..... ..... ..... @rr_2bw
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bstrins_d 0000 000010 ...... ...... ..... ..... @rr_2bd
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bstrpick_d 0000 000011 ...... ...... ..... ..... @rr_2bd
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2022-06-06 15:42:57 +03:00
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#
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# Fixed point load/store instruction
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#
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ld_b 0010 100000 ............ ..... ..... @rr_i12
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ld_h 0010 100001 ............ ..... ..... @rr_i12
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ld_w 0010 100010 ............ ..... ..... @rr_i12
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ld_d 0010 100011 ............ ..... ..... @rr_i12
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st_b 0010 100100 ............ ..... ..... @rr_i12
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st_h 0010 100101 ............ ..... ..... @rr_i12
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st_w 0010 100110 ............ ..... ..... @rr_i12
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st_d 0010 100111 ............ ..... ..... @rr_i12
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ld_bu 0010 101000 ............ ..... ..... @rr_i12
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ld_hu 0010 101001 ............ ..... ..... @rr_i12
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ld_wu 0010 101010 ............ ..... ..... @rr_i12
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ldx_b 0011 10000000 00000 ..... ..... ..... @rrr
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ldx_h 0011 10000000 01000 ..... ..... ..... @rrr
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ldx_w 0011 10000000 10000 ..... ..... ..... @rrr
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ldx_d 0011 10000000 11000 ..... ..... ..... @rrr
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stx_b 0011 10000001 00000 ..... ..... ..... @rrr
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stx_h 0011 10000001 01000 ..... ..... ..... @rrr
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stx_w 0011 10000001 10000 ..... ..... ..... @rrr
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stx_d 0011 10000001 11000 ..... ..... ..... @rrr
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ldx_bu 0011 10000010 00000 ..... ..... ..... @rrr
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ldx_hu 0011 10000010 01000 ..... ..... ..... @rrr
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ldx_wu 0011 10000010 10000 ..... ..... ..... @rrr
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preld 0010 101011 ............ ..... ..... @hint_r_i12
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dbar 0011 10000111 00100 ............... @i15
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ibar 0011 10000111 00101 ............... @i15
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ldptr_w 0010 0100 .............. ..... ..... @rr_i14s2
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stptr_w 0010 0101 .............. ..... ..... @rr_i14s2
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ldptr_d 0010 0110 .............. ..... ..... @rr_i14s2
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stptr_d 0010 0111 .............. ..... ..... @rr_i14s2
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ldgt_b 0011 10000111 10000 ..... ..... ..... @rrr
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ldgt_h 0011 10000111 10001 ..... ..... ..... @rrr
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ldgt_w 0011 10000111 10010 ..... ..... ..... @rrr
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ldgt_d 0011 10000111 10011 ..... ..... ..... @rrr
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ldle_b 0011 10000111 10100 ..... ..... ..... @rrr
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ldle_h 0011 10000111 10101 ..... ..... ..... @rrr
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ldle_w 0011 10000111 10110 ..... ..... ..... @rrr
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ldle_d 0011 10000111 10111 ..... ..... ..... @rrr
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stgt_b 0011 10000111 11000 ..... ..... ..... @rrr
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stgt_h 0011 10000111 11001 ..... ..... ..... @rrr
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stgt_w 0011 10000111 11010 ..... ..... ..... @rrr
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stgt_d 0011 10000111 11011 ..... ..... ..... @rrr
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stle_b 0011 10000111 11100 ..... ..... ..... @rrr
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stle_h 0011 10000111 11101 ..... ..... ..... @rrr
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stle_w 0011 10000111 11110 ..... ..... ..... @rrr
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stle_d 0011 10000111 11111 ..... ..... ..... @rrr
|
2022-06-06 15:42:58 +03:00
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|
#
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|
|
# Fixed point atomic instruction
|
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|
#
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ll_w 0010 0000 .............. ..... ..... @rr_i14s2
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sc_w 0010 0001 .............. ..... ..... @rr_i14s2
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ll_d 0010 0010 .............. ..... ..... @rr_i14s2
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sc_d 0010 0011 .............. ..... ..... @rr_i14s2
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amswap_w 0011 10000110 00000 ..... ..... ..... @rrr
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amswap_d 0011 10000110 00001 ..... ..... ..... @rrr
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amadd_w 0011 10000110 00010 ..... ..... ..... @rrr
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amadd_d 0011 10000110 00011 ..... ..... ..... @rrr
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amand_w 0011 10000110 00100 ..... ..... ..... @rrr
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amand_d 0011 10000110 00101 ..... ..... ..... @rrr
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amor_w 0011 10000110 00110 ..... ..... ..... @rrr
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amor_d 0011 10000110 00111 ..... ..... ..... @rrr
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amxor_w 0011 10000110 01000 ..... ..... ..... @rrr
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amxor_d 0011 10000110 01001 ..... ..... ..... @rrr
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ammax_w 0011 10000110 01010 ..... ..... ..... @rrr
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ammax_d 0011 10000110 01011 ..... ..... ..... @rrr
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ammin_w 0011 10000110 01100 ..... ..... ..... @rrr
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ammin_d 0011 10000110 01101 ..... ..... ..... @rrr
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ammax_wu 0011 10000110 01110 ..... ..... ..... @rrr
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ammax_du 0011 10000110 01111 ..... ..... ..... @rrr
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ammin_wu 0011 10000110 10000 ..... ..... ..... @rrr
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ammin_du 0011 10000110 10001 ..... ..... ..... @rrr
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amswap_db_w 0011 10000110 10010 ..... ..... ..... @rrr
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amswap_db_d 0011 10000110 10011 ..... ..... ..... @rrr
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amadd_db_w 0011 10000110 10100 ..... ..... ..... @rrr
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amadd_db_d 0011 10000110 10101 ..... ..... ..... @rrr
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amand_db_w 0011 10000110 10110 ..... ..... ..... @rrr
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amand_db_d 0011 10000110 10111 ..... ..... ..... @rrr
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amor_db_w 0011 10000110 11000 ..... ..... ..... @rrr
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amor_db_d 0011 10000110 11001 ..... ..... ..... @rrr
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amxor_db_w 0011 10000110 11010 ..... ..... ..... @rrr
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amxor_db_d 0011 10000110 11011 ..... ..... ..... @rrr
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ammax_db_w 0011 10000110 11100 ..... ..... ..... @rrr
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ammax_db_d 0011 10000110 11101 ..... ..... ..... @rrr
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ammin_db_w 0011 10000110 11110 ..... ..... ..... @rrr
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ammin_db_d 0011 10000110 11111 ..... ..... ..... @rrr
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ammax_db_wu 0011 10000111 00000 ..... ..... ..... @rrr
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ammax_db_du 0011 10000111 00001 ..... ..... ..... @rrr
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ammin_db_wu 0011 10000111 00010 ..... ..... ..... @rrr
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ammin_db_du 0011 10000111 00011 ..... ..... ..... @rrr
|
2022-06-06 15:42:59 +03:00
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|
#
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|
|
# Fixed point extra instruction
|
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|
|
#
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crc_w_b_w 0000 00000010 01000 ..... ..... ..... @rrr
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crc_w_h_w 0000 00000010 01001 ..... ..... ..... @rrr
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crc_w_w_w 0000 00000010 01010 ..... ..... ..... @rrr
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crc_w_d_w 0000 00000010 01011 ..... ..... ..... @rrr
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crcc_w_b_w 0000 00000010 01100 ..... ..... ..... @rrr
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crcc_w_h_w 0000 00000010 01101 ..... ..... ..... @rrr
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crcc_w_w_w 0000 00000010 01110 ..... ..... ..... @rrr
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crcc_w_d_w 0000 00000010 01111 ..... ..... ..... @rrr
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break 0000 00000010 10100 ............... @i15
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syscall 0000 00000010 10110 ............... @i15
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asrtle_d 0000 00000000 00010 ..... ..... 00000 @rr_jk
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asrtgt_d 0000 00000000 00011 ..... ..... 00000 @rr_jk
|
2022-06-06 15:43:19 +03:00
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rdtimel_w 0000 00000000 00000 11000 ..... ..... @rr
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rdtimeh_w 0000 00000000 00000 11001 ..... ..... @rr
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rdtime_d 0000 00000000 00000 11010 ..... ..... @rr
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2022-06-06 15:42:59 +03:00
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cpucfg 0000 00000000 00000 11011 ..... ..... @rr
|
2022-06-06 15:43:00 +03:00
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|
#
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|
# Floating point arithmetic operation instruction
|
|
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|
#
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fadd_s 0000 00010000 00001 ..... ..... ..... @fff
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fadd_d 0000 00010000 00010 ..... ..... ..... @fff
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fsub_s 0000 00010000 00101 ..... ..... ..... @fff
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fsub_d 0000 00010000 00110 ..... ..... ..... @fff
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fmul_s 0000 00010000 01001 ..... ..... ..... @fff
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fmul_d 0000 00010000 01010 ..... ..... ..... @fff
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fdiv_s 0000 00010000 01101 ..... ..... ..... @fff
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fdiv_d 0000 00010000 01110 ..... ..... ..... @fff
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fmadd_s 0000 10000001 ..... ..... ..... ..... @ffff
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fmadd_d 0000 10000010 ..... ..... ..... ..... @ffff
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fmsub_s 0000 10000101 ..... ..... ..... ..... @ffff
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fmsub_d 0000 10000110 ..... ..... ..... ..... @ffff
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fnmadd_s 0000 10001001 ..... ..... ..... ..... @ffff
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fnmadd_d 0000 10001010 ..... ..... ..... ..... @ffff
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fnmsub_s 0000 10001101 ..... ..... ..... ..... @ffff
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fnmsub_d 0000 10001110 ..... ..... ..... ..... @ffff
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|
fmax_s 0000 00010000 10001 ..... ..... ..... @fff
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fmax_d 0000 00010000 10010 ..... ..... ..... @fff
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fmin_s 0000 00010000 10101 ..... ..... ..... @fff
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fmin_d 0000 00010000 10110 ..... ..... ..... @fff
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fmaxa_s 0000 00010000 11001 ..... ..... ..... @fff
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fmaxa_d 0000 00010000 11010 ..... ..... ..... @fff
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fmina_s 0000 00010000 11101 ..... ..... ..... @fff
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fmina_d 0000 00010000 11110 ..... ..... ..... @fff
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fabs_s 0000 00010001 01000 00001 ..... ..... @ff
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fabs_d 0000 00010001 01000 00010 ..... ..... @ff
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fneg_s 0000 00010001 01000 00101 ..... ..... @ff
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fneg_d 0000 00010001 01000 00110 ..... ..... @ff
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fsqrt_s 0000 00010001 01000 10001 ..... ..... @ff
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fsqrt_d 0000 00010001 01000 10010 ..... ..... @ff
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frecip_s 0000 00010001 01000 10101 ..... ..... @ff
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frecip_d 0000 00010001 01000 10110 ..... ..... @ff
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frsqrt_s 0000 00010001 01000 11001 ..... ..... @ff
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frsqrt_d 0000 00010001 01000 11010 ..... ..... @ff
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fscaleb_s 0000 00010001 00001 ..... ..... ..... @fff
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fscaleb_d 0000 00010001 00010 ..... ..... ..... @fff
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flogb_s 0000 00010001 01000 01001 ..... ..... @ff
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flogb_d 0000 00010001 01000 01010 ..... ..... @ff
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fcopysign_s 0000 00010001 00101 ..... ..... ..... @fff
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fcopysign_d 0000 00010001 00110 ..... ..... ..... @fff
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fclass_s 0000 00010001 01000 01101 ..... ..... @ff
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fclass_d 0000 00010001 01000 01110 ..... ..... @ff
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2022-06-06 15:43:01 +03:00
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#
|
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|
|
# Floating point compare instruction
|
|
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|
#
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fcmp_cond_s 0000 11000001 ..... ..... ..... 00 ... @cff_fcond
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fcmp_cond_d 0000 11000010 ..... ..... ..... 00 ... @cff_fcond
|
2022-06-06 15:43:02 +03:00
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#
|
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|
|
# Floating point conversion instruction
|
|
|
|
|
#
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|
|
fcvt_s_d 0000 00010001 10010 00110 ..... ..... @ff
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fcvt_d_s 0000 00010001 10010 01001 ..... ..... @ff
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ftintrm_w_s 0000 00010001 10100 00001 ..... ..... @ff
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ftintrm_w_d 0000 00010001 10100 00010 ..... ..... @ff
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ftintrm_l_s 0000 00010001 10100 01001 ..... ..... @ff
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ftintrm_l_d 0000 00010001 10100 01010 ..... ..... @ff
|
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ftintrp_w_s 0000 00010001 10100 10001 ..... ..... @ff
|
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ftintrp_w_d 0000 00010001 10100 10010 ..... ..... @ff
|
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ftintrp_l_s 0000 00010001 10100 11001 ..... ..... @ff
|
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|
ftintrp_l_d 0000 00010001 10100 11010 ..... ..... @ff
|
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|
ftintrz_w_s 0000 00010001 10101 00001 ..... ..... @ff
|
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|
ftintrz_w_d 0000 00010001 10101 00010 ..... ..... @ff
|
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|
|
ftintrz_l_s 0000 00010001 10101 01001 ..... ..... @ff
|
|
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|
|
ftintrz_l_d 0000 00010001 10101 01010 ..... ..... @ff
|
|
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|
|
ftintrne_w_s 0000 00010001 10101 10001 ..... ..... @ff
|
|
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|
|
ftintrne_w_d 0000 00010001 10101 10010 ..... ..... @ff
|
|
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|
|
ftintrne_l_s 0000 00010001 10101 11001 ..... ..... @ff
|
|
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|
|
ftintrne_l_d 0000 00010001 10101 11010 ..... ..... @ff
|
|
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|
|
ftint_w_s 0000 00010001 10110 00001 ..... ..... @ff
|
|
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|
|
ftint_w_d 0000 00010001 10110 00010 ..... ..... @ff
|
|
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|
|
ftint_l_s 0000 00010001 10110 01001 ..... ..... @ff
|
|
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|
|
ftint_l_d 0000 00010001 10110 01010 ..... ..... @ff
|
|
|
|
|
ffint_s_w 0000 00010001 11010 00100 ..... ..... @ff
|
|
|
|
|
ffint_s_l 0000 00010001 11010 00110 ..... ..... @ff
|
|
|
|
|
ffint_d_w 0000 00010001 11010 01000 ..... ..... @ff
|
|
|
|
|
ffint_d_l 0000 00010001 11010 01010 ..... ..... @ff
|
|
|
|
|
frint_s 0000 00010001 11100 10001 ..... ..... @ff
|
|
|
|
|
frint_d 0000 00010001 11100 10010 ..... ..... @ff
|
2022-06-06 15:43:03 +03:00
|
|
|
|
|
|
|
|
#
|
|
|
|
|
# Floating point move instruction
|
|
|
|
|
#
|
|
|
|
|
fmov_s 0000 00010001 01001 00101 ..... ..... @ff
|
|
|
|
|
fmov_d 0000 00010001 01001 00110 ..... ..... @ff
|
|
|
|
|
fsel 0000 11010000 00 ... ..... ..... ..... @fffc
|
|
|
|
|
movgr2fr_w 0000 00010001 01001 01001 ..... ..... @fr
|
|
|
|
|
movgr2fr_d 0000 00010001 01001 01010 ..... ..... @fr
|
|
|
|
|
movgr2frh_w 0000 00010001 01001 01011 ..... ..... @fr
|
|
|
|
|
movfr2gr_s 0000 00010001 01001 01101 ..... ..... @rf
|
|
|
|
|
movfr2gr_d 0000 00010001 01001 01110 ..... ..... @rf
|
|
|
|
|
movfrh2gr_s 0000 00010001 01001 01111 ..... ..... @rf
|
|
|
|
|
movgr2fcsr 0000 00010001 01001 10000 ..... ..... @fcsrd_r
|
|
|
|
|
movfcsr2gr 0000 00010001 01001 10010 ..... ..... @r_fcsrs
|
|
|
|
|
movfr2cf 0000 00010001 01001 10100 ..... 00 ... @cf
|
|
|
|
|
movcf2fr 0000 00010001 01001 10101 00 ... ..... @fc
|
|
|
|
|
movgr2cf 0000 00010001 01001 10110 ..... 00 ... @cr
|
|
|
|
|
movcf2gr 0000 00010001 01001 10111 00 ... ..... @rc
|
2022-06-06 15:43:04 +03:00
|
|
|
|
|
|
|
|
#
|
|
|
|
|
# Floating point load/store instruction
|
|
|
|
|
#
|
|
|
|
|
fld_s 0010 101100 ............ ..... ..... @fr_i12
|
|
|
|
|
fst_s 0010 101101 ............ ..... ..... @fr_i12
|
|
|
|
|
fld_d 0010 101110 ............ ..... ..... @fr_i12
|
|
|
|
|
fst_d 0010 101111 ............ ..... ..... @fr_i12
|
|
|
|
|
fldx_s 0011 10000011 00000 ..... ..... ..... @frr
|
|
|
|
|
fldx_d 0011 10000011 01000 ..... ..... ..... @frr
|
|
|
|
|
fstx_s 0011 10000011 10000 ..... ..... ..... @frr
|
|
|
|
|
fstx_d 0011 10000011 11000 ..... ..... ..... @frr
|
|
|
|
|
fldgt_s 0011 10000111 01000 ..... ..... ..... @frr
|
|
|
|
|
fldgt_d 0011 10000111 01001 ..... ..... ..... @frr
|
|
|
|
|
fldle_s 0011 10000111 01010 ..... ..... ..... @frr
|
|
|
|
|
fldle_d 0011 10000111 01011 ..... ..... ..... @frr
|
|
|
|
|
fstgt_s 0011 10000111 01100 ..... ..... ..... @frr
|
|
|
|
|
fstgt_d 0011 10000111 01101 ..... ..... ..... @frr
|
|
|
|
|
fstle_s 0011 10000111 01110 ..... ..... ..... @frr
|
|
|
|
|
fstle_d 0011 10000111 01111 ..... ..... ..... @frr
|
2022-06-06 15:43:05 +03:00
|
|
|
|
|
|
|
|
#
|
|
|
|
|
# Branch instructions
|
|
|
|
|
#
|
|
|
|
|
beqz 0100 00 ................ ..... ..... @r_offs21
|
|
|
|
|
bnez 0100 01 ................ ..... ..... @r_offs21
|
|
|
|
|
bceqz 0100 10 ................ 00 ... ..... @c_offs21
|
|
|
|
|
bcnez 0100 10 ................ 01 ... ..... @c_offs21
|
|
|
|
|
jirl 0100 11 ................ ..... ..... @rr_offs16
|
|
|
|
|
b 0101 00 .......................... @offs26
|
|
|
|
|
bl 0101 01 .......................... @offs26
|
|
|
|
|
beq 0101 10 ................ ..... ..... @rr_offs16
|
|
|
|
|
bne 0101 11 ................ ..... ..... @rr_offs16
|
|
|
|
|
blt 0110 00 ................ ..... ..... @rr_offs16
|
|
|
|
|
bge 0110 01 ................ ..... ..... @rr_offs16
|
|
|
|
|
bltu 0110 10 ................ ..... ..... @rr_offs16
|
|
|
|
|
bgeu 0110 11 ................ ..... ..... @rr_offs16
|
2022-06-06 15:43:15 +03:00
|
|
|
|
|
|
|
|
#
|
|
|
|
|
# Core instructions
|
|
|
|
|
#
|
|
|
|
|
{
|
|
|
|
|
csrrd 0000 0100 .............. 00000 ..... @r_csr
|
|
|
|
|
csrwr 0000 0100 .............. 00001 ..... @r_csr
|
|
|
|
|
csrxchg 0000 0100 .............. ..... ..... @rr_csr
|
|
|
|
|
}
|
2022-06-06 15:43:16 +03:00
|
|
|
|
|
|
|
|
iocsrrd_b 0000 01100100 10000 00000 ..... ..... @rr
|
|
|
|
|
iocsrrd_h 0000 01100100 10000 00001 ..... ..... @rr
|
|
|
|
|
iocsrrd_w 0000 01100100 10000 00010 ..... ..... @rr
|
|
|
|
|
iocsrrd_d 0000 01100100 10000 00011 ..... ..... @rr
|
|
|
|
|
iocsrwr_b 0000 01100100 10000 00100 ..... ..... @rr
|
|
|
|
|
iocsrwr_h 0000 01100100 10000 00101 ..... ..... @rr
|
|
|
|
|
iocsrwr_w 0000 01100100 10000 00110 ..... ..... @rr
|
|
|
|
|
iocsrwr_d 0000 01100100 10000 00111 ..... ..... @rr
|
2022-06-06 15:43:17 +03:00
|
|
|
tlbsrch 0000 01100100 10000 01010 00000 00000 @empty
|
|
|
|
|
tlbrd 0000 01100100 10000 01011 00000 00000 @empty
|
|
|
|
|
tlbwr 0000 01100100 10000 01100 00000 00000 @empty
|
|
|
|
|
tlbfill 0000 01100100 10000 01101 00000 00000 @empty
|
|
|
|
|
tlbclr 0000 01100100 10000 01000 00000 00000 @empty
|
|
|
|
|
tlbflush 0000 01100100 10000 01001 00000 00000 @empty
|
|
|
|
|
invtlb 0000 01100100 10011 ..... ..... ..... @i_rr
|
2022-06-06 15:43:18 +03:00
|
|
|
cacop 0000 011000 ............ ..... ..... @cop_r_i
|
|
|
|
|
lddir 0000 01100100 00 ........ ..... ..... @rr_ui8
|
|
|
|
|
ldpte 0000 01100100 01 ........ ..... 00000 @j_i
|
|
|
|
|
ertn 0000 01100100 10000 01110 00000 00000 @empty
|
|
|
|
|
idle 0000 01100100 10001 ............... @i15
|
|
|
|
|
dbcl 0000 00000010 10101 ............... @i15
|
