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qemu/tcg/s390x/tcg-target-con-str.h

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tcg/s390: Split out target constraints to tcg-target-con-str.h Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2020-10-17 06:09:02 +03:00
/* SPDX-License-Identifier: MIT */
/*
* Define S390 target-specific operand constraints.
* Copyright (c) 2021 Linaro
*/
/*
* Define constraint letters for register sets:
* REGS(letter, register_mask)
*/
REGS('r', ALL_GENERAL_REGS)
tcg/s390x: Add host vector framework Add registers and function stubs. The functionality is disabled via squashing s390_facilities[2] to 0. We must still include results for the mandatory opcodes in tcg_target_op_def, as all opcodes are checked during tcg init. Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2020-09-15 02:33:14 +03:00
REGS('v', ALL_VECTOR_REGS)
tcg/s390x: Use register pair allocation for div and mulu2 Previously we hard-coded R2 and R3. Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-10-10 18:41:15 +03:00
REGS('o', 0xaaaa) /* odd numbered general regs */
tcg/s390: Split out target constraints to tcg-target-con-str.h Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2020-10-17 06:09:02 +03:00
/*
* Define constraint letters for constants:
* CONST(letter, TCG_CT_CONST_* bit set)
*/
tcg/s390x: Add TCG_CT_CONST_CMP Better constraint for tcg_out_cmp, based on the comparison. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-28 08:34:24 +03:00
CONST('C', TCG_CT_CONST_CMP)
tcg/s390: Split out target constraints to tcg-target-con-str.h Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2020-10-17 06:09:02 +03:00
CONST('I', TCG_CT_CONST_S16)
CONST('J', TCG_CT_CONST_S32)
tcg/s390x: Tighten constraints for or_i64 and xor_i64 Drop support for sequential OR and XOR, as the serial dependency is slower than loading the constant first. Let the register allocator handle such immediates by matching only what one insn can achieve. Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-12-08 20:28:19 +03:00
CONST('K', TCG_CT_CONST_P32)
tcg/s390x: Optimize cmpsel with constant 0/-1 arguments These can be simplified to and/or/andc/orc, avoiding the load of the constantinto a register. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-09-11 06:24:10 +03:00
CONST('M', TCG_CT_CONST_M1)
tcg/s390x: Tighten constraints for and_i64 Let the register allocator handle such immediates by matching only what one insn can achieve. Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-12-08 21:06:03 +03:00
CONST('N', TCG_CT_CONST_INV)
CONST('R', TCG_CT_CONST_INVRISBG)
tcg/s390x: Split constraint A into J+U Signed 33-bit == signed 32-bit + unsigned 32-bit. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-28 07:57:06 +03:00
CONST('U', TCG_CT_CONST_U32)
tcg/s390: Split out target constraints to tcg-target-con-str.h Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2020-10-17 06:09:02 +03:00
CONST('Z', TCG_CT_CONST_ZERO)
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