mirror of
https://github.com/memtest86plus/memtest86plus
synced 2025-03-13 17:33:14 +03:00
f34a85ce07
* Add CPUID detection for MTL & ARL CPUs * Add support for ARL SMBus Controler Add PCI Device polling on Bus 0x80 (instead of fixed 0x00) Solve issue with DDR5 SPD Bank switching when SPD Write is disabled (using Proc Call) * Add Live Freq/Timings IMC Polling for Intel MTL & ADL CPUs * Correct K8 Rev G detection Fix #361 (PR hijacking)
114 lines
3.2 KiB
C
114 lines
3.2 KiB
C
// SPDX-License-Identifier: GPL-2.0
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// Copyright (C) 2004-2024 Sam Demeulemeester
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//
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// ------------------------
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//
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// Platform-specific code for Intel Meteor Lake (MTL) and
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// Arrow-Lake (ARL) CPUs
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//
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#include "cpuinfo.h"
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#include "memctrl.h"
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#include "msr.h"
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#include "pci.h"
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#include "vmem.h"
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#include "imc.h"
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#define MTL_MMR_BASE_REG_LOW 0x48
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#define MTL_MMR_BASE_REG_HIGH 0x4C
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#define MTL_MMR_WINDOW_RANGE (1UL << 17)
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#define MTL_MMR_BASE_MASK 0x3FFFFFE0000
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#define MTL_MMR_MC1_OFFSET 0x10000
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#define MTL_MMR_CH1_OFFSET 0x800
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#define MTL_MMR_IC_DECODE 0xD800
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#define MTL_MMR_CH0_DIMM_REG 0xD80C
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#define MTL_MMR_CH0_PRE_REG 0xE000
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#define MTL_MMR_CH0_CAS_REG 0xE070
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#define MTL_MMR_CH0_ACT_REG 0xE138
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#define MTL_MMR_PTGRAM_REG 0x13D98
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void get_imc_config_intel_mtl(void)
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{
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uint64_t mmio_reg;
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uint32_t cha, chb, offset;
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uint32_t tmp;
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uintptr_t *ptr;
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uint32_t *ptr32;
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// Get Memory Mapped Register Base Address (Enable MMIO if needed)
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mmio_reg = pci_config_read32(0, 0, 0, MTL_MMR_BASE_REG_LOW);
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if (!(mmio_reg & 0x1)) {
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pci_config_write32( 0, 0, 0, MTL_MMR_BASE_REG_LOW, mmio_reg | 1);
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mmio_reg = pci_config_read32(0, 0, 0, MTL_MMR_BASE_REG_LOW);
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if (!(mmio_reg & 0x1)) return;
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}
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mmio_reg |= (uint64_t)pci_config_read32(0, 0, 0, MTL_MMR_BASE_REG_HIGH) << 32;
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mmio_reg &= MTL_MMR_BASE_MASK;
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#ifndef __x86_64__
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if (mmio_reg >= (1ULL << 32)) return; // MMIO is outside reachable range (> 32bit)
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#endif
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uintptr_t mchbar_addr = map_region(mmio_reg, MTL_MMR_WINDOW_RANGE, false);
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// Get channel configuration & IMC width
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cha = *(uintptr_t*)(mchbar_addr + MTL_MMR_CH0_DIMM_REG);
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tmp = *(uintptr_t*)(mchbar_addr + MTL_MMR_IC_DECODE);
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cha = ~cha ? 1 << (((tmp >> 27) & 3) + 4) : 0;
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chb = *(uintptr_t*)(mchbar_addr + MTL_MMR_CH0_DIMM_REG + MTL_MMR_MC1_OFFSET);
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tmp = *(uintptr_t*)(mchbar_addr + MTL_MMR_IC_DECODE + MTL_MMR_MC1_OFFSET);
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chb = ~chb ? 1 << (((tmp >> 27) & 3) + 4) : 0;
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offset = cha ? 0x0 : MTL_MMR_MC1_OFFSET;
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imc.width = (cha + chb) * 2;
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// MTL+ only supports DDR5
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imc.type = "DDR5";
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// Get Memory Clock
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ptr32 = (uint32_t*)(mchbar_addr + MTL_MMR_PTGRAM_REG);
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switch((*ptr32 >> 20) & 0xF) {
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default:
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case 0x1:
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imc.freq = 200;
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break;
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case 0x2:
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imc.freq = 100;
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break;
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case 0xA:
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imc.freq = 133;
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break;
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case 0xB:
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imc.freq = 66;
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break;
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case 0xC:
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imc.freq = 33;
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break;
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}
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imc.freq *= (*ptr32 >> 12) & 0xFF; // * Divider
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imc.freq *= (((*ptr32 >> 24) & 1) + 1) * 2; // * Gear * DDR
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// Get DRAM Timings
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ptr = (uintptr_t*)(mchbar_addr + offset + MTL_MMR_CH0_CAS_REG);
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imc.tCL = (*ptr >> 16) & 0x7F;
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ptr = (uintptr_t*)(mchbar_addr + offset + MTL_MMR_CH0_ACT_REG);
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imc.tRCD = (*ptr >> 22) & 0xFF;
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ptr = (uintptr_t*)(mchbar_addr + offset + MTL_MMR_CH0_PRE_REG);
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imc.tRP = (*ptr >> 10) & 0xFF;
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ptr32 = (uint32_t*)((uintptr_t)mchbar_addr + offset + MTL_MMR_CH0_PRE_REG + 4);
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imc.tRAS = (*ptr32 >> 13) & 0x1FF;
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}
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