Sam Demeulemeester f34a85ce07
Add support for Intel MTL & ARL CPUs (#441)
* Add CPUID detection for MTL & ARL CPUs

* Add support for ARL SMBus Controler
Add PCI Device polling on Bus 0x80 (instead of fixed 0x00)
Solve issue with DDR5 SPD Bank switching when SPD Write is disabled (using Proc Call)

* Add Live Freq/Timings IMC Polling for Intel MTL & ADL CPUs

* Correct K8 Rev G detection
Fix #361 (PR hijacking)
2024-09-30 13:38:13 +02:00
..
2024-08-30 13:38:46 +02:00