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stivale: Zero out unused GPRs and add a signature

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mintsuki 2020-07-09 03:24:54 +02:00
parent 1bbe7f9385
commit e45f8ac41a
3 changed files with 54 additions and 5 deletions
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8
STIVALE.md
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@ -73,6 +73,10 @@ PIC/APIC IRQs are all masked.
`rdi` will point to the stivale structure (described below). `rdi` will point to the stivale structure (described below).
`rax` contains the stivale signature `0x73746976616c6521` (`stivale!` in ASCII).
All other general purpose registers are set to 0.
### 32-bit kernel ### 32-bit kernel
`eip` will be the entry point as defined in the ELF file, unless the `entry_point` `eip` will be the entry point as defined in the ELF file, unless the `entry_point`
@ -97,9 +101,13 @@ PIC/APIC IRQs are all masked.
`esp` is set to the requested stack as per stivale header. `esp` is set to the requested stack as per stivale header.
`edx:eax` contain the stivale signature `0x73746976:0x616c6521` (`stivale!` in ASCII).
A pointer to the stivale structure (described below) is pushed onto this stack A pointer to the stivale structure (described below) is pushed onto this stack
before the entry point is called. before the entry point is called.
All other general purpose registers are set to 0.
## stivale header (.stivalehdr) ## stivale header (.stivalehdr)
The kernel executable shall have a section `.stivalehdr` which will contain The kernel executable shall have a section `.stivalehdr` which will contain

BIN
qloader2.bin
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51
src/protos/stivale.c
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@ -346,22 +346,63 @@ void stivale_load(char *cmdline, int boot_drive) {
"mov fs, ax\n\t" "mov fs, ax\n\t"
"mov gs, ax\n\t" "mov gs, ax\n\t"
"mov ss, ax\n\t" "mov ss, ax\n\t"
"mov rsp, [rsi]\n\t"
"call [rbx]\n\t" "push 0x30\n\t"
"push [rsi]\n\t"
"pushfq\n\t"
"push 0x28\n\t"
"push [rbx]\n\t"
"mov rax, 0x73746976616c6521\n\t"
"xor rbx, rbx\n\t"
"xor rcx, rcx\n\t"
"xor rdx, rdx\n\t"
"xor rsi, rsi\n\t"
"xor rbp, rbp\n\t"
"xor r8, r8\n\t"
"xor r9, r9\n\t"
"xor r10, r10\n\t"
"xor r11, r11\n\t"
"xor r12, r12\n\t"
"xor r13, r13\n\t"
"xor r14, r14\n\t"
"xor r15, r15\n\t"
"iretq\n\t"
".code32\n\t" ".code32\n\t"
: :
: "a" (pagemap_ptr), "b" (&entry_point), : "a" (pagemap_ptr), "b" (&entry_point),
"D" (&stivale_struct), "S" (&stivale_hdr.stack) "D" (&stivale_struct), "S" (&stivale_hdr.stack)
: "memory"
); );
} else if (bits == 32) { } else if (bits == 32) {
asm volatile ( asm volatile (
"cli\n\t" "cli\n\t"
"cld\n\t" "cld\n\t"
"mov esp, [esi]\n\t"
"push edi\n\t" "sub esp, 4\n\t"
"call [ebx]\n\t" "mov [esp], edi\n\t"
"push 0x20\n\t"
"push [esi]\n\t"
"pushfd\n\t"
"push 0x18\n\t"
"push [ebx]\n\t"
"mov edx, 0x73746976\n\t"
"mov eax, 0x616c6521\n\t"
"xor ebx, ebx\n\t"
"xor ecx, ecx\n\t"
"xor esi, esi\n\t"
"xor edi, edi\n\t"
"xor ebp, ebp\n\t"
"iret\n\t"
: :
: "b" (&entry_point), "D" (&stivale_struct), "S" (&stivale_hdr.stack) : "b" (&entry_point), "D" (&stivale_struct), "S" (&stivale_hdr.stack)
: "memory"
); );
} }
} }