diff --git a/STIVALE.md b/STIVALE.md
index 0463ced3..9dce822a 100644
--- a/STIVALE.md
+++ b/STIVALE.md
@@ -73,6 +73,10 @@ PIC/APIC IRQs are all masked.
 
 `rdi` will point to the stivale structure (described below).
 
+`rax` contains the stivale signature `0x73746976616c6521` (`stivale!` in ASCII).
+
+All other general purpose registers are set to 0.
+
 ### 32-bit kernel
 
 `eip` will be the entry point as defined in the ELF file, unless the `entry_point`
@@ -97,9 +101,13 @@ PIC/APIC IRQs are all masked.
 
 `esp` is set to the requested stack as per stivale header.
 
+`edx:eax` contain the stivale signature `0x73746976:0x616c6521` (`stivale!` in ASCII).
+
 A pointer to the stivale structure (described below) is pushed onto this stack
 before the entry point is called.
 
+All other general purpose registers are set to 0.
+
 ## stivale header (.stivalehdr)
 
 The kernel executable shall have a section `.stivalehdr` which will contain
diff --git a/qloader2.bin b/qloader2.bin
index 0c5efa16..4e3a00fb 100644
Binary files a/qloader2.bin and b/qloader2.bin differ
diff --git a/src/protos/stivale.c b/src/protos/stivale.c
index 401f3e1b..d943170d 100644
--- a/src/protos/stivale.c
+++ b/src/protos/stivale.c
@@ -346,22 +346,63 @@ void stivale_load(char *cmdline, int boot_drive) {
             "mov fs, ax\n\t"
             "mov gs, ax\n\t"
             "mov ss, ax\n\t"
-            "mov rsp, [rsi]\n\t"
-            "call [rbx]\n\t"
+
+            "push 0x30\n\t"
+            "push [rsi]\n\t"
+            "pushfq\n\t"
+            "push 0x28\n\t"
+            "push [rbx]\n\t"
+
+            "mov rax, 0x73746976616c6521\n\t"
+
+            "xor rbx, rbx\n\t"
+            "xor rcx, rcx\n\t"
+            "xor rdx, rdx\n\t"
+            "xor rsi, rsi\n\t"
+            "xor rbp, rbp\n\t"
+            "xor r8,  r8\n\t"
+            "xor r9,  r9\n\t"
+            "xor r10, r10\n\t"
+            "xor r11, r11\n\t"
+            "xor r12, r12\n\t"
+            "xor r13, r13\n\t"
+            "xor r14, r14\n\t"
+            "xor r15, r15\n\t"
+
+            "iretq\n\t"
             ".code32\n\t"
             :
             : "a" (pagemap_ptr), "b" (&entry_point),
               "D" (&stivale_struct), "S" (&stivale_hdr.stack)
+            : "memory"
         );
     } else if (bits == 32) {
         asm volatile (
             "cli\n\t"
             "cld\n\t"
-            "mov esp, [esi]\n\t"
-            "push edi\n\t"
-            "call [ebx]\n\t"
+
+            "sub esp, 4\n\t"
+            "mov [esp], edi\n\t"
+
+            "push 0x20\n\t"
+            "push [esi]\n\t"
+            "pushfd\n\t"
+            "push 0x18\n\t"
+            "push [ebx]\n\t"
+
+            "mov edx, 0x73746976\n\t"
+            "mov eax, 0x616c6521\n\t"
+
+            "xor ebx, ebx\n\t"
+            "xor ecx, ecx\n\t"
+            "xor esi, esi\n\t"
+            "xor edi, edi\n\t"
+            "xor ebp, ebp\n\t"
+
+            "iret\n\t"
             :
             : "b" (&entry_point), "D" (&stivale_struct), "S" (&stivale_hdr.stack)
+            : "memory"
         );
     }
 }