Fixes a problem where a WalkNamespace user function could have a
namespace node deleted out from under it due to the execution of
an AML Unload operator. A new mutex has been defined to exclude
these two activities. ACPICA BZ 749.
Removed locking for reads from the ACPI bit registers in PM1 Status,
Enable, Control, and PM2 Control. The lock is not required when
reading the single-bit registers. The AcpiGetRegisterUnlocked function
is no longer needed and has been removed. This will improve performance
for reads on these registers.
ACPICA BZ 760.
Remove all instances of this obsolete macro, since it is now a simple
reference to ->common.type. There were about 150 invocations of the
macro across 41 files.
Added AcpiHwWritePm1Control. This function writes both of the PM1
control registers (A/B). These registers are
different than than the PM1 A/B status and enable registers
in that different values can be written to the A/B registers.
Most notably, the SLP_TYP bits can be different, as per the
values returned from the _Sx predefined methods.
Now return AE_BAD_PARAMETER if the input register pointer is null,
and AE_BAD_ADDRESS if the register has an address of zero.
Previously, these cases simply returned AE_OK. For optional registers
such as PM1B status/enable/control, the caller should check for a valid
register address before calling.
ACPICA BZ 748.
The PM1B registers are mirrors of the PM1A registers with different
bits actually implemented. From the ACPI specification:
"Although the bits can be split between the two register blocks (each
register block has a unique pointer within the FADT), the bit positions
are maintained. The register block with unimplemented bits (that is, those
implemented in the other register block) always returns zeros, and
writes have no side effects"
This function was writing an optional PM1B status register twice.
The existing call to the low-level AcpiHwRegisterWrite automatically
handles a possibly split PM1 A/B register.
ACPICA BZ 751.
On read, shift B register bits above the A bits. On write, shift B bits
down to zero before writing the B register. New: AcpiHwReadMultiple,
AcpiHwWriteMultiple. These two functions now transparently handle the
(possible) split registers for PM1 Status, Enable, and Control.
Add new globals for the PM1 status registers (A/B), similar to the
way the PM1 enable registers are handled. Instead of overloading the
FADT Event Register blocks. This makes the code clearer and less prone
to error.
Use absolute paths to all project directories. Previously, used paths
relative to the project root, but there is a bug in VC++ that then
creates project directories all over the disk.
Add 2009 copyright to all module headers and signons, including the Linux
header. This affects virtually every file in the ACPICA core subsystem,
iASL compiler, and all utilities.
1) Decode all Boot Architecture flags.
2) Decode all flags, regardless of the FADT version. Previously,
only those flags that were actually valid for the FADT version
were displayed. This seemed to omit some information.
Previously, the table override mechanism was implemented for the
DSDT only. Now, any table in the RSDT/XSDT can be replaced by the
host OS. (including the DSDT).
This returns the FADT support to the original behavior, which is to
use default register widths. However, now check each register
definition and report a warning if it differs from the default.
This is a first step to moving away from the default widths, rather
than outright believing the widths in all FADTs for all machines,
considered rather dangerous until more data is obtained.
1) Update the register lengths for the PM1 event blocks. The length
must be divided by two in order to use these to access the status
registers.
2) Add run-time option to use default register lengths to override a
faulty FADT.
3) Add warning message if any of the X64 address structures contain a
length that does not match the legacy length earlier in the FADT.
4) Move all FADT warning messages into the ValidateFadt function.
