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https://github.com/acpica/acpica/
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Resynching any changes
date 2000.11.02.18.46.00; author cgreen; state Exp;
This commit is contained in:
aystarik
parent
2aea93f8f4
commit
f22a8c4f9f
@ -1,7 +1,7 @@
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/******************************************************************************
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*
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* Name: actbl.h - Table data structures defined in ACPI specification
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* $Revision: 1.40 $
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* $Revision: 1.41 $
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*
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*****************************************************************************/
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@ -293,13 +293,8 @@ typedef struct _AcpiTableSupport
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* Get the architecture-specific tables
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*/
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#include "actbl2.h" /* Acpi 2.0 tables */
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#ifdef IA64
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#include "actbl71.h"
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#else
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#include "actbl1.h" /* Acpi 1.0 tables */
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#endif
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#include "actbl1.h" /* Acpi 1.0 table defintions */
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#include "actbl71.h" /* Acpi 0.71 IA-64 Extension table defintions */
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#include "actbl2.h" /* Acpi 2.0 table definitions */
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#endif /* __ACTBL_H__ */
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@ -1,7 +1,7 @@
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/******************************************************************************
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*
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* Name: actbl64.h - ACPI tables specific to IA64
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*
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* Name: actbl2.h - ACPI Specification Revision 2.0 Tables
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* $Revision: 1.18 $
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*
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*****************************************************************************/
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@ -38,9 +38,9 @@
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* The above copyright and patent license is granted only if the following
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* conditions are met:
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*
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* 3. Conditions
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* 3. Conditions
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*
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* 3.1. Redistribution of Source with Rights to Further Distribute Source.
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* 3.1. Redistribution of Source with Rights to Further Distribute Source.
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* Redistribution of source code of any substantial portion of the Covered
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* Code or modification with rights to further distribute source must include
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* the above Copyright Notice, the above License, this list of Conditions,
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@ -48,11 +48,11 @@
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* Licensee must cause all Covered Code to which Licensee contributes to
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* contain a file documenting the changes Licensee made to create that Covered
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* Code and the date of any change. Licensee must include in that file the
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* documentation of any changes made by any predecessor Licensee. Licensee
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* documentation of any changes made by any predecessor Licensee. Licensee
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* must include a prominent statement that the modification is derived,
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* directly or indirectly, from Original Intel Code.
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*
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* 3.2. Redistribution of Source with no Rights to Further Distribute Source.
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* 3.2. Redistribution of Source with no Rights to Further Distribute Source.
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* Redistribution of source code of any substantial portion of the Covered
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* Code or modification without rights to further distribute source must
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* include the following Disclaimer and Export Compliance provision in the
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@ -86,7 +86,7 @@
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* INSTALLATION, TRAINING OR OTHER SERVICES. INTEL WILL NOT PROVIDE ANY
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* UPDATES, ENHANCEMENTS OR EXTENSIONS. INTEL SPECIFICALLY DISCLAIMS ANY
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* IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT AND FITNESS FOR A
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* PARTICULAR PURPOSE.
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* PARTICULAR PURPOSE.
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*
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* 4.2. IN NO EVENT SHALL INTEL HAVE ANY LIABILITY TO LICENSEE, ITS LICENSEES
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* OR ANY OTHER THIRD PARTY, FOR ANY LOST PROFITS, LOST DATA, LOSS OF USE OR
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@ -114,94 +114,167 @@
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*
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*****************************************************************************/
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#ifndef __ACTBL64_H__
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#define __ACTBL64_H__
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#ifndef __ACTBL2_H__
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#define __ACTBL2_H__
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/**************************************/
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/* Prefered Power Management Profiles */
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/**************************************/
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#define PM_UNSPECIFIED 0
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#define PM_DESKTOP 1
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#define PM_MOBILE 2
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#define PM_WORKSTATION 3
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#define PM_ENTERPRISE_SERVER 4
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#define PM_SOHO_SERVER 5
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#define PM_APPLIANCE_PC 6
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/*********************************************/
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/* ACPI Boot Arch Flags, See spec Table 5-10 */
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/*********************************************/
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#define BAF_LEGACY_DEVICES 0x0001
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#define BAF_8042_KEYBOARD_CONTROLLER 0x0002
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#define FADT2_REVISION_ID 3
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#pragma pack(1)
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/*************************************/
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/* ACPI Specification Rev 2.0 for */
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/* the Root System Description Table */
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/*************************************/
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typedef struct
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{
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ACPI_TABLE_HEADER header; /* Table header */
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UINT32 TableOffsetEntry [1]; /* Array of pointers to */
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/* other tables' headers */
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} RSDT_DESCRIPTOR_REV2;
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typedef UINT64 IO_ADDRESS; /* Only for clarity in declarations */
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/********************************************/
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/* ACPI Specification Rev 2.0 for the */
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/* Extended System Description Table (XSDT) */
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/********************************************/
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typedef struct
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{
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ACPI_TABLE_HEADER Header; /* Table header */
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UINT64 TableOffsetEntry [1]; /* Array of pointers to */
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/* other tables' headers */
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} XSDT_DESCRIPTOR_REV2;
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/***************************************/
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/* ACPI Specification Rev 2.0 for */
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/* the Firmware ACPI Control Structure */
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/***************************************/
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typedef struct
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{
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NATIVE_CHAR Signature[4]; /* signature "FACS" */
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UINT32 Length; /* length of structure, in bytes */
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UINT32 HardwareSignature; /* hardware configuration signature */
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UINT32 FirmwareWakingVector; /* 32bit physical address of the Firmware Waking Vector. */
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UINT32 GlobalLock; /* Global Lock used to synchronize access to shared hardware resources */
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UINT32_BIT S4Bios_f : 1; /* Indicates if S4BIOS support is present */
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UINT32_BIT Reserved1 : 31; /* must be 0 */
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UINT64 XFirmwareWakingVector; /* 64bit physical address of the Firmware Waking Vector. */
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UINT8 Version; /* Version of this table */
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UINT8 Reserved3 [31]; /* reserved - must be zero */
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} FACS_DESCRIPTOR_REV2;
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/* IA64 Root System Description Table */
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/***************************************/
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/* ACPI Specification Rev 2.0 for */
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/* the Generic Address Structure (GAS) */
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/***************************************/
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typedef struct
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{
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UINT8 AddressSpaceId; /* Address space where struct or register exists. */
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UINT8 RegisterBitWidth; /* Size in bits of given register */
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UINT8 RegisterBitOffset; /* Bit offset within the register */
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UINT8 Reserved; /* Must be 0 */
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UINT64 Address; /* 64-bit address of struct or register */
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typedef struct
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{
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ACPI_TABLE_HEADER header; /* Table header */
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UINT32 ReservedPad; /* IA64 alignment, must be 0 */
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void *TableOffsetEntry [1]; /* Array of pointers to other */
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/* tables' headers */
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} ROOT_SYSTEM_DESCRIPTION_TABLE;
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} ACPI_GAS;
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/* IA64 Firmware ACPI Control Structure */
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/************************************/
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/* ACPI Specification Rev 2.0 for */
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/* the Fixed ACPI Description Table */
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/************************************/
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typedef struct
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{
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ACPI_TABLE_HEADER header; /* table header */
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UINT32 FirmwareCtrl; /* 32-bit physical address of FACS */
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UINT32 Dsdt; /* 32-bit physical address of DSDT */
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UINT8 Reserved1; /* System Interrupt Model isn't used in ACPI 2.0*/
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UINT8 Prefer_PM_Profile; /* Conveys preferred power management profile to OSPM. */
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UINT16 SciInt; /* System vector of SCI interrupt */
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UINT32 SmiCmd; /* Port address of SMI command port */
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UINT8 AcpiEnable; /* value to write to smi_cmd to enable ACPI */
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UINT8 AcpiDisable; /* value to write to smi_cmd to disable ACPI */
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UINT8 S4BiosReq; /* Value to write to SMI CMD to enter S4BIOS state */
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UINT8 PstateCnt; /* processor performance state control*/
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UINT32 Pm1aEvtBlk; /* Port address of Power Mgt 1a AcpiEvent Reg Blk */
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UINT32 Pm1bEvtBlk; /* Port address of Power Mgt 1b AcpiEvent Reg Blk */
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UINT32 Pm1aCntBlk; /* Port address of Power Mgt 1a Control Reg Blk */
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UINT32 Pm1bCntBlk; /* Port address of Power Mgt 1b Control Reg Blk */
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UINT32 Pm2CntBlk; /* Port address of Power Mgt 2 Control Reg Blk */
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UINT32 PmTmrBlk; /* Port address of Power Mgt Timer Ctrl Reg Blk */
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UINT32 Gpe0Blk; /* Port addr of General Purpose AcpiEvent 0 Reg Blk */
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UINT32 Gpe1Blk; /* Port addr of General Purpose AcpiEvent 1 Reg Blk */
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UINT8 Pm1EvtLen; /* Byte Length of ports at pm1X_evt_blk */
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UINT8 Pm1CntLen; /* Byte Length of ports at pm1X_cnt_blk */
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UINT8 Pm2CntLen; /* Byte Length of ports at pm2_cnt_blk */
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UINT8 PmTmLen; /* Byte Length of ports at pm_tm_blk */
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UINT8 Gpe0BlkLen; /* Byte Length of ports at gpe0_blk */
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UINT8 Gpe1BlkLen; /* Byte Length of ports at gpe1_blk */
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UINT8 Gpe1Base; /* offset in gpe model where gpe1 events start */
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UINT8 CstCnt; /* Support for the _CST object and C States change notification.*/
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UINT16 Plvl2Lat; /* worst case HW latency to enter/exit C2 state */
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UINT16 Plvl3Lat; /* worst case HW latency to enter/exit C3 state */
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UINT16 FlushSize; /* number of flush strides that need to be read */
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UINT16 FlushStride; /* Processor's memory cache line width, in bytes */
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UINT8 DutyOffset; /* Processor’s duty cycle index in processor's P_CNT reg*/
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UINT8 DutyWidth; /* Processor’s duty cycle value bit width in P_CNT register.*/
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UINT8 DayAlrm; /* index to day-of-month alarm in RTC CMOS RAM */
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UINT8 MonAlrm; /* index to month-of-year alarm in RTC CMOS RAM */
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UINT8 Century; /* index to century in RTC CMOS RAM */
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UINT16 IapcBootArch; /* IA-PC Boot Architecture Flags. See Table 5-10 for description*/
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UINT8 Reserved2; /* reserved */
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UINT32_BIT WbInvd : 1; /* wbinvd instruction works properly */
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UINT32_BIT WbInvdFlush : 1; /* wbinvd flushes but does not invalidate */
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UINT32_BIT ProcC1 : 1; /* all processors support C1 state */
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UINT32_BIT Plvl2Up : 1; /* C2 state works on MP system */
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UINT32_BIT PwrButton : 1; /* Power button is handled as a generic feature */
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UINT32_BIT SleepButton : 1; /* Sleep button is handled as a generic feature, or not present */
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UINT32_BIT FixedRTC : 1; /* RTC wakeup stat not in fixed register space */
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UINT32_BIT Rtcs4 : 1; /* RTC wakeup stat not possible from S4 */
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UINT32_BIT TmrValExt : 1; /* tmr_val is 32 bits */
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UINT32_BIT DockCap : 1; /* Supports Docking */
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UINT32_BIT ResetRegSup : 1; /* Indicates system supports system reset via the FADT RESET_REG*/
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UINT32_BIT SealedCase : 1; /* Indicates system has no internal expansion capabilities and case is sealed. */
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UINT32_BIT Headless : 1; /* Indicates system does not have local video capabilities or local input devices.*/
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UINT32_BIT CpuSwSleep : 1; /* Indicates to OSPM that a processor native instruction */
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/* must be executed after writing the SLP_TYPx register. */
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UINT32_BIT Reserved6 : 18; /* reserved - must be zero */
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typedef struct
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{
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char Signature[4]; /* signature "FACS" */
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UINT32 Length; /* length of structure, in bytes */
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UINT32 HardwareSignature; /* hardware configuration signature */
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UINT32 Reserved4; /* must be 0 */
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UINT64 FirmwareWakingVector; /* ACPI OS waking vector */
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UINT64 GlobalLock; /* Global Lock */
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UINT32_BIT S4Bios_f : 1; /* Indicates if S4BIOS support is present */
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UINT32_BIT Reserved1 : 31; /* must be 0 */
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UINT8 Resverved3 [28]; /* reserved - must be zero */
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ACPI_GAS ResetRegister; /* Reset register address in GAS format */
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UINT8 ResetValue; /* Value to write to the ResetRegister port to reset the system. */
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UINT8 Reserved7[3]; /* These three bytes must be zero */
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UINT64 XFirmwareCtrl; /* 64-bit physical address of FACS */
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UINT64 XDsdt; /* 64-bit physical address of DSDT */
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ACPI_GAS XPm1aEvtBlk; /* Extended Power Mgt 1a AcpiEvent Reg Blk address */
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ACPI_GAS XPm1bEvtBlk; /* Extended Power Mgt 1b AcpiEvent Reg Blk address */
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ACPI_GAS XPm1aCntBlk; /* Extended Power Mgt 1a Control Reg Blk address */
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ACPI_GAS XPm1bCntBlk; /* Extended Power Mgt 1b Control Reg Blk address */
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ACPI_GAS XPm2CntBlk; /* Extended Power Mgt 2 Control Reg Blk address */
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ACPI_GAS XPmTmrBlk; /* Extended Power Mgt Timer Ctrl Reg Blk address */
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ACPI_GAS XGpe0Blk; /* Extended General Purpose AcpiEvent 0 Reg Blk address */
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ACPI_GAS XGpe1Blk; /* Extended General Purpose AcpiEvent 1 Reg Blk address */
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} FIRMWARE_ACPI_CONTROL_STRUCTURE;
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} FADT_DESCRIPTOR_REV2;
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#pragma pack()
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/* IA64 Fixed ACPI Description Table */
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typedef struct
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{
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ACPI_TABLE_HEADER header; /* table header */
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UINT32 ReservedPad; /* IA64 alignment, must be 0 */
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ACPI_TBLPTR FirmwareCtrl; /* Physical address of FACS */
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ACPI_TBLPTR Dsdt; /* Physical address of DSDT */
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UINT8 Model; /* System Interrupt Model */
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UINT8 AddressSpace; /* Address Space Bitmask */
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UINT16 SciInt; /* System vector of SCI interrupt */
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UINT8 AcpiEnable; /* value to write to smi_cmd to enable ACPI */
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UINT8 AcpiDisable; /* value to write to smi_cmd to disable ACPI */
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UINT8 S4BiosReq; /* Value to write to SMI CMD to enter S4BIOS state */
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UINT8 Reserved2; /* reserved - must be zero */
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UINT64 SmiCmd; /* Port address of SMI command port */
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UINT64 Pm1aEvtBlk; /* Port address of Power Mgt 1a Event Reg Blk */
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UINT64 Pm1bEvtBlk; /* Port address of Power Mgt 1b Event Reg Blk */
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UINT64 Pm1aCntBlk; /* Port address of Power Mgt 1a Control Reg Blk */
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UINT64 Pm1bCntBlk; /* Port address of Power Mgt 1b Control Reg Blk */
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UINT64 Pm2CntBlk; /* Port address of Power Mgt 2 Control Reg Blk */
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UINT64 PmTmrBlk; /* Port address of Power Mgt Timer Ctrl Reg Blk */
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UINT64 Gpe0Blk; /* Port addr of General Purpose Event 0 Reg Blk */
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UINT64 Gpe1Blk; /* Port addr of General Purpose Event 1 Reg Blk */
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UINT8 Pm1EvtLen; /* Byte Length of ports at pm1X_evt_blk */
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UINT8 Pm1CntLen; /* Byte Length of ports at pm1X_cnt_blk */
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UINT8 Pm2CntLen; /* Byte Length of ports at pm2_cnt_blk */
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UINT8 PmTmLen; /* Byte Length of ports at pm_tm_blk */
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UINT8 Gpe0BlkLen; /* Byte Length of ports at gpe0_blk */
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UINT8 Gpe1BlkLen; /* Byte Length of ports at gpe1_blk */
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UINT8 Gpe1Base; /* offset in gpe model where gpe1 events start */
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UINT8 Reserved3; /* reserved */
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UINT16 PLvl2Lat; /* worst case HW latency to enter/exit C2 state */
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UINT16 PLvl3Lat; /* worst case HW latency to enter/exit C3 state */
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UINT8 DayAlrm; /* index to day-of-month alarm in RTC CMOS RAM */
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UINT8 MonAlrm; /* index to month-of-year alarm in RTC CMOS RAM */
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UINT8 Century; /* index to century in RTC CMOS RAM */
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UINT8 Reserved4; /* reserved */
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UINT32_BIT FlushCash : 1; /* PAL_FLUSH_CACHE is correctly supported */
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UINT32_BIT Reserved5 : 1; /* reserved - must be zero */
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UINT32_BIT ProcC1 : 1; /* all processors support C1 state */
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UINT32_BIT PLvl2Up : 1; /* C2 state works on MP system */
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UINT32_BIT PwrButton : 1; /* Power button is handled as a generic feature */
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UINT32_BIT SleepButton : 1; /* Sleep button is handled as a generic feature, or not present */
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UINT32_BIT FixedRTC : 1; /* RTC wakeup stat not in fixed register space */
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UINT32_BIT RTCS4 : 1; /* RTC wakeup stat not possible from S4 */
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UINT32_BIT TmrValExt : 1; /* tmr_val is 32 bits */
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UINT32_BIT DockCap : 1; /* Supports Docking */
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UINT32_BIT Reserved6 : 22; /* reserved - must be zero */
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} FIXED_ACPI_DESCRIPTION_TABLE;
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#endif /* __ACTBL64_H__ */
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#endif /* __ACTBL2_H__ */
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