From f22a8c4f9ff0cd8cca7b919ca430ae8522bfc76c Mon Sep 17 00:00:00 2001 From: aystarik Date: Wed, 29 Jun 2005 20:07:07 +0000 Subject: [PATCH] Resynching any changes date 2000.11.02.18.46.00; author cgreen; state Exp; --- source/include/actbl.h | 13 +-- source/include/actbl2.h | 245 ++++++++++++++++++++++++++-------------- 2 files changed, 163 insertions(+), 95 deletions(-) diff --git a/source/include/actbl.h b/source/include/actbl.h index 07c3e8a5e..eac2724cd 100644 --- a/source/include/actbl.h +++ b/source/include/actbl.h @@ -1,7 +1,7 @@ /****************************************************************************** * * Name: actbl.h - Table data structures defined in ACPI specification - * $Revision: 1.40 $ + * $Revision: 1.41 $ * *****************************************************************************/ @@ -293,13 +293,8 @@ typedef struct _AcpiTableSupport * Get the architecture-specific tables */ -#include "actbl2.h" /* Acpi 2.0 tables */ - -#ifdef IA64 -#include "actbl71.h" -#else -#include "actbl1.h" /* Acpi 1.0 tables */ -#endif - +#include "actbl1.h" /* Acpi 1.0 table defintions */ +#include "actbl71.h" /* Acpi 0.71 IA-64 Extension table defintions */ +#include "actbl2.h" /* Acpi 2.0 table definitions */ #endif /* __ACTBL_H__ */ diff --git a/source/include/actbl2.h b/source/include/actbl2.h index 0d288c7b0..d8f3102ee 100644 --- a/source/include/actbl2.h +++ b/source/include/actbl2.h @@ -1,7 +1,7 @@ - /****************************************************************************** - * - * Name: actbl64.h - ACPI tables specific to IA64 + * + * Name: actbl2.h - ACPI Specification Revision 2.0 Tables + * $Revision: 1.18 $ * *****************************************************************************/ @@ -38,9 +38,9 @@ * The above copyright and patent license is granted only if the following * conditions are met: * - * 3. Conditions + * 3. Conditions * - * 3.1. Redistribution of Source with Rights to Further Distribute Source. + * 3.1. Redistribution of Source with Rights to Further Distribute Source. * Redistribution of source code of any substantial portion of the Covered * Code or modification with rights to further distribute source must include * the above Copyright Notice, the above License, this list of Conditions, @@ -48,11 +48,11 @@ * Licensee must cause all Covered Code to which Licensee contributes to * contain a file documenting the changes Licensee made to create that Covered * Code and the date of any change. Licensee must include in that file the - * documentation of any changes made by any predecessor Licensee. Licensee + * documentation of any changes made by any predecessor Licensee. Licensee * must include a prominent statement that the modification is derived, * directly or indirectly, from Original Intel Code. * - * 3.2. Redistribution of Source with no Rights to Further Distribute Source. + * 3.2. Redistribution of Source with no Rights to Further Distribute Source. * Redistribution of source code of any substantial portion of the Covered * Code or modification without rights to further distribute source must * include the following Disclaimer and Export Compliance provision in the @@ -86,7 +86,7 @@ * INSTALLATION, TRAINING OR OTHER SERVICES. INTEL WILL NOT PROVIDE ANY * UPDATES, ENHANCEMENTS OR EXTENSIONS. INTEL SPECIFICALLY DISCLAIMS ANY * IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT AND FITNESS FOR A - * PARTICULAR PURPOSE. + * PARTICULAR PURPOSE. * * 4.2. IN NO EVENT SHALL INTEL HAVE ANY LIABILITY TO LICENSEE, ITS LICENSEES * OR ANY OTHER THIRD PARTY, FOR ANY LOST PROFITS, LOST DATA, LOSS OF USE OR @@ -114,94 +114,167 @@ * *****************************************************************************/ -#ifndef __ACTBL64_H__ -#define __ACTBL64_H__ +#ifndef __ACTBL2_H__ +#define __ACTBL2_H__ + +/**************************************/ +/* Prefered Power Management Profiles */ +/**************************************/ +#define PM_UNSPECIFIED 0 +#define PM_DESKTOP 1 +#define PM_MOBILE 2 +#define PM_WORKSTATION 3 +#define PM_ENTERPRISE_SERVER 4 +#define PM_SOHO_SERVER 5 +#define PM_APPLIANCE_PC 6 + +/*********************************************/ +/* ACPI Boot Arch Flags, See spec Table 5-10 */ +/*********************************************/ +#define BAF_LEGACY_DEVICES 0x0001 +#define BAF_8042_KEYBOARD_CONTROLLER 0x0002 + +#define FADT2_REVISION_ID 3 + +#pragma pack(1) + +/*************************************/ +/* ACPI Specification Rev 2.0 for */ +/* the Root System Description Table */ +/*************************************/ +typedef struct +{ + ACPI_TABLE_HEADER header; /* Table header */ + UINT32 TableOffsetEntry [1]; /* Array of pointers to */ + /* other tables' headers */ +} RSDT_DESCRIPTOR_REV2; -typedef UINT64 IO_ADDRESS; /* Only for clarity in declarations */ +/********************************************/ +/* ACPI Specification Rev 2.0 for the */ +/* Extended System Description Table (XSDT) */ +/********************************************/ +typedef struct +{ + ACPI_TABLE_HEADER Header; /* Table header */ + UINT64 TableOffsetEntry [1]; /* Array of pointers to */ + /* other tables' headers */ +} XSDT_DESCRIPTOR_REV2; + +/***************************************/ +/* ACPI Specification Rev 2.0 for */ +/* the Firmware ACPI Control Structure */ +/***************************************/ +typedef struct +{ + NATIVE_CHAR Signature[4]; /* signature "FACS" */ + UINT32 Length; /* length of structure, in bytes */ + UINT32 HardwareSignature; /* hardware configuration signature */ + UINT32 FirmwareWakingVector; /* 32bit physical address of the Firmware Waking Vector. */ + UINT32 GlobalLock; /* Global Lock used to synchronize access to shared hardware resources */ + UINT32_BIT S4Bios_f : 1; /* Indicates if S4BIOS support is present */ + UINT32_BIT Reserved1 : 31; /* must be 0 */ + UINT64 XFirmwareWakingVector; /* 64bit physical address of the Firmware Waking Vector. */ + UINT8 Version; /* Version of this table */ + UINT8 Reserved3 [31]; /* reserved - must be zero */ + +} FACS_DESCRIPTOR_REV2; -/* IA64 Root System Description Table */ +/***************************************/ +/* ACPI Specification Rev 2.0 for */ +/* the Generic Address Structure (GAS) */ +/***************************************/ +typedef struct +{ + UINT8 AddressSpaceId; /* Address space where struct or register exists. */ + UINT8 RegisterBitWidth; /* Size in bits of given register */ + UINT8 RegisterBitOffset; /* Bit offset within the register */ + UINT8 Reserved; /* Must be 0 */ + UINT64 Address; /* 64-bit address of struct or register */ -typedef struct -{ - ACPI_TABLE_HEADER header; /* Table header */ - UINT32 ReservedPad; /* IA64 alignment, must be 0 */ - void *TableOffsetEntry [1]; /* Array of pointers to other */ - /* tables' headers */ -} ROOT_SYSTEM_DESCRIPTION_TABLE; +} ACPI_GAS; -/* IA64 Firmware ACPI Control Structure */ +/************************************/ +/* ACPI Specification Rev 2.0 for */ +/* the Fixed ACPI Description Table */ +/************************************/ +typedef struct +{ + ACPI_TABLE_HEADER header; /* table header */ + UINT32 FirmwareCtrl; /* 32-bit physical address of FACS */ + UINT32 Dsdt; /* 32-bit physical address of DSDT */ + UINT8 Reserved1; /* System Interrupt Model isn't used in ACPI 2.0*/ + UINT8 Prefer_PM_Profile; /* Conveys preferred power management profile to OSPM. */ + UINT16 SciInt; /* System vector of SCI interrupt */ + UINT32 SmiCmd; /* Port address of SMI command port */ + UINT8 AcpiEnable; /* value to write to smi_cmd to enable ACPI */ + UINT8 AcpiDisable; /* value to write to smi_cmd to disable ACPI */ + UINT8 S4BiosReq; /* Value to write to SMI CMD to enter S4BIOS state */ + UINT8 PstateCnt; /* processor performance state control*/ + UINT32 Pm1aEvtBlk; /* Port address of Power Mgt 1a AcpiEvent Reg Blk */ + UINT32 Pm1bEvtBlk; /* Port address of Power Mgt 1b AcpiEvent Reg Blk */ + UINT32 Pm1aCntBlk; /* Port address of Power Mgt 1a Control Reg Blk */ + UINT32 Pm1bCntBlk; /* Port address of Power Mgt 1b Control Reg Blk */ + UINT32 Pm2CntBlk; /* Port address of Power Mgt 2 Control Reg Blk */ + UINT32 PmTmrBlk; /* Port address of Power Mgt Timer Ctrl Reg Blk */ + UINT32 Gpe0Blk; /* Port addr of General Purpose AcpiEvent 0 Reg Blk */ + UINT32 Gpe1Blk; /* Port addr of General Purpose AcpiEvent 1 Reg Blk */ + UINT8 Pm1EvtLen; /* Byte Length of ports at pm1X_evt_blk */ + UINT8 Pm1CntLen; /* Byte Length of ports at pm1X_cnt_blk */ + UINT8 Pm2CntLen; /* Byte Length of ports at pm2_cnt_blk */ + UINT8 PmTmLen; /* Byte Length of ports at pm_tm_blk */ + UINT8 Gpe0BlkLen; /* Byte Length of ports at gpe0_blk */ + UINT8 Gpe1BlkLen; /* Byte Length of ports at gpe1_blk */ + UINT8 Gpe1Base; /* offset in gpe model where gpe1 events start */ + UINT8 CstCnt; /* Support for the _CST object and C States change notification.*/ + UINT16 Plvl2Lat; /* worst case HW latency to enter/exit C2 state */ + UINT16 Plvl3Lat; /* worst case HW latency to enter/exit C3 state */ + UINT16 FlushSize; /* number of flush strides that need to be read */ + UINT16 FlushStride; /* Processor's memory cache line width, in bytes */ + UINT8 DutyOffset; /* Processor’s duty cycle index in processor's P_CNT reg*/ + UINT8 DutyWidth; /* Processor’s duty cycle value bit width in P_CNT register.*/ + UINT8 DayAlrm; /* index to day-of-month alarm in RTC CMOS RAM */ + UINT8 MonAlrm; /* index to month-of-year alarm in RTC CMOS RAM */ + UINT8 Century; /* index to century in RTC CMOS RAM */ + UINT16 IapcBootArch; /* IA-PC Boot Architecture Flags. See Table 5-10 for description*/ + UINT8 Reserved2; /* reserved */ + UINT32_BIT WbInvd : 1; /* wbinvd instruction works properly */ + UINT32_BIT WbInvdFlush : 1; /* wbinvd flushes but does not invalidate */ + UINT32_BIT ProcC1 : 1; /* all processors support C1 state */ + UINT32_BIT Plvl2Up : 1; /* C2 state works on MP system */ + UINT32_BIT PwrButton : 1; /* Power button is handled as a generic feature */ + UINT32_BIT SleepButton : 1; /* Sleep button is handled as a generic feature, or not present */ + UINT32_BIT FixedRTC : 1; /* RTC wakeup stat not in fixed register space */ + UINT32_BIT Rtcs4 : 1; /* RTC wakeup stat not possible from S4 */ + UINT32_BIT TmrValExt : 1; /* tmr_val is 32 bits */ + UINT32_BIT DockCap : 1; /* Supports Docking */ + UINT32_BIT ResetRegSup : 1; /* Indicates system supports system reset via the FADT RESET_REG*/ + UINT32_BIT SealedCase : 1; /* Indicates system has no internal expansion capabilities and case is sealed. */ + UINT32_BIT Headless : 1; /* Indicates system does not have local video capabilities or local input devices.*/ + UINT32_BIT CpuSwSleep : 1; /* Indicates to OSPM that a processor native instruction */ + /* must be executed after writing the SLP_TYPx register. */ + UINT32_BIT Reserved6 : 18; /* reserved - must be zero */ -typedef struct -{ - char Signature[4]; /* signature "FACS" */ - UINT32 Length; /* length of structure, in bytes */ - UINT32 HardwareSignature; /* hardware configuration signature */ - UINT32 Reserved4; /* must be 0 */ - UINT64 FirmwareWakingVector; /* ACPI OS waking vector */ - UINT64 GlobalLock; /* Global Lock */ - UINT32_BIT S4Bios_f : 1; /* Indicates if S4BIOS support is present */ - UINT32_BIT Reserved1 : 31; /* must be 0 */ - UINT8 Resverved3 [28]; /* reserved - must be zero */ + ACPI_GAS ResetRegister; /* Reset register address in GAS format */ + UINT8 ResetValue; /* Value to write to the ResetRegister port to reset the system. */ + UINT8 Reserved7[3]; /* These three bytes must be zero */ + UINT64 XFirmwareCtrl; /* 64-bit physical address of FACS */ + UINT64 XDsdt; /* 64-bit physical address of DSDT */ + ACPI_GAS XPm1aEvtBlk; /* Extended Power Mgt 1a AcpiEvent Reg Blk address */ + ACPI_GAS XPm1bEvtBlk; /* Extended Power Mgt 1b AcpiEvent Reg Blk address */ + ACPI_GAS XPm1aCntBlk; /* Extended Power Mgt 1a Control Reg Blk address */ + ACPI_GAS XPm1bCntBlk; /* Extended Power Mgt 1b Control Reg Blk address */ + ACPI_GAS XPm2CntBlk; /* Extended Power Mgt 2 Control Reg Blk address */ + ACPI_GAS XPmTmrBlk; /* Extended Power Mgt Timer Ctrl Reg Blk address */ + ACPI_GAS XGpe0Blk; /* Extended General Purpose AcpiEvent 0 Reg Blk address */ + ACPI_GAS XGpe1Blk; /* Extended General Purpose AcpiEvent 1 Reg Blk address */ -} FIRMWARE_ACPI_CONTROL_STRUCTURE; +} FADT_DESCRIPTOR_REV2; +#pragma pack() -/* IA64 Fixed ACPI Description Table */ - -typedef struct -{ - ACPI_TABLE_HEADER header; /* table header */ - UINT32 ReservedPad; /* IA64 alignment, must be 0 */ - ACPI_TBLPTR FirmwareCtrl; /* Physical address of FACS */ - ACPI_TBLPTR Dsdt; /* Physical address of DSDT */ - UINT8 Model; /* System Interrupt Model */ - UINT8 AddressSpace; /* Address Space Bitmask */ - UINT16 SciInt; /* System vector of SCI interrupt */ - UINT8 AcpiEnable; /* value to write to smi_cmd to enable ACPI */ - UINT8 AcpiDisable; /* value to write to smi_cmd to disable ACPI */ - UINT8 S4BiosReq; /* Value to write to SMI CMD to enter S4BIOS state */ - UINT8 Reserved2; /* reserved - must be zero */ - UINT64 SmiCmd; /* Port address of SMI command port */ - UINT64 Pm1aEvtBlk; /* Port address of Power Mgt 1a Event Reg Blk */ - UINT64 Pm1bEvtBlk; /* Port address of Power Mgt 1b Event Reg Blk */ - UINT64 Pm1aCntBlk; /* Port address of Power Mgt 1a Control Reg Blk */ - UINT64 Pm1bCntBlk; /* Port address of Power Mgt 1b Control Reg Blk */ - UINT64 Pm2CntBlk; /* Port address of Power Mgt 2 Control Reg Blk */ - UINT64 PmTmrBlk; /* Port address of Power Mgt Timer Ctrl Reg Blk */ - UINT64 Gpe0Blk; /* Port addr of General Purpose Event 0 Reg Blk */ - UINT64 Gpe1Blk; /* Port addr of General Purpose Event 1 Reg Blk */ - UINT8 Pm1EvtLen; /* Byte Length of ports at pm1X_evt_blk */ - UINT8 Pm1CntLen; /* Byte Length of ports at pm1X_cnt_blk */ - UINT8 Pm2CntLen; /* Byte Length of ports at pm2_cnt_blk */ - UINT8 PmTmLen; /* Byte Length of ports at pm_tm_blk */ - UINT8 Gpe0BlkLen; /* Byte Length of ports at gpe0_blk */ - UINT8 Gpe1BlkLen; /* Byte Length of ports at gpe1_blk */ - UINT8 Gpe1Base; /* offset in gpe model where gpe1 events start */ - UINT8 Reserved3; /* reserved */ - UINT16 PLvl2Lat; /* worst case HW latency to enter/exit C2 state */ - UINT16 PLvl3Lat; /* worst case HW latency to enter/exit C3 state */ - UINT8 DayAlrm; /* index to day-of-month alarm in RTC CMOS RAM */ - UINT8 MonAlrm; /* index to month-of-year alarm in RTC CMOS RAM */ - UINT8 Century; /* index to century in RTC CMOS RAM */ - UINT8 Reserved4; /* reserved */ - UINT32_BIT FlushCash : 1; /* PAL_FLUSH_CACHE is correctly supported */ - UINT32_BIT Reserved5 : 1; /* reserved - must be zero */ - UINT32_BIT ProcC1 : 1; /* all processors support C1 state */ - UINT32_BIT PLvl2Up : 1; /* C2 state works on MP system */ - UINT32_BIT PwrButton : 1; /* Power button is handled as a generic feature */ - UINT32_BIT SleepButton : 1; /* Sleep button is handled as a generic feature, or not present */ - UINT32_BIT FixedRTC : 1; /* RTC wakeup stat not in fixed register space */ - UINT32_BIT RTCS4 : 1; /* RTC wakeup stat not possible from S4 */ - UINT32_BIT TmrValExt : 1; /* tmr_val is 32 bits */ - UINT32_BIT DockCap : 1; /* Supports Docking */ - UINT32_BIT Reserved6 : 22; /* reserved - must be zero */ - -} FIXED_ACPI_DESCRIPTION_TABLE; - - -#endif /* __ACTBL64_H__ */ +#endif /* __ACTBL2_H__ */