mirror of https://github.com/libsdl-org/SDL
GPU: Fix documentation formatting
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cosmonaut
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@ -307,28 +307,71 @@ typedef enum SDL_GPUIndexElementSize
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* a format is supported before using it. However, there are a few guaranteed
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* formats.
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*
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* For SAMPLER usage, the following formats are universally supported: -
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* R8G8B8A8_UNORM - B8G8R8A8_UNORM - R8_UNORM - R8_SNORM - R8G8_UNORM -
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* R8G8_SNORM - R8G8B8A8_SNORM - R16_FLOAT - R16G16_FLOAT - R16G16B16A16_FLOAT
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* - R32_FLOAT - R32G32_FLOAT - R32G32B32A32_FLOAT - R11G11B10_UFLOAT -
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* R8G8B8A8_UNORM_SRGB - B8G8R8A8_UNORM_SRGB - D16_UNORM
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* For SAMPLER usage, the following formats are universally supported:
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*
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* For COLOR_TARGET usage, the following formats are universally supported: -
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* R8G8B8A8_UNORM - B8G8R8A8_UNORM - R8_UNORM - R16_FLOAT - R16G16_FLOAT -
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* R16G16B16A16_FLOAT - R32_FLOAT - R32G32_FLOAT - R32G32B32A32_FLOAT -
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* R8_UINT - R8G8_UINT - R8G8B8A8_UINT - R16_UINT - R16G16_UINT -
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* R16G16B16A16_UINT - R8_INT - R8G8_INT - R8G8B8A8_INT - R16_INT - R16G16_INT
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* - R16G16B16A16_INT - R8G8B8A8_UNORM_SRGB - B8G8R8A8_UNORM_SRGB
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* - R8G8B8A8_UNORM
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* - B8G8R8A8_UNORM
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* - R8_UNORM
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* - R8_SNORM
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* - R8G8_UNORM
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* - R8G8_SNORM
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* - R8G8B8A8_SNORM
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* - R16_FLOAT
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* - R16G16_FLOAT
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* - R16G16B16A16_FLOAT
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* - R32_FLOAT
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* - R32G32_FLOAT
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* - R32G32B32A32_FLOAT
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* - R11G11B10_UFLOAT
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* - R8G8B8A8_UNORM_SRGB
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* - B8G8R8A8_UNORM_SRGB
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* - D16_UNORM
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*
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* For STORAGE usages, the following formats are universally supported: -
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* R8G8B8A8_UNORM - R8G8B8A8_SNORM - R16G16B16A16_FLOAT - R32_FLOAT -
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* R32G32_FLOAT - R32G32B32A32_FLOAT - R8G8B8A8_UINT - R16G16B16A16_UINT -
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* R8G8B8A8_INT - R16G16B16A16_INT
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* For COLOR_TARGET usage, the following formats are universally supported:
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*
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* - R8G8B8A8_UNORM
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* - B8G8R8A8_UNORM
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* - R8_UNORM
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* - R16_FLOAT
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* - R16G16_FLOAT
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* - R16G16B16A16_FLOAT
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* - R32_FLOAT
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* - R32G32_FLOAT
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* - R32G32B32A32_FLOAT
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* - R8_UINT
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* - R8G8_UINT
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* - R8G8B8A8_UINT
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* - R16_UINT
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* - R16G16_UINT
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* - R16G16B16A16_UINT
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* - R8_INT
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* - R8G8_INT
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* - R8G8B8A8_INT
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* - R16_INT
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* - R16G16_INT
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* - R16G16B16A16_INT
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* - R8G8B8A8_UNORM_SRGB
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* - B8G8R8A8_UNORM_SRGB
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*
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* For STORAGE usages, the following formats are universally supported:
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*
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* - R8G8B8A8_UNORM
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* - R8G8B8A8_SNORM
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* - R16G16B16A16_FLOAT
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* - R32_FLOAT
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* - R32G32_FLOAT
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* - R32G32B32A32_FLOAT
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* - R8G8B8A8_UINT
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* - R16G16B16A16_UINT
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* - R8G8B8A8_INT
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* - R16G16B16A16_INT
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*
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* For DEPTH_STENCIL_TARGET usage, the following formats are universally
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* supported: - D16_UNORM - Either (but not necessarily both!) D24_UNORM or
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* D32_SFLOAT - Either (but not necessarily both!) D24_UNORM_S8_UINT or
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* D32_SFLOAT_S8_UINT
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* supported:
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*
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* - D16_UNORM
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* - Either (but not necessarily both!) D24_UNORM or D32_SFLOAT
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* - Either (but not necessarily both!) D24_UNORM_S8_UINT or D32_SFLOAT_S8_UINT
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*
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* Unless D16_UNORM is sufficient for your purposes, always check which of
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* D24/D32 is supported before creating a depth-stencil texture!
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@ -664,7 +707,7 @@ typedef enum SDL_GPUCullMode
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typedef enum SDL_GPUFrontFace
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{
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SDL_GPU_FRONTFACE_COUNTER_CLOCKWISE, /**< A triangle with counter-clockwise vertex winding will be considered front-facing. */
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SDL_GPU_FRONTFACE_CLOCKWISE /**< A triangle with clockwise winding vertex winding will be considered front-facing. */
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SDL_GPU_FRONTFACE_CLOCKWISE /**< A triangle with clockwise vertex winding will be considered front-facing. */
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} SDL_GPUFrontFace;
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/**
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@ -820,13 +863,14 @@ typedef enum SDL_GPUSamplerAddressMode
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* It is recommended to query SDL_WindowSupportsGPUPresentMode after claiming
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* the window if you wish to change the present mode to IMMEDIATE or MAILBOX.
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*
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* VSYNC: Waits for vblank before presenting. No tearing is possible. If there
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* - VSYNC: Waits for vblank before presenting. No tearing is possible. If there
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* is a pending image to present, the new image is enqueued for presentation.
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* Disallows tearing at the cost of visual latency. When using this present
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* mode, AcquireSwapchainTexture will block if too many frames are in flight.
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* IMMEDIATE: Immediately presents. Lowest latency option, but tearing may
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* - IMMEDIATE: Immediately presents. Lowest latency option, but tearing may
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* occur. When using this mode, AcquireSwapchainTexture will return NULL if
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* too many frames are in flight. MAILBOX: Waits for vblank before presenting.
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* too many frames are in flight.
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* - MAILBOX: Waits for vblank before presenting.
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* No tearing is possible. If there is a pending image to present, the pending
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* image is replaced by the new image. Similar to VSYNC, but with reduced
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* visual latency. When using this mode, AcquireSwapchainTexture will return
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@ -855,11 +899,14 @@ typedef enum SDL_GPUPresentMode
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* claiming the window if you wish to change the swapchain composition from
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* SDR.
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*
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* SDR: B8G8R8A8 or R8G8B8A8 swapchain. Pixel values are in nonlinear sRGB
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* encoding. SDR_LINEAR: B8G8R8A8_SRGB or R8G8B8A8_SRGB swapchain. Pixel
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* values are in nonlinear sRGB encoding. HDR_EXTENDED_LINEAR:
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* - SDR: B8G8R8A8 or R8G8B8A8 swapchain. Pixel values are in nonlinear sRGB
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* encoding.
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* - SDR_LINEAR: B8G8R8A8_SRGB or R8G8B8A8_SRGB swapchain. Pixel
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* values are in nonlinear sRGB encoding.
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* - HDR_EXTENDED_LINEAR:
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* R16G16B16A16_SFLOAT swapchain. Pixel values are in extended linear
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* encoding. HDR10_ST2048: A2R10G10B10 or A2B10G10R10 swapchain. Pixel values
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* encoding.
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* - HDR10_ST2048: A2R10G10B10 or A2B10G10R10 swapchain. Pixel values
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* are in PQ ST2048 encoding.
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*
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* \since This enum is available since SDL 3.0.0
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@ -1462,25 +1509,30 @@ extern SDL_DECLSPEC SDL_GPUDriver SDLCALL SDL_GetGPUDriver(SDL_GPUDevice *device
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/**
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* Creates a pipeline object to be used in a compute workflow.
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*
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* Shader resource bindings must be authored to follow a particular order. For
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* SPIR-V shaders, use the following resource sets: 0: Read-only storage
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* textures, followed by read-only storage buffers 1: Write-only storage
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* textures, followed by write-only storage buffers 2: Uniform buffers
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* Shader resource bindings must be authored to follow a particular order depending on the shader format.
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*
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* For DXBC Shader Model 5_0 shaders, use the following register order: For t
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* registers: Read-only storage textures, followed by read-only storage
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* buffers For u registers: Write-only storage textures, followed by
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* write-only storage buffers For b registers: Uniform buffers
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* For SPIR-V shaders, use the following resource sets:
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*
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* For DXIL shaders, use the following register order: (t[n], space0):
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* Read-only storage textures, followed by read-only storage buffers (u[n],
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* space1): Write-only storage textures, followed by write-only storage
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* buffers (b[n], space2): Uniform buffers
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* - 0: Read-only storage textures, followed by read-only storage buffers
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* - 1: Write-only storage textures, followed by write-only storage buffers
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* - 2: Uniform buffers
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*
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* For MSL/metallib, use the following order: For [[buffer]]: Uniform buffers,
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* followed by write-only storage buffers, followed by write-only storage
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* buffers For [[texture]]: Read-only storage textures, followed by write-only
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* storage textures
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* For DXBC Shader Model 5_0 shaders, use the following register order:
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*
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* - t registers: Read-only storage textures, followed by read-only storage buffers
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* - u registers: Write-only storage textures, followed by write-only storage buffers
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* - b registers: Uniform buffers
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*
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* For DXIL shaders, use the following register order:
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*
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* - (t[n], space0): Read-only storage textures, followed by read-only storage buffers
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* - (u[n], space1): Write-only storage textures, followed by write-only storage buffers
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* - (b[n], space2): Uniform buffers
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*
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* For MSL/metallib, use the following order:
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*
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* - [[buffer]]: Uniform buffers, followed by write-only storage buffers, followed by write-only storage buffers
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* - [[texture]]: Read-only storage textures, followed by write-only storage textures
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*
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* \param device a GPU Context.
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* \param computePipelineCreateInfo a struct describing the state of the
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@ -1536,31 +1588,49 @@ extern SDL_DECLSPEC SDL_GPUSampler *SDLCALL SDL_CreateGPUSampler(
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/**
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* Creates a shader to be used when creating a graphics pipeline.
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*
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* Shader resource bindings must be authored to follow a particular order
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* depending on the shader format.
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* Shader resource bindings must be authored to follow a particular order depending on the shader format.
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*
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* For SPIR-V shaders, use the following resource sets: For vertex shaders: 0:
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* Sampled textures, followed by storage textures, followed by storage buffers
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* 1: Uniform buffers For fragment shaders: 2: Sampled textures, followed by
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* storage textures, followed by storage buffers 3: Uniform buffers
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* For SPIR-V shaders, use the following resource sets:
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*
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* For DXBC Shader Model 5_0 shaders, use the following register order: For t
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* registers: Sampled textures, followed by storage textures, followed by
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* storage buffers For s registers: Samplers with indices corresponding to the
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* sampled textures For b registers: Uniform buffers
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* For vertex shaders:
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*
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* For DXIL shaders, use the following register order: For vertex shaders:
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* (t[n], space0): Sampled textures, followed by storage textures, followed by
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* storage buffers (s[n], space0): Samplers with indices corresponding to the
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* sampled textures (b[n], space1): Uniform buffers For pixel shaders: (t[n],
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* space2): Sampled textures, followed by storage textures, followed by
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* storage buffers (s[n], space2): Samplers with indices corresponding to the
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* sampled textures (b[n], space3): Uniform buffers
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* - 0: Sampled textures, followed by storage textures, followed by storage buffers
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* - 1: Uniform buffers
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*
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* For MSL/metallib, use the following order: For [[texture]]: Sampled
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* textures, followed by storage textures For [[sampler]]: Samplers with
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* indices corresponding to the sampled textures For [[buffer]]: Uniform
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* buffers, followed by storage buffers. Vertex buffer 0 is bound at
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* For fragment shaders:
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*
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* - 2: Sampled textures, followed by storage textures, followed by storage buffers
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* - 3: Uniform buffers
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*
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* For DXBC Shader Model 5_0 shaders, use the following register order:
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*
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* - t registers: Sampled textures, followed by storage textures, followed by storage buffers
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* - s registers: Samplers with indices corresponding to the sampled textures
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* - b registers: Uniform buffers
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*
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* For DXIL shaders, use the following register order:
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*
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* For vertex shaders:
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*
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* - (t[n], space0): Sampled textures, followed by storage textures, followed by
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* storage buffers
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* - (s[n], space0): Samplers with indices corresponding to the
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* sampled textures
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* - (b[n], space1): Uniform buffers
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*
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* For pixel shaders:
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*
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* - (t[n], space2): Sampled textures, followed by storage textures, followed by
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* storage buffers
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* - (s[n], space2): Samplers with indices corresponding to the
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* sampled textures
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* - (b[n], space3): Uniform buffers
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*
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* For MSL/metallib, use the following order:
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*
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* - [[texture]]: Sampled textures, followed by storage textures
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* - [[sampler]]: Samplers with indices corresponding to the sampled textures
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* - [[buffer]]: Uniform buffers, followed by storage buffers. Vertex buffer 0 is bound at
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* [[buffer(30)]], vertex buffer 1 at [[buffer(29)]], and so on. Rather than
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* manually authoring vertex buffer indices, use the [[stage_in]] attribute
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* which will automatically use the vertex input information from the
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