691 lines
21 KiB
C++
691 lines
21 KiB
C++
/////////////////////////////////////////////////////////////////////////
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// $Id$
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2002-2018 The Bochs Project
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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// PCI host bridge support
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// i430FX - TSC/TDP
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// i440FX - PMC/DBX
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// i440BX - Host bridge
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// Define BX_PLUGGABLE in files that can be compiled into plugins. For
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// platforms that require a special tag on exported symbols, BX_PLUGGABLE
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// is used to know when we are exporting symbols and when we are importing.
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#define BX_PLUGGABLE
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#include "iodev.h"
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#if BX_SUPPORT_PCI
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#include "pci.h"
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#define LOG_THIS thePciBridge->
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const char csname[3][20] = {"i430FX TSC", "i440FX PMC", "i440BX Host bridge"};
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bx_pci_bridge_c *thePciBridge = NULL;
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int CDECL libpci_LTX_plugin_init(plugin_t *plugin, plugintype_t type)
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{
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if (type == PLUGTYPE_CORE) {
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thePciBridge = new bx_pci_bridge_c();
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BX_REGISTER_DEVICE_DEVMODEL(plugin, type, thePciBridge, BX_PLUGIN_PCI);
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return 0; // Success
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} else {
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return -1;
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}
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}
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void CDECL libpci_LTX_plugin_fini(void)
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{
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delete thePciBridge;
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}
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bx_pci_bridge_c::bx_pci_bridge_c()
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{
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put("PCI");
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vbridge = NULL;
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}
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bx_pci_bridge_c::~bx_pci_bridge_c()
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{
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if (vbridge != NULL) {
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delete vbridge;
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}
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SIM->get_bochs_root()->remove("pci_bridge");
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BX_DEBUG(("Exit"));
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}
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void bx_pci_bridge_c::init(void)
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{
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// called once when bochs initializes
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unsigned i;
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Bit32u ramsize;
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Bit8u devfunc = BX_PCI_DEVICE(0, 0);
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BX_PCI_THIS chipset = SIM->get_param_enum(BXPN_PCI_CHIPSET)->get();
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DEV_register_pci_handlers(this, &devfunc, BX_PLUGIN_PCI, csname[BX_PCI_THIS chipset]);
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// initialize readonly registers
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if (BX_PCI_THIS chipset == BX_PCI_CHIPSET_I430FX) {
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init_pci_conf(0x8086, 0x0122, 0x02, 0x060000, 0x00, 0);
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} else if (BX_PCI_THIS chipset == BX_PCI_CHIPSET_I440BX) {
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init_pci_conf(0x8086, 0x7190, 0x02, 0x060000, 0x00, 0);
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BX_PCI_THIS pci_conf[0x10] = 0x08;
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init_bar_mem(0, 0xf0000000, agp_ap_read_handler, agp_ap_write_handler);
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BX_PCI_THIS pci_conf[0x06] = 0x10;
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BX_PCI_THIS pci_conf[0x34] = 0xa0;
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BX_PCI_THIS pci_conf[0xa0] = 0x02;
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BX_PCI_THIS pci_conf[0xa2] = 0x10;
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BX_PCI_THIS pci_conf[0xa4] = 0x03;
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BX_PCI_THIS pci_conf[0xa5] = 0x02;
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BX_PCI_THIS pci_conf[0xa7] = 0x1f;
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BX_PCI_THIS pci_conf[0xf3] = 0xf8;
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BX_PCI_THIS pci_conf[0xf8] = 0x20;
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BX_PCI_THIS pci_conf[0xf9] = 0x0f;
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BX_PCI_THIS vbridge = new bx_pci_vbridge_c();
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BX_PCI_THIS vbridge->init();
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} else { // i440FX
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init_pci_conf(0x8086, 0x1237, 0x00, 0x060000, 0x00, 0);
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}
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// DRAM module setup
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for (i = 0; i < 8; i++)
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BX_PCI_THIS DRBA[i] = 0x0;
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ramsize = SIM->get_param_num(BXPN_MEM_SIZE)->get();
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if ((ramsize & 0x07) != 0) {
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ramsize = (ramsize & ~0x07) + 8;
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}
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if (BX_PCI_THIS chipset == BX_PCI_CHIPSET_I430FX) {
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if (ramsize > 128) ramsize = 128;
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if (ramsize == 8) {
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for (i = 0; i < 5; i++) {
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BX_PCI_THIS DRBA[i] = 0x02;
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}
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} else if (ramsize == 16) {
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BX_PCI_THIS DRBA[0] = 0x02;
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for (i = 1; i < 5; i++) {
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BX_PCI_THIS DRBA[i] = 0x04;
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}
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} else if (ramsize == 24) {
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BX_PCI_THIS DRBA[0] = 0x02;
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BX_PCI_THIS DRBA[1] = 0x04;
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for (i = 2; i < 5; i++) {
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BX_PCI_THIS DRBA[i] = 0x06;
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}
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} else if (ramsize == 32) {
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BX_PCI_THIS DRBA[0] = 0x04;
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for (i = 1; i < 5; i++) {
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BX_PCI_THIS DRBA[i] = 0x08;
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}
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} else if (ramsize <= 48) {
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BX_PCI_THIS DRBA[0] = 0x04;
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BX_PCI_THIS DRBA[1] = 0x08;
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for (i = 2; i < 5; i++) {
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BX_PCI_THIS DRBA[i] = 0x0c;
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}
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} else if (ramsize <= 64) {
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BX_PCI_THIS DRBA[0] = 0x08;
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for (i = 1; i < 5; i++) {
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BX_PCI_THIS DRBA[i] = 0x10;
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}
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} else if (ramsize <= 96) {
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BX_PCI_THIS DRBA[0] = 0x04;
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BX_PCI_THIS DRBA[1] = 0x08;
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BX_PCI_THIS DRBA[2] = 0x10;
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BX_PCI_THIS DRBA[3] = 0x18;
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BX_PCI_THIS DRBA[4] = 0x18;
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} else if (ramsize <= 128) {
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BX_PCI_THIS DRBA[0] = 0x10;
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for (i = 1; i < 5; i++) {
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BX_PCI_THIS DRBA[i] = 0x20;
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}
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}
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} else { // i440FX
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const Bit8u type[3] = {128, 32, 8};
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if (ramsize > 1024) ramsize = 1024;
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Bit8u drbval = 0;
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unsigned row = 0;
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unsigned ti = 0;
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while ((ramsize > 0) && (row < 8) && (ti < 3)) {
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unsigned mc = ramsize / type[ti];
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ramsize = ramsize % type[ti];
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for (i = 0; i < mc; i++) {
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drbval += (type[ti] >> 3);
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BX_PCI_THIS DRBA[row++] = drbval;
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if (row == 8) break;
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}
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ti++;
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}
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while (row < 8) {
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BX_PCI_THIS DRBA[row++] = drbval;
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}
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}
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for (i = 0; i < 8; i++)
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BX_PCI_THIS pci_conf[0x60 + i] = BX_PCI_THIS DRBA[i];
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dram_detect = 0;
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#if BX_DEBUGGER
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// register device for the 'info device' command (calls debug_dump())
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bx_dbg_register_debug_info("pci", this);
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#endif
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}
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void
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bx_pci_bridge_c::reset(unsigned type)
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{
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unsigned i;
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BX_PCI_THIS pci_conf[0x04] = 0x06;
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BX_PCI_THIS pci_conf[0x05] = 0x00;
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BX_PCI_THIS pci_conf[0x07] = 0x02;
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BX_PCI_THIS pci_conf[0x0d] = 0x00;
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BX_PCI_THIS pci_conf[0x0f] = 0x00;
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BX_PCI_THIS pci_conf[0x50] = 0x00;
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BX_PCI_THIS pci_conf[0x52] = 0x00;
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BX_PCI_THIS pci_conf[0x53] = 0x80;
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BX_PCI_THIS pci_conf[0x54] = 0x00;
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BX_PCI_THIS pci_conf[0x55] = 0x00;
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BX_PCI_THIS pci_conf[0x56] = 0x00;
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BX_PCI_THIS pci_conf[0x57] = 0x01;
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if (BX_PCI_THIS chipset == BX_PCI_CHIPSET_I430FX) {
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BX_PCI_THIS pci_conf[0x06] = 0x00;
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BX_PCI_THIS pci_conf[0x58] = 0x00;
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} else if (BX_PCI_THIS chipset == BX_PCI_CHIPSET_I440BX) {
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BX_PCI_THIS vbridge->reset(type);
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} else { // i440FX
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BX_PCI_THIS pci_conf[0x06] = 0x80;
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BX_PCI_THIS pci_conf[0x51] = 0x01;
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BX_PCI_THIS pci_conf[0x58] = 0x10;
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BX_PCI_THIS pci_conf[0xb4] = 0x00;
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BX_PCI_THIS pci_conf[0xb9] = 0x00;
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BX_PCI_THIS pci_conf[0xba] = 0x00;
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BX_PCI_THIS pci_conf[0xbb] = 0x00;
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BX_PCI_THIS gart_base = 0;
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}
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for (i=0x59; i<0x60; i++)
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BX_PCI_THIS pci_conf[i] = 0x00;
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for (i = 0; i <= BX_MEM_AREA_F0000; i++) {
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DEV_mem_set_memory_type(i, 0, 0);
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DEV_mem_set_memory_type(i, 1, 0);
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}
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BX_PCI_THIS pci_conf[0x72] = 0x02;
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}
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void bx_pci_bridge_c::register_state(void)
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{
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bx_list_c *list = new bx_list_c(SIM->get_bochs_root(), "pci_bridge", "PCI Bridge State");
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register_pci_state(list);
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if (BX_PCI_THIS chipset == BX_PCI_CHIPSET_I440BX) {
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BX_PCI_THIS vbridge->register_state();
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}
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}
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void bx_pci_bridge_c::after_restore_state(void)
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{
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BX_PCI_THIS smram_control(BX_PCI_THIS pci_conf[0x72]);
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if (BX_PCI_THIS chipset == BX_PCI_CHIPSET_I440BX) {
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BX_PCI_THIS vbridge->after_restore_state();
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}
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}
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// pci configuration space write callback handler
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void bx_pci_bridge_c::pci_write_handler(Bit8u address, Bit32u value, unsigned io_len)
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{
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Bit8u value8, oldval;
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unsigned area;
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Bit8u drba_reg, old_dram_detect;
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bx_bool drba_changed;
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bx_bool attbase_changed = 0;
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Bit32u apsize;
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old_dram_detect = BX_PCI_THIS dram_detect;
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if ((address >= 0x10) && (address < 0x34))
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return;
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BX_DEBUG_PCI_WRITE(address, value, io_len);
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for (unsigned i=0; i<io_len; i++) {
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value8 = (value >> (i*8)) & 0xFF;
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oldval = BX_PCI_THIS pci_conf[address+i];
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switch (address+i) {
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case 0x04:
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if (BX_PCI_THIS chipset == BX_PCI_CHIPSET_I430FX) {
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BX_PCI_THIS pci_conf[address+i] = (value8 & 0x02) | 0x04;
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} else {
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BX_PCI_THIS pci_conf[address+i] = (value8 & 0x40) | 0x06;
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}
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break;
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case 0x05:
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if (BX_PCI_THIS chipset != BX_PCI_CHIPSET_I430FX) {
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BX_PCI_THIS pci_conf[address+i] = (value8 & 0x01);
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}
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break;
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case 0x07:
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if (BX_PCI_THIS chipset == BX_PCI_CHIPSET_I430FX) {
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value8 &= 0x30;
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} else if (BX_PCI_THIS chipset != BX_PCI_CHIPSET_I440BX) {
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value8 = (BX_PCI_THIS pci_conf[0x07] & ~value8) | 0x02;
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} else {
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value8 &= 0xf9;
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}
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BX_PCI_THIS pci_conf[address+i] &= ~value8;
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break;
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case 0x0d:
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BX_PCI_THIS pci_conf[address+i] = (value8 & 0xf8);
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break;
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case 0x06:
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case 0x0c:
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case 0x0f:
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break;
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case 0x50:
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if (BX_PCI_THIS chipset == BX_PCI_CHIPSET_I430FX) {
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BX_PCI_THIS pci_conf[address+i] = (value8 & 0xef);
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} else if (BX_PCI_THIS chipset == BX_PCI_CHIPSET_I440BX) {
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BX_PCI_THIS pci_conf[address+i] = (value8 & 0xec);
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} else {
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BX_PCI_THIS pci_conf[address+i] = (value8 & 0x70);
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}
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break;
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case 0x51:
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if (BX_PCI_THIS chipset != BX_PCI_CHIPSET_I430FX) {
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BX_PCI_THIS pci_conf[address+i] = (value8 & 0x80) | 0x01;
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} else if (BX_PCI_THIS chipset == BX_PCI_CHIPSET_I440BX) {
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BX_PCI_THIS pci_conf[address+i] = (value8 & 0x8f);
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}
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break;
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case 0x59:
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case 0x5A:
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case 0x5B:
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case 0x5C:
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case 0x5D:
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case 0x5E:
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case 0x5F:
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if (value8 != oldval) {
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BX_PCI_THIS pci_conf[address+i] = value8;
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if ((address+i) == 0x59) {
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area = BX_MEM_AREA_F0000;
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DEV_mem_set_memory_type(area, 0, (value8 >> 4) & 0x1);
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DEV_mem_set_memory_type(area, 1, (value8 >> 5) & 0x1);
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} else {
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area = ((address+i) - 0x5a) << 1;
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DEV_mem_set_memory_type(area, 0, (value8 >> 0) & 0x1);
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DEV_mem_set_memory_type(area, 1, (value8 >> 1) & 0x1);
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area++;
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DEV_mem_set_memory_type(area, 0, (value8 >> 4) & 0x1);
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DEV_mem_set_memory_type(area, 1, (value8 >> 5) & 0x1);
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}
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BX_INFO(("%s write to PAM register %x (TLB Flush)", csname[BX_PCI_THIS chipset], address+i));
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bx_pc_system.MemoryMappingChanged();
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}
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break;
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case 0x60:
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case 0x61:
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case 0x62:
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case 0x63:
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case 0x64:
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case 0x65:
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case 0x66:
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case 0x67:
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BX_PCI_THIS pci_conf[address+i] = value8;
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drba_reg = (address + i) & 0x07;
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drba_changed = (BX_PCI_THIS pci_conf[0x60 + drba_reg] != BX_PCI_THIS DRBA[drba_reg]);
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if (drba_changed) {
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BX_PCI_THIS dram_detect |= (1 << drba_reg);
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} else if (!drba_changed && dram_detect) {
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BX_PCI_THIS dram_detect &= ~(1 << drba_reg);
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}
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break;
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case 0x72:
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smram_control(value8); // SMRAM control register
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break;
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case 0xb4:
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if (BX_PCI_THIS chipset == BX_PCI_CHIPSET_I440BX) {
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BX_PCI_THIS pci_conf[address+i] = value8 & 0x3f;
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switch (BX_PCI_THIS pci_conf[0xb4]) {
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case 0x00:
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apsize = (1 << 28);
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break;
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case 0x20:
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apsize = (1 << 27);
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break;
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case 0x30:
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apsize = (1 << 26);
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break;
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case 0x38:
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apsize = (1 << 25);
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break;
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case 0x3c:
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apsize = (1 << 24);
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break;
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case 0x3e:
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apsize = (1 << 23);
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break;
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case 0x3f:
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apsize = (1 << 22);
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break;
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default:
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BX_ERROR(("Invalid AGP aperture size mask"));
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apsize = 0;
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}
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BX_INFO(("AGP aperture size set to %d MB", apsize >> 20));
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pci_bar[0].size = apsize;
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}
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break;
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case 0xb8:
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break;
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case 0xb9:
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value8 &= 0xf0;
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case 0xba:
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case 0xbb:
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if ((BX_PCI_THIS chipset == BX_PCI_CHIPSET_I440BX) &&
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(value8 != oldval)) {
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BX_PCI_THIS pci_conf[address+i] = value8;
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attbase_changed |= 1;
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}
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break;
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case 0xf0:
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if (BX_PCI_THIS chipset == BX_PCI_CHIPSET_I440BX) {
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BX_PCI_THIS pci_conf[address+i] = value8 & 0xc0;
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}
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break;
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default:
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BX_PCI_THIS pci_conf[address+i] = value8;
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BX_DEBUG(("%s write register 0x%02x value 0x%02x", csname[BX_PCI_THIS chipset], address+i, value8));
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}
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}
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if ((BX_PCI_THIS dram_detect > 0) && (old_dram_detect == 0)) {
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// TODO
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BX_ERROR(("FIXME: DRAM module detection"));
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} else if ((BX_PCI_THIS dram_detect == 0) && (old_dram_detect > 0)) {
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// TODO
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BX_INFO(("normal memory access mode"));
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}
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if (attbase_changed) {
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BX_PCI_THIS gart_base = ((BX_PCI_THIS pci_conf[0xbb] << 24) |
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(BX_PCI_THIS pci_conf[0xba] << 16) |
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(BX_PCI_THIS pci_conf[0xb9] << 8));
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BX_INFO(("New GART base address = 0x%08x", BX_PCI_THIS gart_base));
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}
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}
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bx_bool bx_pci_bridge_c::agp_ap_read_handler(bx_phy_address addr, unsigned len,
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void *data, void *param)
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{
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bx_pci_bridge_c *class_ptr = (bx_pci_bridge_c*)param;
|
|
Bit32u value = class_ptr->agp_aperture_read(addr, len, 0);
|
|
switch (len) {
|
|
case 1:
|
|
value &= 0xFF;
|
|
*((Bit8u *) data) = (Bit8u) value;
|
|
break;
|
|
case 2:
|
|
value &= 0xFFFF;
|
|
*((Bit16u *) data) = (Bit16u) value;
|
|
break;
|
|
case 4:
|
|
*((Bit32u *) data) = value;
|
|
break;
|
|
}
|
|
return 1;
|
|
}
|
|
|
|
Bit32u bx_pci_bridge_c::agp_aperture_read(bx_phy_address addr, unsigned len,
|
|
bx_bool agp)
|
|
{
|
|
if (BX_PCI_THIS pci_conf[0x51] & 0x02) {
|
|
Bit32u offset = (Bit32u)(addr - pci_bar[0].addr);
|
|
Bit32u gart_index = (Bit32u)(offset >> 12);
|
|
Bit32u page_offset = (Bit32u)(offset & 0xfff);
|
|
Bit32u gart_addr = BX_PCI_THIS gart_base + (gart_index << 2);
|
|
Bit32u page_addr;
|
|
DEV_MEM_READ_PHYSICAL(gart_addr, 4, (Bit8u*)&page_addr);
|
|
BX_INFO(("TODO: AGP aperture read: page address = 0x%08x / offset = 0x%04x",
|
|
page_addr, (Bit16u)page_offset));
|
|
// TODO
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
bx_bool bx_pci_bridge_c::agp_ap_write_handler(bx_phy_address addr, unsigned len,
|
|
void *data, void *param)
|
|
{
|
|
bx_pci_bridge_c *class_ptr = (bx_pci_bridge_c*)param;
|
|
Bit32u value = *(Bit32u*)data;
|
|
class_ptr->agp_aperture_write(addr, value, len, 0);
|
|
return 1;
|
|
}
|
|
|
|
void bx_pci_bridge_c::agp_aperture_write(bx_phy_address addr, Bit32u value,
|
|
unsigned len, bx_bool agp)
|
|
{
|
|
if (BX_PCI_THIS pci_conf[0x51] & 0x02) {
|
|
Bit32u offset = (Bit32u)(addr - pci_bar[0].addr);
|
|
Bit32u gart_index = (Bit32u)(offset >> 12);
|
|
Bit32u page_offset = (Bit32u)(offset & 0xfff);
|
|
Bit32u gart_addr = BX_PCI_THIS gart_base + (gart_index << 2);
|
|
Bit32u page_addr;
|
|
DEV_MEM_READ_PHYSICAL(gart_addr, 4, (Bit8u*)&page_addr);
|
|
BX_INFO(("TODO: AGP aperture write: page address = 0x%08x / offset = 0x%04x",
|
|
page_addr, (Bit16u)page_offset));
|
|
// TODO
|
|
}
|
|
}
|
|
|
|
void bx_pci_bridge_c::smram_control(Bit8u value8)
|
|
{
|
|
//
|
|
// From i440FX chipset manual:
|
|
//
|
|
// [7:7] Reserved.
|
|
// [6:6] SMM Space Open (DOPEN), when DOPEN=1 and DLCK=0, SMM space DRAM
|
|
// became visible even CPU not indicte SMM mode access. This is
|
|
// indended to help BIOS to initialize SMM space.
|
|
// [5:5] SMM Space Closed (DCLS), when DCLS=1, SMM space is not accessible
|
|
// for data references, even if CPU indicates SMM mode access. Code
|
|
// references may still access SMM space DRAM.
|
|
// [4:4] SMM Space Locked (DLCK), when DLCK=1, DOPEN is set to 0 and
|
|
// both DLCK and DOPEN became R/O. DLCK can only be cleared by
|
|
// a power-on reset.
|
|
// [3:3] SMRAM Enable (SMRAME)
|
|
// [2:0] SMM space base segment, program the location of SMM space
|
|
// reserved.
|
|
//
|
|
|
|
// SMRAM space access cycles:
|
|
|
|
// | SMRAME | DLCK | DCLS | DOPEN | CPU_SMM | | Code | Data |
|
|
// ------------------------------------------ ---------------
|
|
// | 0 | X | X | X | X | -> | PCI | PCI |
|
|
// | 1 | 0 | X | 0 | 0 | -> | PCI | PCI |
|
|
// | 1 | 0 | 0 | 0 | 1 | -> | DRAM | DRAM |
|
|
// | 1 | 0 | 0 | 1 | X | -> | DRAM | DRAM |
|
|
// | 1 | 1 | 0 | X | 1 | -> | DRAM | DRAM |
|
|
// | 1 | 0 | 1 | 0 | 1 | -> | DRAM | PCI |
|
|
// | 1 | 0 | 1 | 1 | X | -> | ---- | ---- |
|
|
// | 1 | 1 | X | X | 0 | -> | PCI | PCI |
|
|
// | 1 | 1 | 1 | X | 1 | -> | DRAM | PCI |
|
|
// ------------------------------------------ ---------------
|
|
|
|
value8 = (value8 & 0x78) | 0x2; // ignore reserved bits
|
|
|
|
if (BX_PCI_THIS pci_conf[0x72] & 0x10)
|
|
{
|
|
value8 &= 0xbf; // set DOPEN=0, DLCK=1
|
|
value8 |= 0x10;
|
|
}
|
|
|
|
if ((value8 & 0x08) == 0) {
|
|
bx_devices.mem->disable_smram();
|
|
}
|
|
else {
|
|
bx_bool DOPEN = (value8 & 0x40) > 0, DCLS = (value8 & 0x20) > 0;
|
|
if(DOPEN && DCLS) BX_PANIC(("SMRAM control: DOPEN not mutually exclusive with DCLS !"));
|
|
bx_devices.mem->enable_smram(DOPEN, DCLS);
|
|
}
|
|
|
|
BX_INFO(("setting SMRAM control register to 0x%02x", value8));
|
|
BX_PCI_THIS pci_conf[0x72] = value8;
|
|
}
|
|
|
|
#if BX_DEBUGGER
|
|
void bx_pci_bridge_c::debug_dump(int argc, char **argv)
|
|
{
|
|
int arg, i, j, r;
|
|
|
|
if (BX_PCI_THIS chipset == BX_PCI_CHIPSET_I430FX) {
|
|
dbg_printf("i430FX TSC/TDP");
|
|
} else if (BX_PCI_THIS chipset == BX_PCI_CHIPSET_I440BX) {
|
|
dbg_printf("i440BX Host bridge");
|
|
} else {
|
|
dbg_printf("i440FX PMC/DBX");
|
|
}
|
|
dbg_printf("\n\nconfAddr = 0x%08x\n\n", DEV_pci_get_confAddr());
|
|
|
|
if (argc == 0) {
|
|
for (i = 0x59; i < 0x60; i++) {
|
|
dbg_printf("PAM reg 0x%02x = 0x%02x\n", i, BX_PCI_THIS pci_conf[i]);
|
|
}
|
|
dbg_printf("SMRAM control = 0x%02x\n", BX_PCI_THIS pci_conf[0x72]);
|
|
dbg_printf("\nSupported options:\n");
|
|
dbg_printf("info device 'pci' 'dump=full' - show PCI config space\n");
|
|
} else {
|
|
for (arg = 0; arg < argc; arg++) {
|
|
if (!strcmp(argv[arg], "dump=full")) {
|
|
dbg_printf("\nPCI config space\n\n");
|
|
r = 0;
|
|
for (i=0; i<16; i++) {
|
|
dbg_printf("%04x ", r);
|
|
for (j=0; j<16; j++) {
|
|
dbg_printf(" %02x", BX_PCI_THIS pci_conf[r++]);
|
|
}
|
|
dbg_printf("\n");
|
|
}
|
|
} else {
|
|
dbg_printf("\nUnknown option: '%s'\n", argv[arg]);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
#endif
|
|
|
|
// i440BX PCI-to-AGP bridge
|
|
|
|
#undef LOG_THIS
|
|
#define LOG_THIS
|
|
|
|
bx_pci_vbridge_c::bx_pci_vbridge_c()
|
|
{
|
|
put("PCIAGP");
|
|
}
|
|
|
|
bx_pci_vbridge_c::~bx_pci_vbridge_c()
|
|
{
|
|
SIM->get_bochs_root()->remove("pci_vbridge");
|
|
BX_DEBUG(("Exit"));
|
|
}
|
|
|
|
void bx_pci_vbridge_c::init(void)
|
|
{
|
|
Bit8u devfunc = BX_PCI_DEVICE(1, 0);
|
|
DEV_register_pci_handlers(this, &devfunc, BX_PLUGIN_PCI, "i440BX PCI-to-AGP bridge");
|
|
init_pci_conf(0x8086, 0x7191, 0x02, 0x060400, 0x01, 0);
|
|
pci_conf[0x06] = 0x20;
|
|
pci_conf[0x07] = 0x02;
|
|
pci_conf[0x1e] = 0xa0;
|
|
}
|
|
|
|
void bx_pci_vbridge_c::reset(unsigned type)
|
|
{
|
|
pci_conf[0x04] = 0x00;
|
|
pci_conf[0x05] = 0x00;
|
|
pci_conf[0x1c] = 0xf0;
|
|
pci_conf[0x1f] = 0x02;
|
|
pci_conf[0x20] = 0xf0;
|
|
pci_conf[0x21] = 0xff;
|
|
pci_conf[0x22] = 0x00;
|
|
pci_conf[0x23] = 0x00;
|
|
pci_conf[0x24] = 0xf0;
|
|
pci_conf[0x25] = 0xff;
|
|
pci_conf[0x26] = 0x00;
|
|
pci_conf[0x27] = 0x00;
|
|
pci_conf[0x3e] = 0x80;
|
|
}
|
|
|
|
void bx_pci_vbridge_c::register_state(void)
|
|
{
|
|
bx_list_c *list = new bx_list_c(SIM->get_bochs_root(), "pci_vbridge", "PCI/AGP Bridge State");
|
|
register_pci_state(list);
|
|
}
|
|
|
|
void bx_pci_vbridge_c::after_restore_state(void)
|
|
{
|
|
// TODO
|
|
}
|
|
|
|
// pci configuration space write callback handler
|
|
void bx_pci_vbridge_c::pci_write_handler(Bit8u address, Bit32u value, unsigned io_len)
|
|
{
|
|
BX_DEBUG_PCI_WRITE(address, value, io_len);
|
|
|
|
for (unsigned i=0; i<io_len; i++) {
|
|
Bit8u value8 = (value >> (i*8)) & 0xff;
|
|
Bit8u oldval = pci_conf[address+i];
|
|
switch (address+i) {
|
|
case 0x04: // PCICMD1
|
|
value8 &= 0x3f;
|
|
break;
|
|
case 0x05:
|
|
value8 &= 0x01;
|
|
break;
|
|
case 0x0d: // MLT1
|
|
case 0x1b: // SMLT
|
|
value8 &= 0xf8;
|
|
break;
|
|
case 0x1c: // IOBASE
|
|
case 0x1d: // IOLIMIT
|
|
case 0x20: // MBASE lo
|
|
case 0x22: // MLIMIT lo
|
|
case 0x24: // PMBASE lo
|
|
case 0x26: // PMLIMIT lo
|
|
value8 &= 0xf0;
|
|
break;
|
|
case 0x1f: // SSTS hi
|
|
value8 = (pci_conf[0x1f] & ~value8) | 0x02;
|
|
break;
|
|
case 0x3e: // BCTRL
|
|
value8 = (value8 & 0xc1) | 0x80;
|
|
break;
|
|
case 0x19: // SBUSN - all bits r/w
|
|
case 0x1a: // SUBUSN
|
|
case 0x21: // MBASE hi
|
|
case 0x23: // MLIMIT hi
|
|
case 0x25: // PMBASE hi
|
|
case 0x27: // PMLIMIT hi
|
|
break;
|
|
case 0x06: // PCISTS1 - all bits r/o
|
|
case 0x07:
|
|
case 0x18: // PBUSN
|
|
case 0x1e: // SSTS lo
|
|
default:
|
|
value8 = oldval;
|
|
}
|
|
pci_conf[address+i] = value8;
|
|
}
|
|
}
|
|
#endif /* BX_SUPPORT_PCI */
|