cc694377b9
Bochs instruction emulation handlers won't refer to direct fields of instructions like MODRM.NNN or MODRM.RM anymore. Use generic source/destination indications like SRC1, SRC2 and DST. All handlers are modified to support new notation. In addition fetchDecode module was modified to assign sources to instructions properly. Immediate benefits: - Removal of several duplicated handlers (FMA3 duplicated with FMA4 is a trivial example) - Simpler to understand fetch-decode code Future benefits: - Integration of disassembler into Bochs CPU module, ability to disasm bx_instruction_c instance (planned) Huge patch. Almost all source files wre modified.
593 lines
13 KiB
C++
593 lines
13 KiB
C++
/////////////////////////////////////////////////////////////////////////
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// $Id$
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001-2012 The Bochs Project
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA
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/////////////////////////////////////////////////////////////////////////
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#define NEED_CPU_REG_SHORTCUTS 1
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#include "bochs.h"
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#include "cpu.h"
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#define LOG_THIS BX_CPU_THIS_PTR
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#if BX_SUPPORT_X86_64
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SHLD_EqGqM(bxInstruction_c *i)
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{
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Bit64u op1_64, op2_64, result_64;
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unsigned count;
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unsigned cf, of;
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bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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/* pointer, segment address pair */
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op1_64 = read_RMW_virtual_qword_64(i->seg(), eaddr);
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if (i->getIaOpcode() == BX_IA_SHLD_EqGq)
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count = CL;
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else // BX_IA_SHLD_EqGqIb
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count = i->Ib();
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count &= 0x3f; // use only 6 LSB's
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if (count) {
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op2_64 = BX_READ_64BIT_REG(i->src());
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result_64 = (op1_64 << count) | (op2_64 >> (64 - count));
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write_RMW_virtual_qword(result_64);
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SET_FLAGS_OSZAPC_LOGIC_64(result_64);
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cf = (op1_64 >> (64 - count)) & 0x1;
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of = cf ^ (result_64 >> 63); // of = cf ^ result63
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SET_FLAGS_OxxxxC(of, cf);
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}
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SHLD_EqGqR(bxInstruction_c *i)
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{
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Bit64u op1_64, op2_64, result_64;
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unsigned count;
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unsigned cf, of;
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if (i->getIaOpcode() == BX_IA_SHLD_EqGq)
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count = CL;
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else // BX_IA_SHLD_EqGqIb
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count = i->Ib();
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count &= 0x3f; // use only 6 LSB's
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if (count) {
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op1_64 = BX_READ_64BIT_REG(i->dst());
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op2_64 = BX_READ_64BIT_REG(i->src());
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result_64 = (op1_64 << count) | (op2_64 >> (64 - count));
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BX_WRITE_64BIT_REG(i->dst(), result_64);
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SET_FLAGS_OSZAPC_LOGIC_64(result_64);
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cf = (op1_64 >> (64 - count)) & 0x1;
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of = cf ^ (result_64 >> 63); // of = cf ^ result63
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SET_FLAGS_OxxxxC(of, cf);
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}
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SHRD_EqGqM(bxInstruction_c *i)
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{
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Bit64u op1_64, op2_64, result_64;
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unsigned count;
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unsigned cf, of;
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bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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/* pointer, segment address pair */
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op1_64 = read_RMW_virtual_qword_64(i->seg(), eaddr);
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if (i->getIaOpcode() == BX_IA_SHRD_EqGq)
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count = CL;
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else // BX_IA_SHRD_EqGqIb
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count = i->Ib();
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count &= 0x3f; // use only 6 LSB's
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if (count) {
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op2_64 = BX_READ_64BIT_REG(i->src());
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result_64 = (op2_64 << (64 - count)) | (op1_64 >> count);
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write_RMW_virtual_qword(result_64);
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SET_FLAGS_OSZAPC_LOGIC_64(result_64);
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cf = (op1_64 >> (count - 1)) & 0x1;
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of = ((result_64 << 1) ^ result_64) >> 63; // of = result62 ^ result63
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SET_FLAGS_OxxxxC(of, cf);
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}
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SHRD_EqGqR(bxInstruction_c *i)
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{
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Bit64u op1_64, op2_64, result_64;
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unsigned count;
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unsigned cf, of;
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if (i->getIaOpcode() == BX_IA_SHRD_EqGq)
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count = CL;
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else // BX_IA_SHRD_EqGqIb
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count = i->Ib();
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count &= 0x3f; // use only 6 LSB's
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if (count) {
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op1_64 = BX_READ_64BIT_REG(i->dst());
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op2_64 = BX_READ_64BIT_REG(i->src());
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result_64 = (op2_64 << (64 - count)) | (op1_64 >> count);
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BX_WRITE_64BIT_REG(i->dst(), result_64);
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SET_FLAGS_OSZAPC_LOGIC_64(result_64);
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cf = (op1_64 >> (count - 1)) & 0x1;
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of = ((result_64 << 1) ^ result_64) >> 63; // of = result62 ^ result63
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SET_FLAGS_OxxxxC(of, cf);
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}
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ROL_EqM(bxInstruction_c *i)
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{
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unsigned count;
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bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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Bit64u op1_64 = read_RMW_virtual_qword_64(i->seg(), eaddr);
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if (i->getIaOpcode() == BX_IA_ROL_Eq)
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count = CL;
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else
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count = i->Ib();
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count &= 0x3f;
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if (count) {
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Bit64u result_64 = (op1_64 << count) | (op1_64 >> (64 - count));
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write_RMW_virtual_qword(result_64);
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unsigned bit0 = (result_64 & 0x1);
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unsigned bit63 = (result_64 >> 63);
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// of = cf ^ result63
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SET_FLAGS_OxxxxC(bit0 ^ bit63, bit0);
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}
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ROL_EqR(bxInstruction_c *i)
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{
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unsigned count;
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if (i->getIaOpcode() == BX_IA_ROL_Eq)
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count = CL;
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else
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count = i->Ib();
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count &= 0x3f;
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if (count) {
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Bit64u op1_64 = BX_READ_64BIT_REG(i->dst());
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Bit64u result_64 = (op1_64 << count) | (op1_64 >> (64 - count));
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BX_WRITE_64BIT_REG(i->dst(), result_64);
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unsigned bit0 = (result_64 & 0x1);
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unsigned bit63 = (result_64 >> 63);
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// of = cf ^ result63
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SET_FLAGS_OxxxxC(bit0 ^ bit63, bit0);
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}
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ROR_EqM(bxInstruction_c *i)
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{
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unsigned count;
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bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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Bit64u op1_64 = read_RMW_virtual_qword_64(i->seg(), eaddr);
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if (i->getIaOpcode() == BX_IA_ROR_Eq)
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count = CL;
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else
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count = i->Ib();
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count &= 0x3f;
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if (count) {
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Bit64u result_64 = (op1_64 >> count) | (op1_64 << (64 - count));
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write_RMW_virtual_qword(result_64);
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unsigned bit63 = (result_64 >> 63) & 1;
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unsigned bit62 = (result_64 >> 62) & 1;
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// of = result62 ^ result63
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SET_FLAGS_OxxxxC(bit62 ^ bit63, bit63);
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}
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ROR_EqR(bxInstruction_c *i)
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{
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unsigned count;
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if (i->getIaOpcode() == BX_IA_ROR_Eq)
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count = CL;
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else
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count = i->Ib();
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count &= 0x3f;
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if (count) {
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Bit64u op1_64 = BX_READ_64BIT_REG(i->dst());
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Bit64u result_64 = (op1_64 >> count) | (op1_64 << (64 - count));
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BX_WRITE_64BIT_REG(i->dst(), result_64);
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unsigned bit63 = (result_64 >> 63) & 1;
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unsigned bit62 = (result_64 >> 62) & 1;
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// of = result62 ^ result63
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SET_FLAGS_OxxxxC(bit62 ^ bit63, bit63);
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}
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::RCL_EqM(bxInstruction_c *i)
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{
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Bit64u result_64;
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unsigned count;
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unsigned cf, of;
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bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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Bit64u op1_64 = read_RMW_virtual_qword_64(i->seg(), eaddr);
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if (i->getIaOpcode() == BX_IA_RCL_Eq)
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count = CL;
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else
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count = i->Ib();
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count &= 0x3f;
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if (!count) {
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BX_NEXT_INSTR(i);
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}
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if (count==1) {
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result_64 = (op1_64 << 1) | getB_CF();
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}
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else {
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result_64 = (op1_64 << count) | (getB_CF() << (count - 1)) |
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(op1_64 >> (65 - count));
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}
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write_RMW_virtual_qword(result_64);
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cf = (op1_64 >> (64 - count)) & 0x1;
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of = cf ^ (result_64 >> 63); // of = cf ^ result63
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SET_FLAGS_OxxxxC(of, cf);
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::RCL_EqR(bxInstruction_c *i)
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{
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Bit64u result_64;
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unsigned count;
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unsigned cf, of;
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if (i->getIaOpcode() == BX_IA_RCL_Eq)
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count = CL;
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else
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count = i->Ib();
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count &= 0x3f;
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if (!count) {
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BX_NEXT_INSTR(i);
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}
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Bit64u op1_64 = BX_READ_64BIT_REG(i->dst());
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if (count==1) {
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result_64 = (op1_64 << 1) | getB_CF();
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}
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else {
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result_64 = (op1_64 << count) | (getB_CF() << (count - 1)) |
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(op1_64 >> (65 - count));
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}
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BX_WRITE_64BIT_REG(i->dst(), result_64);
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cf = (op1_64 >> (64 - count)) & 0x1;
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of = cf ^ (result_64 >> 63); // of = cf ^ result63
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SET_FLAGS_OxxxxC(of, cf);
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::RCR_EqM(bxInstruction_c *i)
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{
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Bit64u result_64;
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unsigned count;
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unsigned of, cf;
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bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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Bit64u op1_64 = read_RMW_virtual_qword_64(i->seg(), eaddr);
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if (i->getIaOpcode() == BX_IA_RCR_Eq)
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count = CL;
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else
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count = i->Ib();
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count &= 0x3f;
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if (!count) {
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BX_NEXT_INSTR(i);
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}
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if (count==1) {
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result_64 = (op1_64 >> 1) | (((Bit64u) getB_CF()) << 63);
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}
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else {
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result_64 = (op1_64 >> count) | (getB_CF() << (64 - count)) |
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(op1_64 << (65 - count));
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}
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write_RMW_virtual_qword(result_64);
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cf = (op1_64 >> (count - 1)) & 0x1;
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of = ((result_64 << 1) ^ result_64) >> 63;
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SET_FLAGS_OxxxxC(of, cf);
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::RCR_EqR(bxInstruction_c *i)
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{
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Bit64u result_64;
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unsigned count;
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unsigned of, cf;
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if (i->getIaOpcode() == BX_IA_RCR_Eq)
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count = CL;
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else
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count = i->Ib();
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count &= 0x3f;
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if (!count) {
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BX_NEXT_INSTR(i);
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}
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Bit64u op1_64 = BX_READ_64BIT_REG(i->dst());
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if (count==1) {
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result_64 = (op1_64 >> 1) | (((Bit64u) getB_CF()) << 63);
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}
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else {
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result_64 = (op1_64 >> count) | (getB_CF() << (64 - count)) |
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(op1_64 << (65 - count));
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}
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BX_WRITE_64BIT_REG(i->dst(), result_64);
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cf = (op1_64 >> (count - 1)) & 0x1;
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of = ((result_64 << 1) ^ result_64) >> 63;
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SET_FLAGS_OxxxxC(of, cf);
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SHL_EqM(bxInstruction_c *i)
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{
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unsigned count;
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bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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Bit64u op1_64 = read_RMW_virtual_qword_64(i->seg(), eaddr);
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if (i->getIaOpcode() == BX_IA_SHL_Eq)
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count = CL;
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else
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count = i->Ib();
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count &= 0x3f;
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if (count) {
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/* count < 64, since only lower 6 bits used */
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Bit64u result_64 = (op1_64 << count);
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unsigned cf = (op1_64 >> (64 - count)) & 0x1;
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unsigned of = cf ^ (result_64 >> 63);
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write_RMW_virtual_qword(result_64);
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SET_FLAGS_OSZAPC_LOGIC_64(result_64);
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SET_FLAGS_OxxxxC(of, cf);
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}
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SHL_EqR(bxInstruction_c *i)
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{
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Bit64u op1_64, result_64;
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unsigned count;
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unsigned cf, of;
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if (i->getIaOpcode() == BX_IA_SHL_Eq)
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count = CL;
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else
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count = i->Ib();
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count &= 0x3f;
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if (count) {
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op1_64 = BX_READ_64BIT_REG(i->dst());
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/* count < 64, since only lower 6 bits used */
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result_64 = (op1_64 << count);
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BX_WRITE_64BIT_REG(i->dst(), result_64);
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cf = (op1_64 >> (64 - count)) & 0x1;
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of = cf ^ (result_64 >> 63);
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SET_FLAGS_OSZAPC_LOGIC_64(result_64);
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SET_FLAGS_OxxxxC(of, cf);
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}
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SHR_EqM(bxInstruction_c *i)
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{
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unsigned count;
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bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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Bit64u op1_64 = read_RMW_virtual_qword_64(i->seg(), eaddr);
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if (i->getIaOpcode() == BX_IA_SHR_Eq)
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count = CL;
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else
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count = i->Ib();
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count &= 0x3f;
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if (count) {
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Bit64u result_64 = (op1_64 >> count);
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write_RMW_virtual_qword(result_64);
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unsigned cf = (op1_64 >> (count - 1)) & 0x1;
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// note, that of == result63 if count == 1 and
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// of == 0 if count >= 2
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unsigned of = ((result_64 << 1) ^ result_64) >> 63;
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SET_FLAGS_OSZAPC_LOGIC_64(result_64);
|
|
SET_FLAGS_OxxxxC(of, cf);
|
|
}
|
|
|
|
BX_NEXT_INSTR(i);
|
|
}
|
|
|
|
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SHR_EqR(bxInstruction_c *i)
|
|
{
|
|
unsigned count;
|
|
|
|
if (i->getIaOpcode() == BX_IA_SHR_Eq)
|
|
count = CL;
|
|
else
|
|
count = i->Ib();
|
|
|
|
count &= 0x3f;
|
|
|
|
if (count) {
|
|
Bit64u op1_64 = BX_READ_64BIT_REG(i->dst());
|
|
Bit64u result_64 = (op1_64 >> count);
|
|
BX_WRITE_64BIT_REG(i->dst(), result_64);
|
|
|
|
unsigned cf = (op1_64 >> (count - 1)) & 0x1;
|
|
// note, that of == result63 if count == 1 and
|
|
// of == 0 if count >= 2
|
|
unsigned of = ((result_64 << 1) ^ result_64) >> 63;
|
|
|
|
SET_FLAGS_OSZAPC_LOGIC_64(result_64);
|
|
SET_FLAGS_OxxxxC(of, cf);
|
|
}
|
|
|
|
BX_NEXT_INSTR(i);
|
|
}
|
|
|
|
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SAR_EqM(bxInstruction_c *i)
|
|
{
|
|
unsigned count;
|
|
|
|
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
|
|
|
Bit64u op1_64 = read_RMW_virtual_qword_64(i->seg(), eaddr);
|
|
|
|
if (i->getIaOpcode() == BX_IA_SAR_Eq)
|
|
count = CL;
|
|
else
|
|
count = i->Ib();
|
|
|
|
count &= 0x3f;
|
|
|
|
if (count) {
|
|
/* count < 64, since only lower 6 bits used */
|
|
Bit64u result_64 = ((Bit64s) op1_64) >> count;
|
|
|
|
write_RMW_virtual_qword(result_64);
|
|
|
|
SET_FLAGS_OSZAPC_LOGIC_64(result_64);
|
|
unsigned cf = (op1_64 >> (count - 1)) & 1;
|
|
SET_FLAGS_OxxxxC(0, cf); /* signed overflow cannot happen in SAR instruction */
|
|
}
|
|
|
|
BX_NEXT_INSTR(i);
|
|
}
|
|
|
|
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SAR_EqR(bxInstruction_c *i)
|
|
{
|
|
unsigned count;
|
|
|
|
if (i->getIaOpcode() == BX_IA_SAR_Eq)
|
|
count = CL;
|
|
else
|
|
count = i->Ib();
|
|
|
|
count &= 0x3f;
|
|
|
|
if (count) {
|
|
Bit64u op1_64 = BX_READ_64BIT_REG(i->dst());
|
|
|
|
/* count < 64, since only lower 6 bits used */
|
|
Bit64u result_64 = ((Bit64s) op1_64) >> count;
|
|
|
|
BX_WRITE_64BIT_REG(i->dst(), result_64);
|
|
|
|
SET_FLAGS_OSZAPC_LOGIC_64(result_64);
|
|
unsigned cf = (op1_64 >> (count - 1)) & 1;
|
|
SET_FLAGS_OxxxxC(0, cf); /* signed overflow cannot happen in SAR instruction */
|
|
}
|
|
|
|
BX_NEXT_INSTR(i);
|
|
}
|
|
|
|
#endif /* if BX_SUPPORT_X86_64 */
|