mirrors/Bochs
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
d082c6a0f9
Bochs/bochs/cpu/logical64.cc
Stanislav Shwartsman cc694377b9 Standartization of Bochs instruction handlers. 
Bochs instruction emulation handlers won't refer to direct fields of instructions like MODRM.NNN or MODRM.RM anymore.
Use generic source/destination indications like SRC1, SRC2 and DST.
All handlers are modified to support new notation. In addition fetchDecode module was modified to assign sources to instructions properly.

Immediate benefits:
- Removal of several duplicated handlers (FMA3 duplicated with FMA4 is a trivial example)
- Simpler to understand fetch-decode code

Future benefits:
- Integration of disassembler into Bochs CPU module, ability to disasm bx_instruction_c instance (planned)

Huge patch. Almost all source files wre modified.
2012-08-05 13:52:40 +00:00

334 lines
7.8 KiB
C++
Raw Blame History

/////////////////////////////////////////////////////////////////////////
// $Id$
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001-2012 The Bochs Project
//
// This library is free software; you can redistribute it and/or
// modify it under the terms of the GNU Lesser General Public
// License as published by the Free Software Foundation; either
// version 2 of the License, or (at your option) any later version.
//
// This library is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// Lesser General Public License for more details.
//
// You should have received a copy of the GNU Lesser General Public
// License along with this library; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA
/////////////////////////////////////////////////////////////////////////
#define NEED_CPU_REG_SHORTCUTS 1
#include "bochs.h"
#include "cpu.h"
#define LOG_THIS BX_CPU_THIS_PTR
#if BX_SUPPORT_X86_64
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::XOR_EqGqM(bxInstruction_c *i)
{
Bit64u op1_64, op2_64;
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
op1_64 = read_RMW_virtual_qword_64(i->seg(), eaddr);
op2_64 = BX_READ_64BIT_REG(i->src());
op1_64 ^= op2_64;
write_RMW_virtual_qword(op1_64);
SET_FLAGS_OSZAPC_LOGIC_64(op1_64);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::XOR_GqEqR(bxInstruction_c *i)
{
Bit64u op1_64, op2_64;
op1_64 = BX_READ_64BIT_REG(i->dst());
op2_64 = BX_READ_64BIT_REG(i->src());
op1_64 ^= op2_64;
BX_WRITE_64BIT_REG(i->dst(), op1_64);
SET_FLAGS_OSZAPC_LOGIC_64(op1_64);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::XOR_GqEqM(bxInstruction_c *i)
{
Bit64u op1_64, op2_64;
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
op1_64 = BX_READ_64BIT_REG(i->dst());
op2_64 = read_virtual_qword_64(i->seg(), eaddr);
op1_64 ^= op2_64;
BX_WRITE_64BIT_REG(i->dst(), op1_64);
SET_FLAGS_OSZAPC_LOGIC_64(op1_64);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::XOR_EqIdM(bxInstruction_c *i)
{
Bit64u op1_64, op2_64 = (Bit32s) i->Id();
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
op1_64 = read_RMW_virtual_qword_64(i->seg(), eaddr);
op1_64 ^= op2_64;
write_RMW_virtual_qword(op1_64);
SET_FLAGS_OSZAPC_LOGIC_64(op1_64);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::XOR_EqIdR(bxInstruction_c *i)
{
Bit64u op1_64, op2_64 = (Bit32s) i->Id();
op1_64 = BX_READ_64BIT_REG(i->dst());
op1_64 ^= op2_64;
BX_WRITE_64BIT_REG(i->dst(), op1_64);
SET_FLAGS_OSZAPC_LOGIC_64(op1_64);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::OR_EqIdM(bxInstruction_c *i)
{
Bit64u op1_64, op2_64 = (Bit32s) i->Id();
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
op1_64 = read_RMW_virtual_qword_64(i->seg(), eaddr);
op1_64 |= op2_64;
write_RMW_virtual_qword(op1_64);
SET_FLAGS_OSZAPC_LOGIC_64(op1_64);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::OR_EqIdR(bxInstruction_c *i)
{
Bit64u op1_64, op2_64 = (Bit32s) i->Id();
op1_64 = BX_READ_64BIT_REG(i->dst());
op1_64 |= op2_64;
BX_WRITE_64BIT_REG(i->dst(), op1_64);
SET_FLAGS_OSZAPC_LOGIC_64(op1_64);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::NOT_EqM(bxInstruction_c *i)
{
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
Bit64u op1_64 = read_RMW_virtual_qword_64(i->seg(), eaddr);
op1_64 = ~op1_64;
write_RMW_virtual_qword(op1_64);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::NOT_EqR(bxInstruction_c *i)
{
Bit64u op1_64 = BX_READ_64BIT_REG(i->dst());
op1_64 = ~op1_64;
BX_WRITE_64BIT_REG(i->dst(), op1_64);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::OR_EqGqM(bxInstruction_c *i)
{
Bit64u op1_64, op2_64;
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
op1_64 = read_RMW_virtual_qword_64(i->seg(), eaddr);
op2_64 = BX_READ_64BIT_REG(i->src());
op1_64 |= op2_64;
write_RMW_virtual_qword(op1_64);
SET_FLAGS_OSZAPC_LOGIC_64(op1_64);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::OR_GqEqR(bxInstruction_c *i)
{
Bit64u op1_64, op2_64;
op1_64 = BX_READ_64BIT_REG(i->dst());
op2_64 = BX_READ_64BIT_REG(i->src());
op1_64 |= op2_64;
BX_WRITE_64BIT_REG(i->dst(), op1_64);
SET_FLAGS_OSZAPC_LOGIC_64(op1_64);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::OR_GqEqM(bxInstruction_c *i)
{
Bit64u op1_64, op2_64;
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
op1_64 = BX_READ_64BIT_REG(i->dst());
op2_64 = read_virtual_qword_64(i->seg(), eaddr);
op1_64 |= op2_64;
BX_WRITE_64BIT_REG(i->dst(), op1_64);
SET_FLAGS_OSZAPC_LOGIC_64(op1_64);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::AND_EqGqM(bxInstruction_c *i)
{
Bit64u op1_64, op2_64;
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
op1_64 = read_RMW_virtual_qword_64(i->seg(), eaddr);
op2_64 = BX_READ_64BIT_REG(i->src());
op1_64 &= op2_64;
write_RMW_virtual_qword(op1_64);
SET_FLAGS_OSZAPC_LOGIC_64(op1_64);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::AND_GqEqR(bxInstruction_c *i)
{
Bit64u op1_64, op2_64;
op1_64 = BX_READ_64BIT_REG(i->dst());
op2_64 = BX_READ_64BIT_REG(i->src());
op1_64 &= op2_64;
BX_WRITE_64BIT_REG(i->dst(), op1_64);
SET_FLAGS_OSZAPC_LOGIC_64(op1_64);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::AND_GqEqM(bxInstruction_c *i)
{
Bit64u op1_64, op2_64;
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
op1_64 = BX_READ_64BIT_REG(i->dst());
op2_64 = read_virtual_qword_64(i->seg(), eaddr);
op1_64 &= op2_64;
BX_WRITE_64BIT_REG(i->dst(), op1_64);
SET_FLAGS_OSZAPC_LOGIC_64(op1_64);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::AND_EqIdM(bxInstruction_c *i)
{
Bit64u op1_64, op2_64 = (Bit32s) i->Id();
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
op1_64 = read_RMW_virtual_qword_64(i->seg(), eaddr);
op1_64 &= op2_64;
write_RMW_virtual_qword(op1_64);
SET_FLAGS_OSZAPC_LOGIC_64(op1_64);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::AND_EqIdR(bxInstruction_c *i)
{
Bit64u op1_64, op2_64 = (Bit32s) i->Id();
op1_64 = BX_READ_64BIT_REG(i->dst());
op1_64 &= op2_64;
BX_WRITE_64BIT_REG(i->dst(), op1_64);
SET_FLAGS_OSZAPC_LOGIC_64(op1_64);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::TEST_EqGqR(bxInstruction_c *i)
{
Bit64u op1_64, op2_64;
op1_64 = BX_READ_64BIT_REG(i->dst());
op2_64 = BX_READ_64BIT_REG(i->src());
op1_64 &= op2_64;
SET_FLAGS_OSZAPC_LOGIC_64(op1_64);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::TEST_EqGqM(bxInstruction_c *i)
{
Bit64u op1_64, op2_64;
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
op1_64 = read_virtual_qword_64(i->seg(), eaddr);
op2_64 = BX_READ_64BIT_REG(i->src());
op1_64 &= op2_64;
SET_FLAGS_OSZAPC_LOGIC_64(op1_64);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::TEST_EqIdR(bxInstruction_c *i)
{
Bit64u op1_64, op2_64;
op1_64 = BX_READ_64BIT_REG(i->dst());
op2_64 = (Bit32s) i->Id();
op1_64 &= op2_64;
SET_FLAGS_OSZAPC_LOGIC_64(op1_64);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::TEST_EqIdM(bxInstruction_c *i)
{
Bit64u op1_64, op2_64;
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
op1_64 = read_virtual_qword_64(i->seg(), eaddr);
op2_64 = (Bit32s) i->Id();
op1_64 &= op2_64;
SET_FLAGS_OSZAPC_LOGIC_64(op1_64);
BX_NEXT_INSTR(i);
}
#endif /* if BX_SUPPORT_X86_64 */
Reference in New Issue View Git Blame Copy Permalink