cc694377b9
Bochs instruction emulation handlers won't refer to direct fields of instructions like MODRM.NNN or MODRM.RM anymore. Use generic source/destination indications like SRC1, SRC2 and DST. All handlers are modified to support new notation. In addition fetchDecode module was modified to assign sources to instructions properly. Immediate benefits: - Removal of several duplicated handlers (FMA3 duplicated with FMA4 is a trivial example) - Simpler to understand fetch-decode code Future benefits: - Integration of disassembler into Bochs CPU module, ability to disasm bx_instruction_c instance (planned) Huge patch. Almost all source files wre modified.
149 lines
4.2 KiB
C++
149 lines
4.2 KiB
C++
/////////////////////////////////////////////////////////////////////////
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// $Id$
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (c) 2008-2012 Stanislav Shwartsman
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// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA
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//
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/////////////////////////////////////////////////////////////////////////
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#define NEED_CPU_REG_SHORTCUTS 1
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#include "bochs.h"
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#include "cpu.h"
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#define LOG_THIS BX_CPU_THIS_PTR
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#if BX_CPU_LEVEL >= 6
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// 3-byte opcodes
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#define CRC32_POLYNOMIAL BX_CONST64(0x11edc6f41)
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// primitives for CRC32 usage
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BX_CPP_INLINE Bit8u BitReflect8(Bit8u val8)
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{
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return ((val8 & 0x80) >> 7) |
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((val8 & 0x40) >> 5) |
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((val8 & 0x20) >> 3) |
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((val8 & 0x10) >> 1) |
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((val8 & 0x08) << 1) |
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((val8 & 0x04) << 3) |
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((val8 & 0x02) << 5) |
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((val8 & 0x01) << 7);
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}
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BX_CPP_INLINE Bit16u BitReflect16(Bit16u val16)
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{
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return ((Bit16u)(BitReflect8(val16 & 0xff)) << 8) | BitReflect8(val16 >> 8);
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}
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BX_CPP_INLINE Bit32u BitReflect32(Bit32u val32)
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{
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return ((Bit32u)(BitReflect16(val32 & 0xffff)) << 16) | BitReflect16(val32 >> 16);
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}
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static Bit32u mod2_64bit(Bit64u divisor, Bit64u dividend)
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{
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Bit64u remainder = dividend >> 32;
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for (int bitpos=31; bitpos>=0; bitpos--) {
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// copy one more bit from the dividend
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remainder = (remainder << 1) | ((dividend >> bitpos) & 1);
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// if MSB is set, then XOR divisor and get new remainder
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if (((remainder >> 32) & 1) == 1) {
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remainder ^= divisor;
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}
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}
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return (Bit32u) remainder;
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CRC32_GdEbR(bxInstruction_c *i)
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{
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Bit8u op1 = BX_READ_8BIT_REGx(i->src(), i->extend8bitL());
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Bit32u op2 = BX_READ_32BIT_REG(i->dst());
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op2 = BitReflect32(op2);
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Bit64u tmp1 = ((Bit64u) BitReflect8 (op1)) << 32;
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Bit64u tmp2 = ((Bit64u) op2) << 8;
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Bit64u tmp3 = tmp1 ^ tmp2;
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op2 = mod2_64bit(CRC32_POLYNOMIAL, tmp3);
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BX_WRITE_32BIT_REGZ(i->dst(), BitReflect32(op2));
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CRC32_GdEwR(bxInstruction_c *i)
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{
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Bit32u op2 = BX_READ_32BIT_REG(i->dst());
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op2 = BitReflect32(op2);
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Bit16u op1 = BX_READ_16BIT_REG(i->src());
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Bit64u tmp1 = ((Bit64u) BitReflect16(op1)) << 32;
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Bit64u tmp2 = ((Bit64u) op2) << 16;
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Bit64u tmp3 = tmp1 ^ tmp2;
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op2 = mod2_64bit(CRC32_POLYNOMIAL, tmp3);
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BX_WRITE_32BIT_REGZ(i->dst(), BitReflect32(op2));
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CRC32_GdEdR(bxInstruction_c *i)
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{
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Bit32u op2 = BX_READ_32BIT_REG(i->dst());
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op2 = BitReflect32(op2);
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Bit32u op1 = BX_READ_32BIT_REG(i->src());
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Bit64u tmp1 = ((Bit64u) BitReflect32(op1)) << 32;
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Bit64u tmp2 = ((Bit64u) op2) << 32;
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Bit64u tmp3 = tmp1 ^ tmp2;
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op2 = mod2_64bit(CRC32_POLYNOMIAL, tmp3);
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BX_WRITE_32BIT_REGZ(i->dst(), BitReflect32(op2));
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BX_NEXT_INSTR(i);
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}
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#if BX_SUPPORT_X86_64
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CRC32_GdEqR(bxInstruction_c *i)
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{
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Bit32u op2 = BX_READ_32BIT_REG(i->dst());
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op2 = BitReflect32(op2);
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Bit64u op1 = BX_READ_64BIT_REG(i->src());
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Bit64u tmp1 = ((Bit64u) BitReflect32(op1 & 0xffffffff)) << 32;
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Bit64u tmp2 = ((Bit64u) op2) << 32;
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Bit64u tmp3 = tmp1 ^ tmp2;
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op2 = mod2_64bit(CRC32_POLYNOMIAL, tmp3);
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tmp1 = ((Bit64u) BitReflect32(op1 >> 32)) << 32;
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tmp2 = ((Bit64u) op2) << 32;
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tmp3 = tmp1 ^ tmp2;
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op2 = mod2_64bit(CRC32_POLYNOMIAL, tmp3);
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BX_WRITE_32BIT_REGZ(i->dst(), BitReflect32(op2));
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BX_NEXT_INSTR(i);
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}
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#endif // BX_SUPPORT_X86_64
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#endif // BX_CPU_LEVEL >= 6
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