b37ae8a969
fixed print prefixes in disasm -> only LOCK, REP and REPNE prefixes printed update changes
240 lines
7.1 KiB
C++
240 lines
7.1 KiB
C++
#include <stdio.h>
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#include <stdarg.h>
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#include <string.h>
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#include "disasm.h"
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#include "dis_tables.h"
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/* ******************** */
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// INSTRUCTION PREFIXES //
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/* ******************** */
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static const unsigned char instruction_has_modrm[512] = {
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/* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
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/* ------------------------------- */
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/* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0,
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/* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0,
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/* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0,
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/* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0,
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/* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
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/* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
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/* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0,
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/* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
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/* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,
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/* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
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/* A0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
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/* B0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
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/* C0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0,
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/* D0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1,
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/* E0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
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/* F0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1,
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/* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
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/* ------------------------------- */
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1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0F 00 */
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1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0, /* 0F 10 */
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1,1,1,1,1,0,1,0,1,1,1,1,1,1,1,1, /* 0F 20 */
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0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 0F 30 */
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1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 0F 40 */
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1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 0F 50 */
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1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 0F 60 */
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1,1,1,1,1,1,1,0,0,0,0,0,0,0,1,1, /* 0F 70 */
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0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 0F 80 */
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1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 0F 90 */
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0,0,0,1,1,1,0,0,0,0,0,1,1,1,1,1, /* 0F A0 */
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1,1,1,1,1,1,1,1,0,0,1,1,1,1,1,1, /* 0F B0 */
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1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* 0F C0 */
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0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 0F D0 */
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1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 0F E0 */
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0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* 0F F0 */
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/* ------------------------------- */
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/* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
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};
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/*
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* Group 1:
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*
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* F0h - LOCK
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* F2h - REPNE/REPZ (used only with string instructions)
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* F3h - REP or REPE/REPZ (used only with string instructions)
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*
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* Group 2 :
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*
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* - segment override prefixes
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* 2Eh - CS segment override
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* 36h - SS segment override
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* 3Eh - DS segment override
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* 26h - ES segment override
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* 64h - FS segment override
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* 65h - GS segment override
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*
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* - branch hints
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* 2Eh - branch not taken (branch hint for Jcc instructions only)
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* 3Eh - branch taken (branch hint for Jcc instructions only)
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*
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* Group 3:
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*
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* 66h - operand size override prefix
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* 67h - address size override prefix
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*
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* For each instruction, one prefix may be used from each of these groups
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* and be placed in any order. Using redundant prefixes (more than one
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* prefix from a group) is reserved and will cause undefined behaviour.
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*/
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unsigned disassembler::disasm(bx_bool is_32,
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Bit32u base, Bit32u ip, Bit8u *instr, char *disbuf)
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{
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i32bit_opsize = is_32;
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i32bit_addrsize = is_32;
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db_eip = ip;
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db_base = base; // cs linear base (base for PM & cs<<4 for RM & VM)
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instruction_begin = instruction = instr;
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displacement.displ32 = 0;
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resolve_modrm = NULL;
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seg_override = NULL;
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n_prefixes = 0;
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disbufptr = disbuf; // start sprintf()'ing into beginning of buffer
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#define SSE_PREFIX_NONE 0
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#define SSE_PREFIX_66 1
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#define SSE_PREFIX_F2 2
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#define SSE_PREFIX_F3 4 /* only one SSE prefix could be used */
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static int sse_prefix_index[8] = { 0, 1, 2, -1, 3, -1, -1, -1 };
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unsigned sse_prefix = SSE_PREFIX_NONE;
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int b1;
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const BxDisasmOpcodeInfo_t *entry;
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for(;;)
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{
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b1 = fetch_byte();
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entry = &BxDisasmOpcodes[b1];
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if (entry->Attr == _PREFIX)
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{
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switch(b1) {
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case 0xf3:
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sse_prefix |= SSE_PREFIX_F3;
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break;
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case 0xf2:
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sse_prefix |= SSE_PREFIX_F2;
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break;
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case 0x2e:
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case 0x36:
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case 0x3e:
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case 0x26:
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case 0x64:
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case 0x65:
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seg_override = entry->Opcode;
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break;
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case 0x66:
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i32bit_opsize = !i32bit_opsize;
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sse_prefix |= SSE_PREFIX_66;
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break;
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case 0x67:
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i32bit_addrsize = !i32bit_addrsize;
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break;
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case 0xf0: // lock
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break;
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default:
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printf("Internal disassembler error !");
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return 0;
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}
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n_prefixes++;
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}
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else break;
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}
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if (b1 == 0x0f)
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{
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b1 = 0x100 | fetch_byte();
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entry = &BxDisasmOpcodes[b1];
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}
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if (instruction_has_modrm[b1])
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decode_modrm();
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int attr = entry->Attr;
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while(attr)
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{
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switch(attr) {
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case _GROUPN:
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entry = &(entry->AnotherArray[nnn]);
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break;
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case _GRPSSE:
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{
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if(sse_prefix) n_prefixes--;
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/* For SSE opcodes, look into another 4 entries table
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with the opcode prefixes (NONE, 0x66, 0xF2, 0xF3) */
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int op = sse_prefix_index[sse_prefix];
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if (op < 0) return 0;
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entry = &(entry->AnotherArray[op]);
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}
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break;
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case _SPLIT11B:
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entry = &(entry->AnotherArray[mod==3]);
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break;
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case _GRPFP:
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if(mod != 3)
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{
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entry = &(entry->AnotherArray[nnn]);
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}
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else
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{
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int index = (b1-0xD8)*64 + (0x3f & modrm);
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entry = &(BxDisasmOpcodeInfoFP[index]);
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}
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break;
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case _GRP3DNOW:
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{
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int suffix = peek_byte();
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entry = &(BxDisasm3DNowGroup[suffix]);
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}
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break;
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default:
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printf("Internal disassembler error !");
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return 0;
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}
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/* get additional attributes from group table */
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attr = entry->Attr;
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}
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// print prefixes
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for(unsigned i=0;i<n_prefixes;i++)
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if (*(instr+i) == 0xF3 || *(instr+i) == 0xF2 || *(instr+i) == 0xF0)
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dis_sprintf("%s ", BxDisasmOpcodes[*(instr+i)].Opcode);
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// print opcode
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dis_sprintf("%s ", entry->Opcode);
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(this->*entry->Operand1)(entry->Op1Attr);
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if (entry->Operand2 != &disassembler::XX)
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dis_sprintf(", ");
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(this->*entry->Operand2)(entry->Op2Attr);
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if (entry->Operand3 != &disassembler::XX)
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dis_sprintf(", ");
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(this->*entry->Operand3)(entry->Op3Attr);
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return(instruction - instruction_begin);
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}
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void disassembler::dis_sprintf(char *fmt, ...)
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{
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va_list ap;
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va_start(ap, fmt);
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vsprintf(disbufptr, fmt, ap);
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va_end(ap);
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disbufptr += strlen(disbufptr);
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}
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