cc694377b9
Bochs instruction emulation handlers won't refer to direct fields of instructions like MODRM.NNN or MODRM.RM anymore. Use generic source/destination indications like SRC1, SRC2 and DST. All handlers are modified to support new notation. In addition fetchDecode module was modified to assign sources to instructions properly. Immediate benefits: - Removal of several duplicated handlers (FMA3 duplicated with FMA4 is a trivial example) - Simpler to understand fetch-decode code Future benefits: - Integration of disassembler into Bochs CPU module, ability to disasm bx_instruction_c instance (planned) Huge patch. Almost all source files wre modified.
495 lines
16 KiB
C++
495 lines
16 KiB
C++
/////////////////////////////////////////////////////////////////////////
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// $Id$
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (c) 2011-2012 Stanislav Shwartsman
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// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA
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//
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/////////////////////////////////////////////////////////////////////////
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#define NEED_CPU_REG_SHORTCUTS 1
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#include "bochs.h"
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#include "cpu.h"
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#define LOG_THIS BX_CPU_THIS_PTR
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#if BX_SUPPORT_AVX
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extern void mxcsr_to_softfloat_status_word(float_status_t &status, bx_mxcsr_t mxcsr);
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#include "simd_pfp.h"
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//////////////////////////
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// AVX FMA Instructions //
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//////////////////////////
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// FMADDPD
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VFMADDPD_VpdHpdWpdR(bxInstruction_c *i)
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{
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BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->src1());
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BxPackedAvxRegister op2 = BX_READ_AVX_REG(i->src2());
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BxPackedAvxRegister op3 = BX_READ_AVX_REG(i->src3());
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unsigned len = i->getVL();
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float_status_t status;
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mxcsr_to_softfloat_status_word(status, MXCSR);
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for (unsigned n=0; n < len; n++)
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fmaddpd(&op1.avx128(n), &op2.avx128(n), &op3.avx128(n), status);
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check_exceptionsSSE(status.float_exception_flags);
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BX_WRITE_AVX_REGZ(i->dst(), op1, len);
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BX_NEXT_INSTR(i);
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}
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// FMADDPS
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VFMADDPS_VpsHpsWpsR(bxInstruction_c *i)
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{
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BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->src1());
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BxPackedAvxRegister op2 = BX_READ_AVX_REG(i->src2());
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BxPackedAvxRegister op3 = BX_READ_AVX_REG(i->src3());
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unsigned len = i->getVL();
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float_status_t status;
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mxcsr_to_softfloat_status_word(status, MXCSR);
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for (unsigned n=0; n < len; n++)
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fmaddps(&op1.avx128(n), &op2.avx128(n), &op3.avx128(n), status);
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check_exceptionsSSE(status.float_exception_flags);
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BX_WRITE_AVX_REGZ(i->dst(), op1, len);
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BX_NEXT_INSTR(i);
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}
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// FMADDSD
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VFMADDSD_VpdHsdWsdR(bxInstruction_c *i)
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{
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float64 op1 = BX_READ_XMM_REG_LO_QWORD(i->src1());
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float64 op2 = BX_READ_XMM_REG_LO_QWORD(i->src2());
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float64 op3 = BX_READ_XMM_REG_LO_QWORD(i->src3());
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float_status_t status;
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mxcsr_to_softfloat_status_word(status, MXCSR);
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op1 = float64_muladd(op1, op2, op3, 0, status);
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check_exceptionsSSE(status.float_exception_flags);
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BX_WRITE_XMM_REG_LO_QWORD(i->dst(), op1);
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BX_CLEAR_AVX_HIGH(i->dst());
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BX_NEXT_INSTR(i);
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}
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// FMADDSS
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VFMADDSS_VpsHssWssR(bxInstruction_c *i)
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{
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float32 op1 = BX_READ_XMM_REG_LO_DWORD(i->src1());
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float32 op2 = BX_READ_XMM_REG_LO_DWORD(i->src2());
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float32 op3 = BX_READ_XMM_REG_LO_DWORD(i->src3());
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float_status_t status;
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mxcsr_to_softfloat_status_word(status, MXCSR);
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op1 = float32_muladd(op1, op2, op3, 0, status);
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check_exceptionsSSE(status.float_exception_flags);
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BX_WRITE_XMM_REG_LO_DWORD(i->dst(), op1);
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BX_CLEAR_AVX_HIGH(i->dst());
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BX_NEXT_INSTR(i);
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}
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// FMADDSUBPD
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VFMADDSUBPD_VpdHpdWpdR(bxInstruction_c *i)
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{
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BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->src1());
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BxPackedAvxRegister op2 = BX_READ_AVX_REG(i->src2());
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BxPackedAvxRegister op3 = BX_READ_AVX_REG(i->src3());
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unsigned len = i->getVL();
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float_status_t status;
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mxcsr_to_softfloat_status_word(status, MXCSR);
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for (unsigned n=0; n < len; n++)
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fmaddsubpd(&op1.avx128(n), &op2.avx128(n), &op3.avx128(n), status);
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check_exceptionsSSE(status.float_exception_flags);
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BX_WRITE_AVX_REGZ(i->dst(), op1, len);
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BX_NEXT_INSTR(i);
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}
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// FMADDSUBPS
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VFMADDSUBPS_VpsHpsWpsR(bxInstruction_c *i)
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{
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BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->src1());
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BxPackedAvxRegister op2 = BX_READ_AVX_REG(i->src2());
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BxPackedAvxRegister op3 = BX_READ_AVX_REG(i->src3());
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unsigned len = i->getVL();
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float_status_t status;
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mxcsr_to_softfloat_status_word(status, MXCSR);
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for (unsigned n=0; n < len; n++)
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fmaddsubps(&op1.avx128(n), &op2.avx128(n), &op3.avx128(n), status);
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check_exceptionsSSE(status.float_exception_flags);
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BX_WRITE_AVX_REGZ(i->dst(), op1, len);
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BX_NEXT_INSTR(i);
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}
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// FMSUBADDPD
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VFMSUBADDPD_VpdHpdWpdR(bxInstruction_c *i)
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{
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BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->src1());
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BxPackedAvxRegister op2 = BX_READ_AVX_REG(i->src2());
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BxPackedAvxRegister op3 = BX_READ_AVX_REG(i->src3());
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unsigned len = i->getVL();
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float_status_t status;
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mxcsr_to_softfloat_status_word(status, MXCSR);
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for (unsigned n=0; n < len; n++)
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fmsubaddpd(&op1.avx128(n), &op2.avx128(n), &op3.avx128(n), status);
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check_exceptionsSSE(status.float_exception_flags);
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BX_WRITE_AVX_REGZ(i->dst(), op1, len);
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BX_NEXT_INSTR(i);
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}
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// FMSUBADDPS
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VFMSUBADDPS_VpsHpsWpsR(bxInstruction_c *i)
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{
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BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->src1());
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BxPackedAvxRegister op2 = BX_READ_AVX_REG(i->src2());
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BxPackedAvxRegister op3 = BX_READ_AVX_REG(i->src3());
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unsigned len = i->getVL();
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float_status_t status;
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mxcsr_to_softfloat_status_word(status, MXCSR);
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for (unsigned n=0; n < len; n++)
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fmsubaddps(&op1.avx128(n), &op2.avx128(n), &op3.avx128(n), status);
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check_exceptionsSSE(status.float_exception_flags);
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BX_WRITE_AVX_REGZ(i->dst(), op1, len);
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BX_NEXT_INSTR(i);
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}
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// FMSUBPD
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VFMSUBPD_VpdHpdWpdR(bxInstruction_c *i)
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{
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BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->src1());
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BxPackedAvxRegister op2 = BX_READ_AVX_REG(i->src2());
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BxPackedAvxRegister op3 = BX_READ_AVX_REG(i->src3());
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unsigned len = i->getVL();
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float_status_t status;
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mxcsr_to_softfloat_status_word(status, MXCSR);
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for (unsigned n=0; n < len; n++)
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fmsubpd(&op1.avx128(n), &op2.avx128(n), &op3.avx128(n), status);
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check_exceptionsSSE(status.float_exception_flags);
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BX_WRITE_AVX_REGZ(i->dst(), op1, len);
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BX_NEXT_INSTR(i);
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}
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// FMSUBPS
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VFMSUBPS_VpsHpsWpsR(bxInstruction_c *i)
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{
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BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->src1());
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BxPackedAvxRegister op2 = BX_READ_AVX_REG(i->src2());
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BxPackedAvxRegister op3 = BX_READ_AVX_REG(i->src3());
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unsigned len = i->getVL();
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float_status_t status;
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mxcsr_to_softfloat_status_word(status, MXCSR);
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for (unsigned n=0; n < len; n++)
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fmsubps(&op1.avx128(n), &op2.avx128(n), &op3.avx128(n), status);
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check_exceptionsSSE(status.float_exception_flags);
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BX_WRITE_AVX_REGZ(i->dst(), op1, len);
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BX_NEXT_INSTR(i);
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}
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// FMSUBSD
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VFMSUBSD_VpdHsdWsdR(bxInstruction_c *i)
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{
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float64 op1 = BX_READ_XMM_REG_LO_QWORD(i->src1());
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float64 op2 = BX_READ_XMM_REG_LO_QWORD(i->src2());
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float64 op3 = BX_READ_XMM_REG_LO_QWORD(i->src3());
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float_status_t status;
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mxcsr_to_softfloat_status_word(status, MXCSR);
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op1 = float64_muladd(op1, op2, op3, float_muladd_negate_c, status);
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check_exceptionsSSE(status.float_exception_flags);
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BX_WRITE_XMM_REG_LO_QWORD(i->dst(), op1);
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BX_CLEAR_AVX_HIGH(i->dst());
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BX_NEXT_INSTR(i);
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}
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// FMSUBSS
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VFMSUBSS_VpsHssWssR(bxInstruction_c *i)
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{
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float32 op1 = BX_READ_XMM_REG_LO_DWORD(i->src1());
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float32 op2 = BX_READ_XMM_REG_LO_DWORD(i->src2());
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float32 op3 = BX_READ_XMM_REG_LO_DWORD(i->src3());
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float_status_t status;
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mxcsr_to_softfloat_status_word(status, MXCSR);
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op1 = float32_muladd(op1, op2, op3, float_muladd_negate_c, status);
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check_exceptionsSSE(status.float_exception_flags);
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BX_WRITE_XMM_REG_LO_DWORD(i->dst(), op1);
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BX_CLEAR_AVX_HIGH(i->dst());
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BX_NEXT_INSTR(i);
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}
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// FNMADDPD
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VFNMADDPD_VpdHpdWpdR(bxInstruction_c *i)
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{
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BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->src1());
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BxPackedAvxRegister op2 = BX_READ_AVX_REG(i->src2());
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BxPackedAvxRegister op3 = BX_READ_AVX_REG(i->src3());
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unsigned len = i->getVL();
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float_status_t status;
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mxcsr_to_softfloat_status_word(status, MXCSR);
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for (unsigned n=0; n < len; n++)
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fnmaddpd(&op1.avx128(n), &op2.avx128(n), &op3.avx128(n), status);
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check_exceptionsSSE(status.float_exception_flags);
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BX_WRITE_AVX_REGZ(i->dst(), op1, len);
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BX_NEXT_INSTR(i);
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}
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// FNMADDPS
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VFNMADDPS_VpsHpsWpsR(bxInstruction_c *i)
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{
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BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->src1());
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BxPackedAvxRegister op2 = BX_READ_AVX_REG(i->src2());
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BxPackedAvxRegister op3 = BX_READ_AVX_REG(i->src3());
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unsigned len = i->getVL();
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float_status_t status;
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mxcsr_to_softfloat_status_word(status, MXCSR);
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for (unsigned n=0; n < len; n++)
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fnmaddps(&op1.avx128(n), &op2.avx128(n), &op3.avx128(n), status);
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check_exceptionsSSE(status.float_exception_flags);
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BX_WRITE_AVX_REGZ(i->dst(), op1, len);
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BX_NEXT_INSTR(i);
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}
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// FNMADDSD
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VFNMADDSD_VpdHsdWsdR(bxInstruction_c *i)
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{
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float64 op1 = BX_READ_XMM_REG_LO_QWORD(i->src1());
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float64 op2 = BX_READ_XMM_REG_LO_QWORD(i->src2());
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float64 op3 = BX_READ_XMM_REG_LO_QWORD(i->src3());
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float_status_t status;
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mxcsr_to_softfloat_status_word(status, MXCSR);
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op1 = float64_muladd(op1, op2, op3, float_muladd_negate_product, status);
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check_exceptionsSSE(status.float_exception_flags);
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BX_WRITE_XMM_REG_LO_QWORD(i->dst(), op1);
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BX_CLEAR_AVX_HIGH(i->dst());
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BX_NEXT_INSTR(i);
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}
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// FNMADDSS
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VFNMADDSS_VpsHssWssR(bxInstruction_c *i)
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{
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float32 op1 = BX_READ_XMM_REG_LO_DWORD(i->src1());
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float32 op2 = BX_READ_XMM_REG_LO_DWORD(i->src2());
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float32 op3 = BX_READ_XMM_REG_LO_DWORD(i->src3());
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float_status_t status;
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mxcsr_to_softfloat_status_word(status, MXCSR);
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op1 = float32_muladd(op1, op2, op3, float_muladd_negate_product, status);
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check_exceptionsSSE(status.float_exception_flags);
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BX_WRITE_XMM_REG_LO_DWORD(i->dst(), op1);
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BX_CLEAR_AVX_HIGH(i->dst());
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BX_NEXT_INSTR(i);
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}
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// FNMSUBPD
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VFNMSUBPD_VpdHpdWpdR(bxInstruction_c *i)
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{
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BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->src1());
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BxPackedAvxRegister op2 = BX_READ_AVX_REG(i->src2());
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BxPackedAvxRegister op3 = BX_READ_AVX_REG(i->src3());
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unsigned len = i->getVL();
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float_status_t status;
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mxcsr_to_softfloat_status_word(status, MXCSR);
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for (unsigned n=0; n < len; n++)
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fnmsubpd(&op1.avx128(n), &op2.avx128(n), &op3.avx128(n), status);
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check_exceptionsSSE(status.float_exception_flags);
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BX_WRITE_AVX_REGZ(i->dst(), op1, len);
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BX_NEXT_INSTR(i);
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}
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// FNMSUBPS
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VFNMSUBPS_VpsHpsWpsR(bxInstruction_c *i)
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{
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BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->src1());
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BxPackedAvxRegister op2 = BX_READ_AVX_REG(i->src2());
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BxPackedAvxRegister op3 = BX_READ_AVX_REG(i->src3());
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unsigned len = i->getVL();
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float_status_t status;
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mxcsr_to_softfloat_status_word(status, MXCSR);
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for (unsigned n=0; n < len; n++)
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fnmsubps(&op1.avx128(n), &op2.avx128(n), &op3.avx128(n), status);
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check_exceptionsSSE(status.float_exception_flags);
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BX_WRITE_AVX_REGZ(i->dst(), op1, len);
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BX_NEXT_INSTR(i);
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}
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// FNMSUBSD
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VFNMSUBSD_VpdHsdWsdR(bxInstruction_c *i)
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{
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float64 op1 = BX_READ_XMM_REG_LO_QWORD(i->src1());
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float64 op2 = BX_READ_XMM_REG_LO_QWORD(i->src2());
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float64 op3 = BX_READ_XMM_REG_LO_QWORD(i->src3());
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float_status_t status;
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mxcsr_to_softfloat_status_word(status, MXCSR);
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op1 = float64_muladd(op1, op2, op3, float_muladd_negate_result, status);
|
|
check_exceptionsSSE(status.float_exception_flags);
|
|
|
|
BX_WRITE_XMM_REG_LO_QWORD(i->dst(), op1);
|
|
BX_CLEAR_AVX_HIGH(i->dst());
|
|
|
|
BX_NEXT_INSTR(i);
|
|
}
|
|
|
|
// FNMSUBSS
|
|
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VFNMSUBSS_VpsHssWssR(bxInstruction_c *i)
|
|
{
|
|
float32 op1 = BX_READ_XMM_REG_LO_DWORD(i->src1());
|
|
float32 op2 = BX_READ_XMM_REG_LO_DWORD(i->src2());
|
|
float32 op3 = BX_READ_XMM_REG_LO_DWORD(i->src3());
|
|
|
|
float_status_t status;
|
|
mxcsr_to_softfloat_status_word(status, MXCSR);
|
|
op1 = float32_muladd(op1, op2, op3, float_muladd_negate_result, status);
|
|
check_exceptionsSSE(status.float_exception_flags);
|
|
|
|
BX_WRITE_XMM_REG_LO_DWORD(i->dst(), op1);
|
|
BX_CLEAR_AVX_HIGH(i->dst());
|
|
|
|
BX_NEXT_INSTR(i);
|
|
}
|
|
|
|
//////////////////////////////////
|
|
// FMA4 (AMD) specific handlers //
|
|
//////////////////////////////////
|
|
|
|
#define FMA4_SINGLE_SCALAR(HANDLER, func) \
|
|
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C:: HANDLER (bxInstruction_c *i) \
|
|
{ \
|
|
float32 op1 = BX_READ_XMM_REG_LO_DWORD(i->src1()); \
|
|
float32 op2 = BX_READ_XMM_REG_LO_DWORD(i->src2()); \
|
|
float32 op3 = BX_READ_XMM_REG_LO_DWORD(i->src3()); \
|
|
\
|
|
BxPackedXmmRegister dest; \
|
|
\
|
|
float_status_t status; \
|
|
mxcsr_to_softfloat_status_word(status, MXCSR); \
|
|
\
|
|
dest.xmm64u(0) = (func)(op1, op2, op3, status); \
|
|
dest.xmm64u(1) = 0; \
|
|
\
|
|
check_exceptionsSSE(status.float_exception_flags); \
|
|
\
|
|
BX_WRITE_XMM_REG_CLEAR_HIGH(i->dst(), dest); \
|
|
\
|
|
BX_NEXT_INSTR(i); \
|
|
}
|
|
|
|
FMA4_SINGLE_SCALAR(VFMADDSS_VssHssWssVIbR, float32_fmadd)
|
|
FMA4_SINGLE_SCALAR(VFMSUBSS_VssHssWssVIbR, float32_fmsub)
|
|
|
|
FMA4_SINGLE_SCALAR(VFNMADDSS_VssHssWssVIbR, float32_fnmadd)
|
|
FMA4_SINGLE_SCALAR(VFNMSUBSS_VssHssWssVIbR, float32_fnmsub)
|
|
|
|
#define FMA4_DOUBLE_SCALAR(HANDLER, func) \
|
|
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C:: HANDLER (bxInstruction_c *i) \
|
|
{ \
|
|
float64 op1 = BX_READ_XMM_REG_LO_QWORD(i->src1()); \
|
|
float64 op2 = BX_READ_XMM_REG_LO_QWORD(i->src2()); \
|
|
float64 op3 = BX_READ_XMM_REG_LO_QWORD(i->src3()); \
|
|
BxPackedXmmRegister dest; \
|
|
\
|
|
float_status_t status; \
|
|
mxcsr_to_softfloat_status_word(status, MXCSR); \
|
|
\
|
|
dest.xmm64u(0) = (func)(op1, op2, op3, status); \
|
|
dest.xmm64u(1) = 0; \
|
|
\
|
|
check_exceptionsSSE(status.float_exception_flags); \
|
|
\
|
|
BX_WRITE_XMM_REG_CLEAR_HIGH(i->dst(), dest); \
|
|
\
|
|
BX_NEXT_INSTR(i); \
|
|
}
|
|
|
|
FMA4_DOUBLE_SCALAR(VFMADDSD_VsdHsdWsdVIbR, float64_fmadd)
|
|
FMA4_DOUBLE_SCALAR(VFMSUBSD_VsdHsdWsdVIbR, float64_fmsub)
|
|
|
|
FMA4_DOUBLE_SCALAR(VFNMADDSD_VsdHsdWsdVIbR, float64_fnmadd)
|
|
FMA4_DOUBLE_SCALAR(VFNMSUBSD_VsdHsdWsdVIbR, float64_fnmsub)
|
|
|
|
#endif
|