940 lines
33 KiB
C++
Executable File
940 lines
33 KiB
C++
Executable File
/////////////////////////////////////////////////////////////////////////
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// $Id: access32.cc,v 1.2 2008-06-12 20:41:48 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (c) 2008 Stanislav Shwartsman
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// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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//
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/////////////////////////////////////////////////////////////////////////
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#define NEED_CPU_REG_SHORTCUTS 1
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#include "bochs.h"
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#include "cpu.h"
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#define LOG_THIS BX_CPU_THIS_PTR
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// The macro was made in order to optimize access alignment into TLB lookup -
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// when aligment check is enabled a misaligned access will miss the TLB.
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// BX_CPU_THIS_PTR alignment_check_mask must be initialized to all'ones if
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// alignment check exception is enabled and LPF_MASK if not.
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#if BX_CPU_LEVEL >= 4 && BX_SUPPORT_ALIGNMENT_CHECK
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#define AlignedAccessLPFOf32(laddr, alignment_mask) \
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((laddr) & (LPF_MASK | (alignment_mask))) & (BX_CPU_THIS_PTR alignment_check_mask)
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#else
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#define AlignedAccessLPFOf32(laddr, alignment_mask) LPFOf(laddr)
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#endif
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void BX_CPP_AttrRegparmN(3)
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BX_CPU_C::write_virtual_byte_32(unsigned s, Bit32u offset, Bit8u data)
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{
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Bit32u laddr;
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bx_segment_reg_t *seg = &BX_CPU_THIS_PTR sregs[s];
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BX_INSTR_MEM_DATA_ACCESS(BX_CPU_ID, s, offset, 1, BX_WRITE);
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BX_ASSERT(BX_CPU_THIS_PTR cpu_mode != BX_MODE_LONG_64);
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if (seg->cache.valid & SegAccessWOK4G) {
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accessOK:
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laddr = BX_CPU_THIS_PTR get_laddr32(s, offset);
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#if BX_SupportGuest2HostTLB
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unsigned tlbIndex = BX_TLB_INDEX_OF(laddr, 0);
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Bit32u lpf = LPFOf(laddr);
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bx_TLB_entry *tlbEntry = &BX_CPU_THIS_PTR TLB.entry[tlbIndex];
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if (tlbEntry->lpf == lpf) {
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// See if the TLB entry privilege level allows us write access
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// from this CPL.
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if (tlbEntry->accessBits & (0x10 << CPL)) {
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bx_hostpageaddr_t hostPageAddr = tlbEntry->hostPageAddr;
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Bit32u pageOffset = PAGE_OFFSET(laddr);
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BX_INSTR_LIN_ACCESS(BX_CPU_ID, laddr, tlbEntry->ppf | pageOffset, 1, BX_WRITE);
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BX_DBG_LIN_MEMORY_ACCESS(BX_CPU_ID, laddr,
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tlbEntry->ppf | pageOffset, 1, CPL, BX_WRITE, (Bit8u*) &data);
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Bit8u *hostAddr = (Bit8u*) (hostPageAddr | pageOffset);
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#if BX_SUPPORT_ICACHE
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pageWriteStampTable.decWriteStamp(tlbEntry->ppf);
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#endif
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*hostAddr = data;
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return;
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}
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}
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#endif
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access_write_linear(laddr, 1, CPL, (void *) &data);
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return;
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}
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if (seg->cache.valid & SegAccessWOK) {
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if (offset <= seg->cache.u.segment.limit_scaled)
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goto accessOK;
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}
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write_virtual_checks(seg, offset, 1);
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goto accessOK;
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}
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void BX_CPP_AttrRegparmN(3)
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BX_CPU_C::write_virtual_word_32(unsigned s, Bit32u offset, Bit16u data)
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{
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Bit32u laddr;
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bx_segment_reg_t *seg = &BX_CPU_THIS_PTR sregs[s];
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BX_INSTR_MEM_DATA_ACCESS(BX_CPU_ID, s, offset, 2, BX_WRITE);
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BX_ASSERT(BX_CPU_THIS_PTR cpu_mode != BX_MODE_LONG_64);
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if (seg->cache.valid & SegAccessWOK4G) {
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accessOK:
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laddr = BX_CPU_THIS_PTR get_laddr32(s, offset);
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#if BX_SupportGuest2HostTLB
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unsigned tlbIndex = BX_TLB_INDEX_OF(laddr, 1);
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Bit32u lpf = AlignedAccessLPFOf32(laddr, 1);
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bx_TLB_entry *tlbEntry = &BX_CPU_THIS_PTR TLB.entry[tlbIndex];
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if (tlbEntry->lpf == lpf) {
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// See if the TLB entry privilege level allows us write access
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// from this CPL.
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if (tlbEntry->accessBits & (0x10 << CPL)) {
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bx_hostpageaddr_t hostPageAddr = tlbEntry->hostPageAddr;
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Bit32u pageOffset = PAGE_OFFSET(laddr);
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BX_INSTR_LIN_ACCESS(BX_CPU_ID, laddr, tlbEntry->ppf | pageOffset, 2, BX_WRITE);
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BX_DBG_LIN_MEMORY_ACCESS(BX_CPU_ID, laddr,
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tlbEntry->ppf | pageOffset, 2, CPL, BX_WRITE, (Bit8u*) &data);
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Bit16u *hostAddr = (Bit16u*) (hostPageAddr | pageOffset);
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#if BX_SUPPORT_ICACHE
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pageWriteStampTable.decWriteStamp(tlbEntry->ppf);
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#endif
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WriteHostWordToLittleEndian(hostAddr, data);
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return;
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}
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}
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#endif
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#if BX_CPU_LEVEL >= 4 && BX_SUPPORT_ALIGNMENT_CHECK
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if (BX_CPU_THIS_PTR alignment_check()) {
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if (laddr & 1) {
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BX_ERROR(("write_virtual_word(): #AC misaligned access"));
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exception(BX_AC_EXCEPTION, 0, 0);
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}
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}
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#endif
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access_write_linear(laddr, 2, CPL, (void *) &data);
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return;
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}
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if (seg->cache.valid & SegAccessWOK) {
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if (offset < seg->cache.u.segment.limit_scaled)
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goto accessOK;
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}
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write_virtual_checks(seg, offset, 2);
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goto accessOK;
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}
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void BX_CPP_AttrRegparmN(3)
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BX_CPU_C::write_virtual_dword_32(unsigned s, Bit32u offset, Bit32u data)
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{
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Bit32u laddr;
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bx_segment_reg_t *seg = &BX_CPU_THIS_PTR sregs[s];
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BX_INSTR_MEM_DATA_ACCESS(BX_CPU_ID, s, offset, 4, BX_WRITE);
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BX_ASSERT(BX_CPU_THIS_PTR cpu_mode != BX_MODE_LONG_64);
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if (seg->cache.valid & SegAccessWOK4G) {
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accessOK:
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laddr = BX_CPU_THIS_PTR get_laddr32(s, offset);
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#if BX_SupportGuest2HostTLB
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unsigned tlbIndex = BX_TLB_INDEX_OF(laddr, 3);
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Bit32u lpf = AlignedAccessLPFOf32(laddr, 3);
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bx_TLB_entry *tlbEntry = &BX_CPU_THIS_PTR TLB.entry[tlbIndex];
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if (tlbEntry->lpf == lpf) {
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// See if the TLB entry privilege level allows us write access
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// from this CPL.
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if (tlbEntry->accessBits & (0x10 << CPL)) {
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bx_hostpageaddr_t hostPageAddr = tlbEntry->hostPageAddr;
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Bit32u pageOffset = PAGE_OFFSET(laddr);
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BX_INSTR_LIN_ACCESS(BX_CPU_ID, laddr, tlbEntry->ppf | pageOffset, 4, BX_WRITE);
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BX_DBG_LIN_MEMORY_ACCESS(BX_CPU_ID, laddr,
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tlbEntry->ppf | pageOffset, 4, CPL, BX_WRITE, (Bit8u*) &data);
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Bit32u *hostAddr = (Bit32u*) (hostPageAddr | pageOffset);
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#if BX_SUPPORT_ICACHE
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pageWriteStampTable.decWriteStamp(tlbEntry->ppf);
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#endif
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WriteHostDWordToLittleEndian(hostAddr, data);
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return;
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}
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}
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#endif
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#if BX_CPU_LEVEL >= 4 && BX_SUPPORT_ALIGNMENT_CHECK
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if (BX_CPU_THIS_PTR alignment_check()) {
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if (laddr & 3) {
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BX_ERROR(("write_virtual_dword(): #AC misaligned access"));
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exception(BX_AC_EXCEPTION, 0, 0);
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}
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}
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#endif
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access_write_linear(laddr, 4, CPL, (void *) &data);
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return;
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}
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if (seg->cache.valid & SegAccessWOK) {
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if (offset < (seg->cache.u.segment.limit_scaled-2))
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goto accessOK;
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}
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write_virtual_checks(seg, offset, 4);
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goto accessOK;
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}
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void BX_CPP_AttrRegparmN(3)
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BX_CPU_C::write_virtual_qword_32(unsigned s, Bit32u offset, Bit64u data)
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{
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Bit32u laddr;
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bx_segment_reg_t *seg = &BX_CPU_THIS_PTR sregs[s];
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BX_INSTR_MEM_DATA_ACCESS(BX_CPU_ID, s, offset, 8, BX_WRITE);
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BX_ASSERT(BX_CPU_THIS_PTR cpu_mode != BX_MODE_LONG_64);
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if (seg->cache.valid & SegAccessWOK4G) {
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accessOK:
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laddr = BX_CPU_THIS_PTR get_laddr32(s, offset);
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#if BX_SupportGuest2HostTLB
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unsigned tlbIndex = BX_TLB_INDEX_OF(laddr, 7);
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Bit32u lpf = AlignedAccessLPFOf32(laddr, 7);
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bx_TLB_entry *tlbEntry = &BX_CPU_THIS_PTR TLB.entry[tlbIndex];
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if (tlbEntry->lpf == lpf) {
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// See if the TLB entry privilege level allows us write access
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// from this CPL.
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if (tlbEntry->accessBits & (0x10 << CPL)) {
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bx_hostpageaddr_t hostPageAddr = tlbEntry->hostPageAddr;
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Bit32u pageOffset = PAGE_OFFSET(laddr);
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BX_INSTR_LIN_ACCESS(BX_CPU_ID, laddr, tlbEntry->ppf | pageOffset, 8, BX_WRITE);
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BX_DBG_LIN_MEMORY_ACCESS(BX_CPU_ID, laddr,
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tlbEntry->ppf | pageOffset, 8, CPL, BX_WRITE, (Bit8u*) &data);
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Bit64u *hostAddr = (Bit64u*) (hostPageAddr | pageOffset);
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#if BX_SUPPORT_ICACHE
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pageWriteStampTable.decWriteStamp(tlbEntry->ppf);
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#endif
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WriteHostQWordToLittleEndian(hostAddr, data);
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return;
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}
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}
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#endif
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#if BX_CPU_LEVEL >= 4 && BX_SUPPORT_ALIGNMENT_CHECK
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if (BX_CPU_THIS_PTR alignment_check()) {
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if (laddr & 7) {
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BX_ERROR(("write_virtual_qword(): #AC misaligned access"));
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exception(BX_AC_EXCEPTION, 0, 0);
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}
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}
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#endif
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access_write_linear(laddr, 8, CPL, (void *) &data);
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return;
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}
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if (seg->cache.valid & SegAccessWOK) {
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if (offset <= (seg->cache.u.segment.limit_scaled-7))
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goto accessOK;
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}
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write_virtual_checks(seg, offset, 8);
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goto accessOK;
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}
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Bit8u BX_CPP_AttrRegparmN(2)
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BX_CPU_C::read_virtual_byte_32(unsigned s, Bit32u offset)
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{
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Bit32u laddr;
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bx_segment_reg_t *seg = &BX_CPU_THIS_PTR sregs[s];
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Bit8u data;
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BX_INSTR_MEM_DATA_ACCESS(BX_CPU_ID, s, offset, 1, BX_READ);
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BX_ASSERT(BX_CPU_THIS_PTR cpu_mode != BX_MODE_LONG_64);
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if (seg->cache.valid & SegAccessROK4G) {
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accessOK:
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laddr = BX_CPU_THIS_PTR get_laddr32(s, offset);
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#if BX_SupportGuest2HostTLB
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unsigned tlbIndex = BX_TLB_INDEX_OF(laddr, 0);
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Bit32u lpf = LPFOf(laddr);
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bx_TLB_entry *tlbEntry = &BX_CPU_THIS_PTR TLB.entry[tlbIndex];
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if (tlbEntry->lpf == lpf) {
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// See if the TLB entry privilege level allows us read access
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// from this CPL.
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if (tlbEntry->accessBits & (1<<CPL)) { // Read this pl OK.
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bx_hostpageaddr_t hostPageAddr = tlbEntry->hostPageAddr;
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Bit32u pageOffset = PAGE_OFFSET(laddr);
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BX_INSTR_LIN_ACCESS(BX_CPU_ID, laddr, tlbEntry->ppf | pageOffset, 1, BX_READ);
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Bit8u *hostAddr = (Bit8u*) (hostPageAddr | pageOffset);
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data = *hostAddr;
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BX_DBG_LIN_MEMORY_ACCESS(BX_CPU_ID, laddr,
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tlbEntry->ppf | pageOffset, 1, CPL, BX_READ, (Bit8u*) &data);
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return data;
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}
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}
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#endif
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access_read_linear(laddr, 1, CPL, BX_READ, (void *) &data);
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return data;
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}
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if (seg->cache.valid & SegAccessROK) {
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if (offset <= seg->cache.u.segment.limit_scaled)
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goto accessOK;
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}
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read_virtual_checks(seg, offset, 1);
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goto accessOK;
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}
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Bit16u BX_CPP_AttrRegparmN(2)
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BX_CPU_C::read_virtual_word_32(unsigned s, Bit32u offset)
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{
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Bit32u laddr;
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bx_segment_reg_t *seg = &BX_CPU_THIS_PTR sregs[s];
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Bit16u data;
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BX_INSTR_MEM_DATA_ACCESS(BX_CPU_ID, s, offset, 2, BX_READ);
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BX_ASSERT(BX_CPU_THIS_PTR cpu_mode != BX_MODE_LONG_64);
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if (seg->cache.valid & SegAccessROK4G) {
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accessOK:
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laddr = BX_CPU_THIS_PTR get_laddr32(s, offset);
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#if BX_SupportGuest2HostTLB
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unsigned tlbIndex = BX_TLB_INDEX_OF(laddr, 1);
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Bit32u lpf = AlignedAccessLPFOf32(laddr, 1);
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bx_TLB_entry *tlbEntry = &BX_CPU_THIS_PTR TLB.entry[tlbIndex];
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if (tlbEntry->lpf == lpf) {
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// See if the TLB entry privilege level allows us read access
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// from this CPL.
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if (tlbEntry->accessBits & (1<<CPL)) { // Read this pl OK.
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bx_hostpageaddr_t hostPageAddr = tlbEntry->hostPageAddr;
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Bit32u pageOffset = PAGE_OFFSET(laddr);
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BX_INSTR_LIN_ACCESS(BX_CPU_ID, laddr, tlbEntry->ppf | pageOffset, 2, BX_READ);
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Bit16u *hostAddr = (Bit16u*) (hostPageAddr | pageOffset);
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ReadHostWordFromLittleEndian(hostAddr, data);
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BX_DBG_LIN_MEMORY_ACCESS(BX_CPU_ID, laddr,
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tlbEntry->ppf | pageOffset, 2, CPL, BX_READ, (Bit8u*) &data);
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return data;
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}
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}
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#endif
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#if BX_CPU_LEVEL >= 4 && BX_SUPPORT_ALIGNMENT_CHECK
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if (BX_CPU_THIS_PTR alignment_check()) {
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if (laddr & 1) {
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BX_ERROR(("read_virtual_word(): #AC misaligned access"));
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exception(BX_AC_EXCEPTION, 0, 0);
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}
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}
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#endif
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access_read_linear(laddr, 2, CPL, BX_READ, (void *) &data);
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return data;
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}
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if (seg->cache.valid & SegAccessROK) {
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if (offset < seg->cache.u.segment.limit_scaled)
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goto accessOK;
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}
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read_virtual_checks(seg, offset, 2);
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goto accessOK;
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}
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Bit32u BX_CPP_AttrRegparmN(2)
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BX_CPU_C::read_virtual_dword_32(unsigned s, Bit32u offset)
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{
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Bit32u laddr;
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bx_segment_reg_t *seg = &BX_CPU_THIS_PTR sregs[s];
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Bit32u data;
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BX_INSTR_MEM_DATA_ACCESS(BX_CPU_ID, s, offset, 4, BX_READ);
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BX_ASSERT(BX_CPU_THIS_PTR cpu_mode != BX_MODE_LONG_64);
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if (seg->cache.valid & SegAccessROK4G) {
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accessOK:
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laddr = BX_CPU_THIS_PTR get_laddr32(s, offset);
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#if BX_SupportGuest2HostTLB
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unsigned tlbIndex = BX_TLB_INDEX_OF(laddr, 3);
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Bit32u lpf = AlignedAccessLPFOf32(laddr, 3);
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bx_TLB_entry *tlbEntry = &BX_CPU_THIS_PTR TLB.entry[tlbIndex];
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if (tlbEntry->lpf == lpf) {
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// See if the TLB entry privilege level allows us read access
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// from this CPL.
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if (tlbEntry->accessBits & (1<<CPL)) { // Read this pl OK.
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bx_hostpageaddr_t hostPageAddr = tlbEntry->hostPageAddr;
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Bit32u pageOffset = PAGE_OFFSET(laddr);
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BX_INSTR_LIN_ACCESS(BX_CPU_ID, laddr, tlbEntry->ppf | pageOffset, 4, BX_READ);
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Bit32u *hostAddr = (Bit32u*) (hostPageAddr | pageOffset);
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ReadHostDWordFromLittleEndian(hostAddr, data);
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BX_DBG_LIN_MEMORY_ACCESS(BX_CPU_ID, laddr,
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tlbEntry->ppf | pageOffset, 4, CPL, BX_READ, (Bit8u*) &data);
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return data;
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}
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}
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#endif
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#if BX_CPU_LEVEL >= 4 && BX_SUPPORT_ALIGNMENT_CHECK
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if (BX_CPU_THIS_PTR alignment_check()) {
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if (laddr & 3) {
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BX_ERROR(("read_virtual_dword(): #AC misaligned access"));
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exception(BX_AC_EXCEPTION, 0, 0);
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}
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}
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#endif
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access_read_linear(laddr, 4, CPL, BX_READ, (void *) &data);
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return data;
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}
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if (seg->cache.valid & SegAccessROK) {
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if (offset < (seg->cache.u.segment.limit_scaled-2))
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goto accessOK;
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}
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read_virtual_checks(seg, offset, 4);
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goto accessOK;
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}
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Bit64u BX_CPP_AttrRegparmN(2)
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BX_CPU_C::read_virtual_qword_32(unsigned s, Bit32u offset)
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{
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Bit32u laddr;
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bx_segment_reg_t *seg = &BX_CPU_THIS_PTR sregs[s];
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Bit64u data;
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BX_INSTR_MEM_DATA_ACCESS(BX_CPU_ID, s, offset, 8, BX_READ);
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BX_ASSERT(BX_CPU_THIS_PTR cpu_mode != BX_MODE_LONG_64);
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if (seg->cache.valid & SegAccessROK4G) {
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accessOK:
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laddr = BX_CPU_THIS_PTR get_laddr32(s, offset);
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#if BX_SupportGuest2HostTLB
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unsigned tlbIndex = BX_TLB_INDEX_OF(laddr, 7);
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Bit32u lpf = AlignedAccessLPFOf32(laddr, 7);
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bx_TLB_entry *tlbEntry = &BX_CPU_THIS_PTR TLB.entry[tlbIndex];
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if (tlbEntry->lpf == lpf) {
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// See if the TLB entry privilege level allows us read access
|
|
// from this CPL.
|
|
if (tlbEntry->accessBits & (1<<CPL)) { // Read this pl OK.
|
|
bx_hostpageaddr_t hostPageAddr = tlbEntry->hostPageAddr;
|
|
Bit32u pageOffset = PAGE_OFFSET(laddr);
|
|
BX_INSTR_LIN_ACCESS(BX_CPU_ID, laddr, tlbEntry->ppf | pageOffset, 8, BX_READ);
|
|
Bit64u *hostAddr = (Bit64u*) (hostPageAddr | pageOffset);
|
|
ReadHostQWordFromLittleEndian(hostAddr, data);
|
|
BX_DBG_LIN_MEMORY_ACCESS(BX_CPU_ID, laddr,
|
|
tlbEntry->ppf | pageOffset, 8, CPL, BX_READ, (Bit8u*) &data);
|
|
return data;
|
|
}
|
|
}
|
|
#endif
|
|
#if BX_CPU_LEVEL >= 4 && BX_SUPPORT_ALIGNMENT_CHECK
|
|
if (BX_CPU_THIS_PTR alignment_check()) {
|
|
if (laddr & 7) {
|
|
BX_ERROR(("read_virtual_qword(): #AC misaligned access"));
|
|
exception(BX_AC_EXCEPTION, 0, 0);
|
|
}
|
|
}
|
|
#endif
|
|
access_read_linear(laddr, 8, CPL, BX_READ, (void *) &data);
|
|
return data;
|
|
}
|
|
|
|
if (seg->cache.valid & SegAccessROK) {
|
|
if (offset <= (seg->cache.u.segment.limit_scaled-7))
|
|
goto accessOK;
|
|
}
|
|
read_virtual_checks(seg, offset, 8);
|
|
goto accessOK;
|
|
}
|
|
|
|
//////////////////////////////////////////////////////////////
|
|
// special Read-Modify-Write operations //
|
|
// address translation info is kept across read/write calls //
|
|
//////////////////////////////////////////////////////////////
|
|
|
|
Bit8u BX_CPP_AttrRegparmN(2)
|
|
BX_CPU_C::read_RMW_virtual_byte_32(unsigned s, Bit32u offset)
|
|
{
|
|
Bit32u laddr;
|
|
bx_segment_reg_t *seg = &BX_CPU_THIS_PTR sregs[s];
|
|
Bit8u data;
|
|
BX_INSTR_MEM_DATA_ACCESS(BX_CPU_ID, s, offset, 1, BX_RW);
|
|
|
|
BX_ASSERT(BX_CPU_THIS_PTR cpu_mode != BX_MODE_LONG_64);
|
|
|
|
if (seg->cache.valid & SegAccessWOK4G) {
|
|
accessOK:
|
|
laddr = BX_CPU_THIS_PTR get_laddr32(s, offset);
|
|
#if BX_SupportGuest2HostTLB
|
|
unsigned tlbIndex = BX_TLB_INDEX_OF(laddr, 0);
|
|
Bit32u lpf = LPFOf(laddr);
|
|
bx_TLB_entry *tlbEntry = &BX_CPU_THIS_PTR TLB.entry[tlbIndex];
|
|
if (tlbEntry->lpf == lpf) {
|
|
// See if the TLB entry privilege level allows us write access
|
|
// from this CPL.
|
|
if (tlbEntry->accessBits & (0x10 << CPL)) {
|
|
bx_hostpageaddr_t hostPageAddr = tlbEntry->hostPageAddr;
|
|
Bit32u pageOffset = PAGE_OFFSET(laddr);
|
|
BX_INSTR_LIN_ACCESS(BX_CPU_ID, laddr, tlbEntry->ppf | pageOffset, 1, BX_RW);
|
|
Bit8u *hostAddr = (Bit8u*) (hostPageAddr | pageOffset);
|
|
#if BX_SUPPORT_ICACHE
|
|
pageWriteStampTable.decWriteStamp(tlbEntry->ppf);
|
|
#endif
|
|
data = *hostAddr;
|
|
BX_CPU_THIS_PTR address_xlation.pages = (bx_ptr_equiv_t) hostAddr;
|
|
BX_DBG_LIN_MEMORY_ACCESS(BX_CPU_ID, laddr,
|
|
tlbEntry->ppf | pageOffset, 1, CPL, BX_READ, (Bit8u*) &data);
|
|
return data;
|
|
}
|
|
}
|
|
#endif
|
|
access_read_linear(laddr, 1, CPL, BX_RW, (void *) &data);
|
|
return data;
|
|
}
|
|
|
|
if (seg->cache.valid & SegAccessWOK) {
|
|
if (offset <= seg->cache.u.segment.limit_scaled)
|
|
goto accessOK;
|
|
}
|
|
write_virtual_checks(seg, offset, 1);
|
|
goto accessOK;
|
|
}
|
|
|
|
Bit16u BX_CPP_AttrRegparmN(2)
|
|
BX_CPU_C::read_RMW_virtual_word_32(unsigned s, Bit32u offset)
|
|
{
|
|
Bit32u laddr;
|
|
bx_segment_reg_t *seg = &BX_CPU_THIS_PTR sregs[s];
|
|
Bit16u data;
|
|
BX_INSTR_MEM_DATA_ACCESS(BX_CPU_ID, s, offset, 2, BX_RW);
|
|
|
|
BX_ASSERT(BX_CPU_THIS_PTR cpu_mode != BX_MODE_LONG_64);
|
|
|
|
if (seg->cache.valid & SegAccessWOK4G) {
|
|
accessOK:
|
|
laddr = BX_CPU_THIS_PTR get_laddr32(s, offset);
|
|
#if BX_SupportGuest2HostTLB
|
|
unsigned tlbIndex = BX_TLB_INDEX_OF(laddr, 1);
|
|
Bit32u lpf = AlignedAccessLPFOf32(laddr, 1);
|
|
bx_TLB_entry *tlbEntry = &BX_CPU_THIS_PTR TLB.entry[tlbIndex];
|
|
if (tlbEntry->lpf == lpf) {
|
|
// See if the TLB entry privilege level allows us write access
|
|
// from this CPL.
|
|
if (tlbEntry->accessBits & (0x10 << CPL)) {
|
|
bx_hostpageaddr_t hostPageAddr = tlbEntry->hostPageAddr;
|
|
Bit32u pageOffset = PAGE_OFFSET(laddr);
|
|
BX_INSTR_LIN_ACCESS(BX_CPU_ID, laddr, tlbEntry->ppf | pageOffset, 2, BX_RW);
|
|
Bit16u *hostAddr = (Bit16u*) (hostPageAddr | pageOffset);
|
|
#if BX_SUPPORT_ICACHE
|
|
pageWriteStampTable.decWriteStamp(tlbEntry->ppf);
|
|
#endif
|
|
ReadHostWordFromLittleEndian(hostAddr, data);
|
|
BX_CPU_THIS_PTR address_xlation.pages = (bx_ptr_equiv_t) hostAddr;
|
|
BX_DBG_LIN_MEMORY_ACCESS(BX_CPU_ID, laddr,
|
|
tlbEntry->ppf | pageOffset, 2, CPL, BX_READ, (Bit8u*) &data);
|
|
return data;
|
|
}
|
|
}
|
|
#endif
|
|
#if BX_CPU_LEVEL >= 4 && BX_SUPPORT_ALIGNMENT_CHECK
|
|
if (BX_CPU_THIS_PTR alignment_check()) {
|
|
if (laddr & 1) {
|
|
BX_ERROR(("read_RMW_virtual_word(): #AC misaligned access"));
|
|
exception(BX_AC_EXCEPTION, 0, 0);
|
|
}
|
|
}
|
|
#endif
|
|
access_read_linear(laddr, 2, CPL, BX_RW, (void *) &data);
|
|
return data;
|
|
}
|
|
|
|
if (seg->cache.valid & SegAccessWOK) {
|
|
if (offset < seg->cache.u.segment.limit_scaled)
|
|
goto accessOK;
|
|
}
|
|
write_virtual_checks(seg, offset, 2);
|
|
goto accessOK;
|
|
}
|
|
|
|
Bit32u BX_CPP_AttrRegparmN(2)
|
|
BX_CPU_C::read_RMW_virtual_dword_32(unsigned s, Bit32u offset)
|
|
{
|
|
Bit32u laddr;
|
|
bx_segment_reg_t *seg = &BX_CPU_THIS_PTR sregs[s];
|
|
Bit32u data;
|
|
BX_INSTR_MEM_DATA_ACCESS(BX_CPU_ID, s, offset, 4, BX_RW);
|
|
|
|
BX_ASSERT(BX_CPU_THIS_PTR cpu_mode != BX_MODE_LONG_64);
|
|
|
|
if (seg->cache.valid & SegAccessWOK4G) {
|
|
accessOK:
|
|
laddr = BX_CPU_THIS_PTR get_laddr32(s, offset);
|
|
#if BX_SupportGuest2HostTLB
|
|
unsigned tlbIndex = BX_TLB_INDEX_OF(laddr, 3);
|
|
Bit32u lpf = AlignedAccessLPFOf32(laddr, 3);
|
|
bx_TLB_entry *tlbEntry = &BX_CPU_THIS_PTR TLB.entry[tlbIndex];
|
|
if (tlbEntry->lpf == lpf) {
|
|
// See if the TLB entry privilege level allows us write access
|
|
// from this CPL.
|
|
if (tlbEntry->accessBits & (0x10 << CPL)) {
|
|
bx_hostpageaddr_t hostPageAddr = tlbEntry->hostPageAddr;
|
|
Bit32u pageOffset = PAGE_OFFSET(laddr);
|
|
BX_INSTR_LIN_ACCESS(BX_CPU_ID, laddr, tlbEntry->ppf | pageOffset, 4, BX_RW);
|
|
Bit32u *hostAddr = (Bit32u*) (hostPageAddr | pageOffset);
|
|
#if BX_SUPPORT_ICACHE
|
|
pageWriteStampTable.decWriteStamp(tlbEntry->ppf);
|
|
#endif
|
|
ReadHostDWordFromLittleEndian(hostAddr, data);
|
|
BX_CPU_THIS_PTR address_xlation.pages = (bx_ptr_equiv_t) hostAddr;
|
|
BX_DBG_LIN_MEMORY_ACCESS(BX_CPU_ID, laddr,
|
|
tlbEntry->ppf | pageOffset, 4, CPL, BX_READ, (Bit8u*) &data);
|
|
return data;
|
|
}
|
|
}
|
|
#endif
|
|
#if BX_CPU_LEVEL >= 4 && BX_SUPPORT_ALIGNMENT_CHECK
|
|
if (BX_CPU_THIS_PTR alignment_check()) {
|
|
if (laddr & 3) {
|
|
BX_ERROR(("read_RMW_virtual_dword(): #AC misaligned access"));
|
|
exception(BX_AC_EXCEPTION, 0, 0);
|
|
}
|
|
}
|
|
#endif
|
|
access_read_linear(laddr, 4, CPL, BX_RW, (void *) &data);
|
|
return data;
|
|
}
|
|
|
|
if (seg->cache.valid & SegAccessWOK) {
|
|
if (offset < (seg->cache.u.segment.limit_scaled-2))
|
|
goto accessOK;
|
|
}
|
|
write_virtual_checks(seg, offset, 4);
|
|
goto accessOK;
|
|
}
|
|
|
|
Bit64u BX_CPP_AttrRegparmN(2)
|
|
BX_CPU_C::read_RMW_virtual_qword_32(unsigned s, Bit32u offset)
|
|
{
|
|
Bit32u laddr;
|
|
bx_segment_reg_t *seg = &BX_CPU_THIS_PTR sregs[s];
|
|
Bit64u data;
|
|
BX_INSTR_MEM_DATA_ACCESS(BX_CPU_ID, s, offset, 8, BX_RW);
|
|
|
|
BX_ASSERT(BX_CPU_THIS_PTR cpu_mode != BX_MODE_LONG_64);
|
|
|
|
if (seg->cache.valid & SegAccessWOK4G) {
|
|
accessOK:
|
|
laddr = BX_CPU_THIS_PTR get_laddr32(s, offset);
|
|
#if BX_SupportGuest2HostTLB
|
|
unsigned tlbIndex = BX_TLB_INDEX_OF(laddr, 7);
|
|
Bit32u lpf = AlignedAccessLPFOf32(laddr, 7);
|
|
bx_TLB_entry *tlbEntry = &BX_CPU_THIS_PTR TLB.entry[tlbIndex];
|
|
if (tlbEntry->lpf == lpf) {
|
|
// See if the TLB entry privilege level allows us write access
|
|
// from this CPL.
|
|
if (tlbEntry->accessBits & (0x10 << CPL)) {
|
|
bx_hostpageaddr_t hostPageAddr = tlbEntry->hostPageAddr;
|
|
Bit32u pageOffset = PAGE_OFFSET(laddr);
|
|
BX_INSTR_LIN_ACCESS(BX_CPU_ID, laddr, tlbEntry->ppf | pageOffset, 8, BX_RW);
|
|
Bit64u *hostAddr = (Bit64u*) (hostPageAddr | pageOffset);
|
|
#if BX_SUPPORT_ICACHE
|
|
pageWriteStampTable.decWriteStamp(tlbEntry->ppf);
|
|
#endif
|
|
ReadHostQWordFromLittleEndian(hostAddr, data);
|
|
BX_CPU_THIS_PTR address_xlation.pages = (bx_ptr_equiv_t) hostAddr;
|
|
BX_DBG_LIN_MEMORY_ACCESS(BX_CPU_ID, laddr,
|
|
tlbEntry->ppf | pageOffset, 8, CPL, BX_READ, (Bit8u*) &data);
|
|
return data;
|
|
}
|
|
}
|
|
#endif
|
|
#if BX_CPU_LEVEL >= 4 && BX_SUPPORT_ALIGNMENT_CHECK
|
|
if (BX_CPU_THIS_PTR alignment_check()) {
|
|
if (laddr & 7) {
|
|
BX_ERROR(("read_RMW_virtual_qword(): #AC misaligned access"));
|
|
exception(BX_AC_EXCEPTION, 0, 0);
|
|
}
|
|
}
|
|
#endif
|
|
access_read_linear(laddr, 8, CPL, BX_RW, (void *) &data);
|
|
return data;
|
|
}
|
|
|
|
if (seg->cache.valid & SegAccessWOK) {
|
|
if (offset <= (seg->cache.u.segment.limit_scaled-7))
|
|
goto accessOK;
|
|
}
|
|
write_virtual_checks(seg, offset, 8);
|
|
goto accessOK;
|
|
}
|
|
|
|
void BX_CPP_AttrRegparmN(1)
|
|
BX_CPU_C::write_RMW_virtual_byte(Bit8u val8)
|
|
{
|
|
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID,
|
|
BX_CPU_THIS_PTR address_xlation.paddress1, 2, BX_WRITE, (Bit8u*) &val8);
|
|
|
|
if (BX_CPU_THIS_PTR address_xlation.pages > 2) {
|
|
// Pages > 2 means it stores a host address for direct access.
|
|
Bit8u *hostAddr = (Bit8u *) BX_CPU_THIS_PTR address_xlation.pages;
|
|
*hostAddr = val8;
|
|
}
|
|
else {
|
|
// address_xlation.pages must be 1
|
|
BX_MEM(0)->writePhysicalPage(BX_CPU_THIS,
|
|
BX_CPU_THIS_PTR address_xlation.paddress1, 1, &val8);
|
|
}
|
|
}
|
|
|
|
void BX_CPP_AttrRegparmN(1)
|
|
BX_CPU_C::write_RMW_virtual_word(Bit16u val16)
|
|
{
|
|
if (BX_CPU_THIS_PTR address_xlation.pages > 2) {
|
|
// Pages > 2 means it stores a host address for direct access.
|
|
Bit16u *hostAddr = (Bit16u *) BX_CPU_THIS_PTR address_xlation.pages;
|
|
WriteHostWordToLittleEndian(hostAddr, val16);
|
|
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID,
|
|
BX_CPU_THIS_PTR address_xlation.paddress1, 2, BX_WRITE, (Bit8u*) &val16);
|
|
}
|
|
else if (BX_CPU_THIS_PTR address_xlation.pages == 1) {
|
|
BX_MEM(0)->writePhysicalPage(BX_CPU_THIS,
|
|
BX_CPU_THIS_PTR address_xlation.paddress1, 2, &val16);
|
|
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID,
|
|
BX_CPU_THIS_PTR address_xlation.paddress1, 2, BX_WRITE, (Bit8u*) &val16);
|
|
}
|
|
else {
|
|
#ifdef BX_LITTLE_ENDIAN
|
|
BX_MEM(0)->writePhysicalPage(BX_CPU_THIS,
|
|
BX_CPU_THIS_PTR address_xlation.paddress1, 1, &val16);
|
|
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID,
|
|
BX_CPU_THIS_PTR address_xlation.paddress1, 1, BX_WRITE, (Bit8u*) &val16);
|
|
BX_MEM(0)->writePhysicalPage(BX_CPU_THIS,
|
|
BX_CPU_THIS_PTR address_xlation.paddress2, 1, ((Bit8u *) &val16) + 1);
|
|
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID,
|
|
BX_CPU_THIS_PTR address_xlation.paddress2, 1, BX_WRITE, ((Bit8u*) &val16)+1);
|
|
#else
|
|
BX_MEM(0)->writePhysicalPage(BX_CPU_THIS,
|
|
BX_CPU_THIS_PTR address_xlation.paddress1, 1, ((Bit8u *) &val16) + 1);
|
|
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID,
|
|
BX_CPU_THIS_PTR address_xlation.paddress1, 1, BX_WRITE, ((Bit8u*) &val16)+1);
|
|
BX_MEM(0)->writePhysicalPage(BX_CPU_THIS,
|
|
BX_CPU_THIS_PTR address_xlation.paddress2, 1, &val16);
|
|
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID,
|
|
BX_CPU_THIS_PTR address_xlation.paddress2, 1, BX_WRITE, (Bit8u*) &val16);
|
|
#endif
|
|
}
|
|
}
|
|
|
|
void BX_CPP_AttrRegparmN(1)
|
|
BX_CPU_C::write_RMW_virtual_dword(Bit32u val32)
|
|
{
|
|
if (BX_CPU_THIS_PTR address_xlation.pages > 2) {
|
|
// Pages > 2 means it stores a host address for direct access.
|
|
Bit32u *hostAddr = (Bit32u *) BX_CPU_THIS_PTR address_xlation.pages;
|
|
WriteHostDWordToLittleEndian(hostAddr, val32);
|
|
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID,
|
|
BX_CPU_THIS_PTR address_xlation.paddress1, 4, BX_WRITE, (Bit8u*) &val32);
|
|
}
|
|
else if (BX_CPU_THIS_PTR address_xlation.pages == 1) {
|
|
BX_MEM(0)->writePhysicalPage(BX_CPU_THIS,
|
|
BX_CPU_THIS_PTR address_xlation.paddress1, 4, &val32);
|
|
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID,
|
|
BX_CPU_THIS_PTR address_xlation.paddress1, 4, BX_WRITE, (Bit8u*) &val32);
|
|
}
|
|
else {
|
|
#ifdef BX_LITTLE_ENDIAN
|
|
BX_MEM(0)->writePhysicalPage(BX_CPU_THIS,
|
|
BX_CPU_THIS_PTR address_xlation.paddress1,
|
|
BX_CPU_THIS_PTR address_xlation.len1,
|
|
&val32);
|
|
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID,
|
|
BX_CPU_THIS_PTR address_xlation.paddress1,
|
|
BX_CPU_THIS_PTR address_xlation.len1, BX_WRITE, (Bit8u*) &val32);
|
|
BX_MEM(0)->writePhysicalPage(BX_CPU_THIS,
|
|
BX_CPU_THIS_PTR address_xlation.paddress2,
|
|
BX_CPU_THIS_PTR address_xlation.len2,
|
|
((Bit8u *) &val32) + BX_CPU_THIS_PTR address_xlation.len1);
|
|
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID,
|
|
BX_CPU_THIS_PTR address_xlation.paddress2,
|
|
BX_CPU_THIS_PTR address_xlation.len2, BX_WRITE,
|
|
((Bit8u *) &val32) + BX_CPU_THIS_PTR address_xlation.len1);
|
|
#else
|
|
BX_MEM(0)->writePhysicalPage(BX_CPU_THIS,
|
|
BX_CPU_THIS_PTR address_xlation.paddress1,
|
|
BX_CPU_THIS_PTR address_xlation.len1,
|
|
((Bit8u *) &val32) + (4 - BX_CPU_THIS_PTR address_xlation.len1));
|
|
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID,
|
|
BX_CPU_THIS_PTR address_xlation.paddress1,
|
|
BX_CPU_THIS_PTR address_xlation.len1, BX_WRITE,
|
|
((Bit8u *) &val32) + (4 - BX_CPU_THIS_PTR address_xlation.len1));
|
|
BX_MEM(0)->writePhysicalPage(BX_CPU_THIS,
|
|
BX_CPU_THIS_PTR address_xlation.paddress2,
|
|
BX_CPU_THIS_PTR address_xlation.len2,
|
|
&val32);
|
|
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID,
|
|
BX_CPU_THIS_PTR address_xlation.paddress2,
|
|
BX_CPU_THIS_PTR address_xlation.len2, BX_WRITE, (Bit8u*) &val32);
|
|
#endif
|
|
}
|
|
}
|
|
|
|
void BX_CPP_AttrRegparmN(1)
|
|
BX_CPU_C::write_RMW_virtual_qword(Bit64u val64)
|
|
{
|
|
if (BX_CPU_THIS_PTR address_xlation.pages > 2) {
|
|
// Pages > 2 means it stores a host address for direct access.
|
|
Bit64u *hostAddr = (Bit64u *) BX_CPU_THIS_PTR address_xlation.pages;
|
|
WriteHostQWordToLittleEndian(hostAddr, val64);
|
|
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID,
|
|
BX_CPU_THIS_PTR address_xlation.paddress1, 8, BX_WRITE, (Bit8u*) &val64);
|
|
}
|
|
else if (BX_CPU_THIS_PTR address_xlation.pages == 1) {
|
|
BX_MEM(0)->writePhysicalPage(BX_CPU_THIS,
|
|
BX_CPU_THIS_PTR address_xlation.paddress1, 8, &val64);
|
|
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID,
|
|
BX_CPU_THIS_PTR address_xlation.paddress1, 8, BX_WRITE, (Bit8u*) &val64);
|
|
}
|
|
else {
|
|
#ifdef BX_LITTLE_ENDIAN
|
|
BX_MEM(0)->writePhysicalPage(BX_CPU_THIS,
|
|
BX_CPU_THIS_PTR address_xlation.paddress1,
|
|
BX_CPU_THIS_PTR address_xlation.len1,
|
|
&val64);
|
|
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID,
|
|
BX_CPU_THIS_PTR address_xlation.paddress1,
|
|
BX_CPU_THIS_PTR address_xlation.len1, BX_WRITE, (Bit8u*) &val64);
|
|
BX_MEM(0)->writePhysicalPage(BX_CPU_THIS,
|
|
BX_CPU_THIS_PTR address_xlation.paddress2,
|
|
BX_CPU_THIS_PTR address_xlation.len2,
|
|
((Bit8u *) &val64) + BX_CPU_THIS_PTR address_xlation.len1);
|
|
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID,
|
|
BX_CPU_THIS_PTR address_xlation.paddress2,
|
|
BX_CPU_THIS_PTR address_xlation.len2, BX_WRITE,
|
|
((Bit8u *) &val64) + BX_CPU_THIS_PTR address_xlation.len1);
|
|
#else
|
|
BX_MEM(0)->writePhysicalPage(BX_CPU_THIS,
|
|
BX_CPU_THIS_PTR address_xlation.paddress1,
|
|
BX_CPU_THIS_PTR address_xlation.len1,
|
|
((Bit8u *) &val64) + (8 - BX_CPU_THIS_PTR address_xlation.len1));
|
|
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID,
|
|
BX_CPU_THIS_PTR address_xlation.paddress1,
|
|
BX_CPU_THIS_PTR address_xlation.len1, BX_WRITE,
|
|
((Bit8u *) &val64) + (8 - BX_CPU_THIS_PTR address_xlation.len1));
|
|
BX_MEM(0)->writePhysicalPage(BX_CPU_THIS,
|
|
BX_CPU_THIS_PTR address_xlation.paddress2,
|
|
BX_CPU_THIS_PTR address_xlation.len2,
|
|
&val64);
|
|
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID,
|
|
BX_CPU_THIS_PTR address_xlation.paddress2,
|
|
BX_CPU_THIS_PTR address_xlation.len2, BX_WRITE, (Bit8u*) &val64);
|
|
#endif
|
|
}
|
|
}
|
|
|
|
//
|
|
// Write data to new stack, these methods are required for emulation
|
|
// correctness but not performance critical.
|
|
//
|
|
|
|
// assuming the write happens in legacy mode
|
|
void BX_CPU_C::write_new_stack_word_32(bx_segment_reg_t *seg, Bit32u offset, unsigned curr_pl, Bit16u data)
|
|
{
|
|
Bit32u laddr;
|
|
|
|
BX_ASSERT(BX_CPU_THIS_PTR cpu_mode != BX_MODE_LONG_64);
|
|
|
|
if (seg->cache.valid & SegAccessWOK4G) {
|
|
accessOK:
|
|
laddr = (Bit32u)(seg->cache.u.segment.base + offset);
|
|
#if BX_SupportGuest2HostTLB
|
|
unsigned tlbIndex = BX_TLB_INDEX_OF(laddr, 1);
|
|
Bit32u lpf = AlignedAccessLPFOf32(laddr, 1);
|
|
bx_TLB_entry *tlbEntry = &BX_CPU_THIS_PTR TLB.entry[tlbIndex];
|
|
if (tlbEntry->lpf == lpf) {
|
|
// See if the TLB entry privilege level allows us write access
|
|
// from this CPL.
|
|
if (tlbEntry->accessBits & (0x10 << CPL)) {
|
|
bx_hostpageaddr_t hostPageAddr = tlbEntry->hostPageAddr;
|
|
Bit32u pageOffset = PAGE_OFFSET(laddr);
|
|
BX_INSTR_LIN_ACCESS(BX_CPU_ID, laddr, tlbEntry->ppf | pageOffset, 2, BX_WRITE);
|
|
BX_DBG_LIN_MEMORY_ACCESS(BX_CPU_ID, laddr,
|
|
tlbEntry->ppf | pageOffset, 2, curr_pl, BX_WRITE, (Bit8u*) &data);
|
|
Bit16u *hostAddr = (Bit16u*) (hostPageAddr | pageOffset);
|
|
#if BX_SUPPORT_ICACHE
|
|
pageWriteStampTable.decWriteStamp(tlbEntry->ppf);
|
|
#endif
|
|
WriteHostWordToLittleEndian(hostAddr, data);
|
|
return;
|
|
}
|
|
}
|
|
#endif
|
|
#if BX_CPU_LEVEL >= 4 && BX_SUPPORT_ALIGNMENT_CHECK
|
|
if (BX_CPU_THIS_PTR alignment_check() && curr_pl == 3) {
|
|
if (laddr & 1) {
|
|
BX_ERROR(("write_new_stack_word_32(): #AC misaligned access"));
|
|
exception(BX_AC_EXCEPTION, 0, 0);
|
|
}
|
|
}
|
|
#endif
|
|
access_write_linear(laddr, 2, curr_pl, (void *) &data);
|
|
return;
|
|
}
|
|
|
|
if (seg->cache.valid & SegAccessWOK) {
|
|
if (offset < seg->cache.u.segment.limit_scaled)
|
|
goto accessOK;
|
|
}
|
|
write_virtual_checks(seg, offset, 2);
|
|
goto accessOK;
|
|
}
|
|
|
|
// assuming the write happens in legacy mode
|
|
void BX_CPU_C::write_new_stack_dword_32(bx_segment_reg_t *seg, Bit32u offset, unsigned curr_pl, Bit32u data)
|
|
{
|
|
Bit32u laddr;
|
|
|
|
BX_ASSERT(BX_CPU_THIS_PTR cpu_mode != BX_MODE_LONG_64);
|
|
|
|
if (seg->cache.valid & SegAccessWOK4G) {
|
|
accessOK:
|
|
laddr = (Bit32u)(seg->cache.u.segment.base + offset);
|
|
#if BX_SupportGuest2HostTLB
|
|
unsigned tlbIndex = BX_TLB_INDEX_OF(laddr, 3);
|
|
Bit32u lpf = AlignedAccessLPFOf32(laddr, 3);
|
|
bx_TLB_entry *tlbEntry = &BX_CPU_THIS_PTR TLB.entry[tlbIndex];
|
|
if (tlbEntry->lpf == lpf) {
|
|
// See if the TLB entry privilege level allows us write access
|
|
// from this CPL.
|
|
if (tlbEntry->accessBits & (0x10 << CPL)) {
|
|
bx_hostpageaddr_t hostPageAddr = tlbEntry->hostPageAddr;
|
|
Bit32u pageOffset = PAGE_OFFSET(laddr);
|
|
BX_INSTR_LIN_ACCESS(BX_CPU_ID, laddr, tlbEntry->ppf | pageOffset, 4, BX_WRITE);
|
|
BX_DBG_LIN_MEMORY_ACCESS(BX_CPU_ID, laddr,
|
|
tlbEntry->ppf | pageOffset, 4, curr_pl, BX_WRITE, (Bit8u*) &data);
|
|
Bit32u *hostAddr = (Bit32u*) (hostPageAddr | pageOffset);
|
|
#if BX_SUPPORT_ICACHE
|
|
pageWriteStampTable.decWriteStamp(tlbEntry->ppf);
|
|
#endif
|
|
WriteHostDWordToLittleEndian(hostAddr, data);
|
|
return;
|
|
}
|
|
}
|
|
#endif
|
|
#if BX_CPU_LEVEL >= 4 && BX_SUPPORT_ALIGNMENT_CHECK
|
|
if (BX_CPU_THIS_PTR alignment_check() && curr_pl == 3) {
|
|
if (laddr & 3) {
|
|
BX_ERROR(("write_new_stack_dword_32(): #AC misaligned access"));
|
|
exception(BX_AC_EXCEPTION, 0, 0);
|
|
}
|
|
}
|
|
#endif
|
|
access_write_linear(laddr, 4, curr_pl, (void *) &data);
|
|
return;
|
|
}
|
|
|
|
if (seg->cache.valid & SegAccessWOK) {
|
|
if (offset < (seg->cache.u.segment.limit_scaled-2))
|
|
goto accessOK;
|
|
}
|
|
write_virtual_checks(seg, offset, 4);
|
|
goto accessOK;
|
|
}
|