620 lines
14 KiB
C++
620 lines
14 KiB
C++
/////////////////////////////////////////////////////////////////////////
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// $Id$
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001-2017 The Bochs Project
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA
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/////////////////////////////////////////////////////////////////////////
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#define NEED_CPU_REG_SHORTCUTS 1
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#include "bochs.h"
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#include "cpu.h"
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#define LOG_THIS BX_CPU_THIS_PTR
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SHLD_EdGdM(bxInstruction_c *i)
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{
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unsigned count;
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unsigned of, cf;
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bx_address eaddr = BX_CPU_RESOLVE_ADDR(i);
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Bit32u op1_32 = read_RMW_virtual_dword(i->seg(), eaddr);
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if (i->getIaOpcode() == BX_IA_SHLD_EdGd)
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count = CL;
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else // BX_IA_SHLD_EdGdIb
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count = i->Ib();
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count &= 0x1f; // use only 5 LSB's
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if (count) {
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Bit32u op2_32 = BX_READ_32BIT_REG(i->src());
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Bit32u result_32 = (op1_32 << count) | (op2_32 >> (32 - count));
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write_RMW_linear_dword(result_32);
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SET_FLAGS_OSZAPC_LOGIC_32(result_32);
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cf = (op1_32 >> (32 - count)) & 0x1;
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of = cf ^ (result_32 >> 31); // of = cf ^ result31
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SET_FLAGS_OxxxxC(of, cf);
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}
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SHLD_EdGdR(bxInstruction_c *i)
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{
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Bit32u op1_32, op2_32, result_32;
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unsigned count;
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unsigned of, cf;
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if (i->getIaOpcode() == BX_IA_SHLD_EdGd)
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count = CL;
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else // BX_IA_SHLD_EdGdIb
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count = i->Ib();
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count &= 0x1f; // use only 5 LSB's
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if (!count) {
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BX_CLEAR_64BIT_HIGH(i->dst()); // always clear upper part of the register
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}
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else {
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op1_32 = BX_READ_32BIT_REG(i->dst());
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op2_32 = BX_READ_32BIT_REG(i->src());
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result_32 = (op1_32 << count) | (op2_32 >> (32 - count));
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BX_WRITE_32BIT_REGZ(i->dst(), result_32);
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SET_FLAGS_OSZAPC_LOGIC_32(result_32);
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cf = (op1_32 >> (32 - count)) & 0x1;
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of = cf ^ (result_32 >> 31); // of = cf ^ result31
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SET_FLAGS_OxxxxC(of, cf);
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}
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SHRD_EdGdM(bxInstruction_c *i)
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{
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unsigned count;
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unsigned cf, of;
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bx_address eaddr = BX_CPU_RESOLVE_ADDR(i);
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Bit32u op1_32 = read_RMW_virtual_dword(i->seg(), eaddr);
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if (i->getIaOpcode() == BX_IA_SHRD_EdGd)
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count = CL;
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else // BX_IA_SHRD_EdGdIb
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count = i->Ib();
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count &= 0x1f; // use only 5 LSB's
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if (count) {
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Bit32u op2_32 = BX_READ_32BIT_REG(i->src());
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Bit32u result_32 = (op2_32 << (32 - count)) | (op1_32 >> count);
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write_RMW_linear_dword(result_32);
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SET_FLAGS_OSZAPC_LOGIC_32(result_32);
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cf = (op1_32 >> (count - 1)) & 0x1;
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of = ((result_32 << 1) ^ result_32) >> 31; // of = result30 ^ result31
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SET_FLAGS_OxxxxC(of, cf);
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}
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SHRD_EdGdR(bxInstruction_c *i)
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{
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Bit32u op1_32, op2_32, result_32;
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unsigned count;
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unsigned cf, of;
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if (i->getIaOpcode() == BX_IA_SHRD_EdGd)
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count = CL;
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else // BX_IA_SHRD_EdGdIb
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count = i->Ib();
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count &= 0x1f; // use only 5 LSB's
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if (!count) {
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BX_CLEAR_64BIT_HIGH(i->dst()); // always clear upper part of the register
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}
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else {
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op1_32 = BX_READ_32BIT_REG(i->dst());
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op2_32 = BX_READ_32BIT_REG(i->src());
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result_32 = (op2_32 << (32 - count)) | (op1_32 >> count);
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BX_WRITE_32BIT_REGZ(i->dst(), result_32);
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SET_FLAGS_OSZAPC_LOGIC_32(result_32);
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cf = (op1_32 >> (count - 1)) & 0x1;
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of = ((result_32 << 1) ^ result_32) >> 31; // of = result30 ^ result31
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SET_FLAGS_OxxxxC(of, cf);
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}
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ROL_EdM(bxInstruction_c *i)
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{
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unsigned count;
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bx_address eaddr = BX_CPU_RESOLVE_ADDR(i);
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Bit32u op1_32 = read_RMW_virtual_dword(i->seg(), eaddr);
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if (i->getIaOpcode() == BX_IA_ROL_Ed)
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count = CL;
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else
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count = i->Ib();
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count &= 0x1f;
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if (count) {
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Bit32u result_32 = (op1_32 << count) | (op1_32 >> (32 - count));
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write_RMW_linear_dword(result_32);
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unsigned bit0 = (result_32 & 0x1);
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unsigned bit31 = (result_32 >> 31);
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// of = cf ^ result31
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SET_FLAGS_OxxxxC(bit0 ^ bit31, bit0);
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}
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ROL_EdR(bxInstruction_c *i)
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{
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Bit32u op1_32, result_32;
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unsigned count;
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unsigned bit0, bit31;
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if (i->getIaOpcode() == BX_IA_ROL_Ed)
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count = CL;
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else
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count = i->Ib();
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count &= 0x1f;
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if (!count) {
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BX_CLEAR_64BIT_HIGH(i->dst()); // always clear upper part of the register
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}
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else {
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op1_32 = BX_READ_32BIT_REG(i->dst());
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result_32 = (op1_32 << count) | (op1_32 >> (32 - count));
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BX_WRITE_32BIT_REGZ(i->dst(), result_32);
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bit0 = (result_32 & 0x1);
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bit31 = (result_32 >> 31);
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// of = cf ^ result31
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SET_FLAGS_OxxxxC(bit0 ^ bit31, bit0);
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}
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ROR_EdM(bxInstruction_c *i)
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{
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unsigned count;
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unsigned bit31, bit30;
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bx_address eaddr = BX_CPU_RESOLVE_ADDR(i);
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Bit32u op1_32 = read_RMW_virtual_dword(i->seg(), eaddr);
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if (i->getIaOpcode() == BX_IA_ROR_Ed)
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count = CL;
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else
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count = i->Ib();
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count &= 0x1f;
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if (count) {
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Bit32u result_32 = (op1_32 >> count) | (op1_32 << (32 - count));
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write_RMW_linear_dword(result_32);
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bit31 = (result_32 >> 31) & 1;
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bit30 = (result_32 >> 30) & 1;
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// of = result30 ^ result31
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SET_FLAGS_OxxxxC(bit30 ^ bit31, bit31);
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}
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ROR_EdR(bxInstruction_c *i)
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{
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Bit32u op1_32, result_32;
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unsigned count;
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unsigned bit31, bit30;
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if (i->getIaOpcode() == BX_IA_ROR_Ed)
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count = CL;
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else
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count = i->Ib();
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count &= 0x1f;
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if (!count) {
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BX_CLEAR_64BIT_HIGH(i->dst()); // always clear upper part of the register
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}
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else {
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op1_32 = BX_READ_32BIT_REG(i->dst());
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result_32 = (op1_32 >> count) | (op1_32 << (32 - count));
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BX_WRITE_32BIT_REGZ(i->dst(), result_32);
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bit31 = (result_32 >> 31) & 1;
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bit30 = (result_32 >> 30) & 1;
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// of = result30 ^ result31
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SET_FLAGS_OxxxxC(bit30 ^ bit31, bit31);
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}
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::RCL_EdM(bxInstruction_c *i)
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{
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Bit32u result_32;
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unsigned count;
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unsigned cf, of;
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bx_address eaddr = BX_CPU_RESOLVE_ADDR(i);
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Bit32u op1_32 = read_RMW_virtual_dword(i->seg(), eaddr);
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if (i->getIaOpcode() == BX_IA_RCL_Ed)
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count = CL;
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else
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count = i->Ib();
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count &= 0x1f;
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if (!count) {
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BX_NEXT_INSTR(i);
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}
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Bit32u temp_CF = getB_CF();
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if (count==1) {
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result_32 = (op1_32 << 1) | temp_CF;
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}
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else {
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result_32 = (op1_32 << count) | (temp_CF << (count - 1)) |
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(op1_32 >> (33 - count));
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}
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write_RMW_linear_dword(result_32);
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cf = (op1_32 >> (32 - count)) & 0x1;
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of = cf ^ (result_32 >> 31); // of = cf ^ result31
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SET_FLAGS_OxxxxC(of, cf);
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::RCL_EdR(bxInstruction_c *i)
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{
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Bit32u result_32;
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unsigned count;
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unsigned cf, of;
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if (i->getIaOpcode() == BX_IA_RCL_Ed)
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count = CL;
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else
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count = i->Ib();
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count &= 0x1f;
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if (!count) {
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BX_CLEAR_64BIT_HIGH(i->dst()); // always clear upper part of the register
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BX_NEXT_INSTR(i);
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}
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Bit32u op1_32 = BX_READ_32BIT_REG(i->dst());
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Bit32u temp_CF = getB_CF();
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if (count==1) {
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result_32 = (op1_32 << 1) | temp_CF;
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}
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else {
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result_32 = (op1_32 << count) | (temp_CF << (count - 1)) |
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(op1_32 >> (33 - count));
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}
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BX_WRITE_32BIT_REGZ(i->dst(), result_32);
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cf = (op1_32 >> (32 - count)) & 0x1;
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of = cf ^ (result_32 >> 31); // of = cf ^ result31
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SET_FLAGS_OxxxxC(of, cf);
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::RCR_EdM(bxInstruction_c *i)
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{
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Bit32u result_32;
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unsigned count;
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unsigned cf, of;
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bx_address eaddr = BX_CPU_RESOLVE_ADDR(i);
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Bit32u op1_32 = read_RMW_virtual_dword(i->seg(), eaddr);
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if (i->getIaOpcode() == BX_IA_RCR_Ed)
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count = CL;
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else
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count = i->Ib();
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count &= 0x1f;
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if (!count) {
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BX_NEXT_INSTR(i);
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}
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Bit32u temp_CF = getB_CF();
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if (count==1) {
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result_32 = (op1_32 >> 1) | (temp_CF << 31);
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}
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else {
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result_32 = (op1_32 >> count) | (temp_CF << (32 - count)) |
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(op1_32 << (33 - count));
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}
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write_RMW_linear_dword(result_32);
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cf = (op1_32 >> (count - 1)) & 0x1;
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of = ((result_32 << 1) ^ result_32) >> 31; // of = result30 ^ result31
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SET_FLAGS_OxxxxC(of, cf);
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::RCR_EdR(bxInstruction_c *i)
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{
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Bit32u result_32;
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unsigned count;
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unsigned cf, of;
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if (i->getIaOpcode() == BX_IA_RCR_Ed)
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count = CL;
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else
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count = i->Ib();
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count &= 0x1f;
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if (!count) {
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BX_CLEAR_64BIT_HIGH(i->dst()); // always clear upper part of the register
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BX_NEXT_INSTR(i);
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}
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Bit32u op1_32 = BX_READ_32BIT_REG(i->dst());
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Bit32u temp_CF = getB_CF();
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if (count==1) {
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result_32 = (op1_32 >> 1) | (temp_CF << 31);
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}
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else {
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result_32 = (op1_32 >> count) | (temp_CF << (32 - count)) |
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(op1_32 << (33 - count));
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}
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BX_WRITE_32BIT_REGZ(i->dst(), result_32);
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cf = (op1_32 >> (count - 1)) & 0x1;
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of = ((result_32 << 1) ^ result_32) >> 31; // of = result30 ^ result31
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SET_FLAGS_OxxxxC(of, cf);
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SHL_EdM(bxInstruction_c *i)
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{
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unsigned count;
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unsigned cf, of;
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bx_address eaddr = BX_CPU_RESOLVE_ADDR(i);
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Bit32u op1_32 = read_RMW_virtual_dword(i->seg(), eaddr);
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if (i->getIaOpcode() == BX_IA_SHL_Ed)
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count = CL;
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else
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count = i->Ib();
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count &= 0x1f;
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if (count) {
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/* count < 32, since only lower 5 bits used */
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Bit32u result_32 = (op1_32 << count);
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write_RMW_linear_dword(result_32);
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cf = (op1_32 >> (32 - count)) & 0x1;
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of = cf ^ (result_32 >> 31);
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SET_FLAGS_OSZAPC_LOGIC_32(result_32);
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SET_FLAGS_OxxxxC(of, cf);
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}
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SHL_EdR(bxInstruction_c *i)
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{
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unsigned count;
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if (i->getIaOpcode() == BX_IA_SHL_Ed)
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count = CL;
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else
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count = i->Ib();
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count &= 0x1f;
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if (!count) {
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BX_CLEAR_64BIT_HIGH(i->dst()); // always clear upper part of the register
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}
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else {
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Bit32u op1_32 = BX_READ_32BIT_REG(i->dst());
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/* count < 32, since only lower 5 bits used */
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Bit32u result_32 = (op1_32 << count);
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BX_WRITE_32BIT_REGZ(i->dst(), result_32);
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unsigned cf = (op1_32 >> (32 - count)) & 0x1;
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unsigned of = cf ^ (result_32 >> 31);
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SET_FLAGS_OSZAPC_LOGIC_32(result_32);
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SET_FLAGS_OxxxxC(of, cf);
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}
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SHR_EdM(bxInstruction_c *i)
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{
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unsigned count;
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bx_address eaddr = BX_CPU_RESOLVE_ADDR(i);
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Bit32u op1_32 = read_RMW_virtual_dword(i->seg(), eaddr);
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if (i->getIaOpcode() == BX_IA_SHR_Ed)
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count = CL;
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else
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count = i->Ib();
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count &= 0x1f;
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if (count) {
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Bit32u result_32 = (op1_32 >> count);
|
|
|
|
write_RMW_linear_dword(result_32);
|
|
|
|
unsigned cf = (op1_32 >> (count - 1)) & 0x1;
|
|
// note, that of == result31 if count == 1 and
|
|
// of == 0 if count >= 2
|
|
unsigned of = ((result_32 << 1) ^ result_32) >> 31;
|
|
|
|
SET_FLAGS_OSZAPC_LOGIC_32(result_32);
|
|
SET_FLAGS_OxxxxC(of, cf);
|
|
}
|
|
|
|
BX_NEXT_INSTR(i);
|
|
}
|
|
|
|
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SHR_EdR(bxInstruction_c *i)
|
|
{
|
|
unsigned count;
|
|
|
|
if (i->getIaOpcode() == BX_IA_SHR_Ed)
|
|
count = CL;
|
|
else
|
|
count = i->Ib();
|
|
|
|
count &= 0x1f;
|
|
|
|
if (!count) {
|
|
BX_CLEAR_64BIT_HIGH(i->dst()); // always clear upper part of the register
|
|
}
|
|
else {
|
|
Bit32u op1_32 = BX_READ_32BIT_REG(i->dst());
|
|
Bit32u result_32 = (op1_32 >> count);
|
|
BX_WRITE_32BIT_REGZ(i->dst(), result_32);
|
|
|
|
unsigned cf = (op1_32 >> (count - 1)) & 0x1;
|
|
// note, that of == result31 if count == 1 and
|
|
// of == 0 if count >= 2
|
|
unsigned of = ((result_32 << 1) ^ result_32) >> 31;
|
|
|
|
SET_FLAGS_OSZAPC_LOGIC_32(result_32);
|
|
SET_FLAGS_OxxxxC(of, cf);
|
|
}
|
|
|
|
BX_NEXT_INSTR(i);
|
|
}
|
|
|
|
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SAR_EdM(bxInstruction_c *i)
|
|
{
|
|
unsigned count;
|
|
|
|
bx_address eaddr = BX_CPU_RESOLVE_ADDR(i);
|
|
|
|
Bit32u op1_32 = read_RMW_virtual_dword(i->seg(), eaddr);
|
|
|
|
if (i->getIaOpcode() == BX_IA_SAR_Ed)
|
|
count = CL;
|
|
else
|
|
count = i->Ib();
|
|
|
|
count &= 0x1f;
|
|
|
|
if (count) {
|
|
/* count < 32, since only lower 5 bits used */
|
|
Bit32u result_32 = ((Bit32s) op1_32) >> count;
|
|
|
|
write_RMW_linear_dword(result_32);
|
|
|
|
SET_FLAGS_OSZAPC_LOGIC_32(result_32);
|
|
unsigned cf = (op1_32 >> (count - 1)) & 1;
|
|
SET_FLAGS_OxxxxC(0, cf); /* signed overflow cannot happen in SAR instruction */
|
|
}
|
|
|
|
BX_NEXT_INSTR(i);
|
|
}
|
|
|
|
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SAR_EdR(bxInstruction_c *i)
|
|
{
|
|
unsigned count;
|
|
|
|
if (i->getIaOpcode() == BX_IA_SAR_Ed)
|
|
count = CL;
|
|
else
|
|
count = i->Ib();
|
|
|
|
count &= 0x1f;
|
|
|
|
if (!count) {
|
|
BX_CLEAR_64BIT_HIGH(i->dst()); // always clear upper part of the register
|
|
}
|
|
else {
|
|
Bit32u op1_32 = BX_READ_32BIT_REG(i->dst());
|
|
|
|
/* count < 32, since only lower 5 bits used */
|
|
Bit32u result_32 = ((Bit32s) op1_32) >> count;
|
|
|
|
BX_WRITE_32BIT_REGZ(i->dst(), result_32);
|
|
|
|
SET_FLAGS_OSZAPC_LOGIC_32(result_32);
|
|
unsigned cf = (op1_32 >> (count - 1)) & 1;
|
|
SET_FLAGS_OxxxxC(0, cf); /* signed overflow cannot happen in SAR instruction */
|
|
}
|
|
|
|
BX_NEXT_INSTR(i);
|
|
}
|