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Bochs/bochs/cpu
History
Stanislav Shwartsman 2ab50c7d66 solve code duplication between different cpudb models
2021-02-16 18:57:49 +00:00
..
avx
regen Makefile include dependencies for CPU and internal debugger
2021-01-30 20:17:15 +00:00
cpudb
solve code duplication between different cpudb models
2021-02-16 18:57:49 +00:00
decoder
fix MSVC warnings
2021-02-11 15:05:06 +00:00
fpu
regen Makefile include dependencies for CPU and internal debugger
2021-01-30 20:17:15 +00:00
3dnow.cc
cleanup return value of all instruction handlers
2018-02-16 07:57:32 +00:00
access2.cc
! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
2021-01-30 08:35:35 +00:00
access.cc
! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
2021-01-30 08:35:35 +00:00
access.h
keep def of YMM/ZMM register even if AVX or EVEX are not compiled in and let reading/writing them to MEM
2018-04-04 19:31:56 +00:00
aes.cc
avoid gcc 7.3 warning
2018-05-27 19:09:59 +00:00
apic.cc
fixed some MSVC wannings in CPU code
2021-02-08 13:06:44 +00:00
apic.h
! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
2021-01-30 08:35:35 +00:00
arith8.cc
cleanup return value of all instruction handlers
2018-02-16 07:57:32 +00:00
arith16.cc
cleanup return value of all instruction handlers
2018-02-16 07:57:32 +00:00
arith32.cc
cleanup return value of all instruction handlers
2018-02-16 07:57:32 +00:00
arith64.cc
cleanup return value of all instruction handlers
2018-02-16 07:57:32 +00:00
bcd.cc
cleanup return value of all instruction handlers
2018-02-16 07:57:32 +00:00
bit16.cc
! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
2021-01-30 08:35:35 +00:00
bit32.cc
! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
2021-01-30 08:35:35 +00:00
bit64.cc
! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
2021-01-30 08:35:35 +00:00
bit.cc
cleanup return value of all instruction handlers
2018-02-16 07:57:32 +00:00
bmi32.cc
! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
2021-01-30 08:35:35 +00:00
bmi64.cc
! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
2021-01-30 08:35:35 +00:00
call_far.cc
Add initial implementation of the CET (Control Flow Enforcement Technology) emulation according to SDM071
2019-12-20 07:42:07 +00:00
cet.cc
! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
2021-01-30 08:35:35 +00:00
cpu.cc
fix MSVC warnings
2021-02-11 15:05:06 +00:00
cpu.h
fixed some MSVC wannings in CPU code
2021-02-08 13:06:44 +00:00
cpuid.cc
solve code duplication between different cpudb models
2021-02-16 18:57:49 +00:00
cpuid.h
solve code duplication between different cpudb models
2021-02-16 18:57:49 +00:00
cpustats.h
…
crc32.cc
change a bit more defines to const with type
2019-12-26 16:48:33 +00:00
crregs.cc
fixed some MSVC wannings in CPU code
2021-02-08 13:06:44 +00:00
crregs.h
! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
2021-01-30 08:35:35 +00:00
ctrl_xfer16.cc
Add initial implementation of the CET (Control Flow Enforcement Technology) emulation according to SDM071
2019-12-20 07:42:07 +00:00
ctrl_xfer32.cc
Add initial implementation of the CET (Control Flow Enforcement Technology) emulation according to SDM071
2019-12-20 07:42:07 +00:00
ctrl_xfer64.cc
Add initial implementation of the CET (Control Flow Enforcement Technology) emulation according to SDM071
2019-12-20 07:42:07 +00:00
ctrl_xfer_pro.cc
Add initial implementation of the CET (Control Flow Enforcement Technology) emulation according to SDM071
2019-12-20 07:42:07 +00:00
data_xfer8.cc
cleanup return value of all instruction handlers
2018-02-16 07:57:32 +00:00
data_xfer16.cc
cleanup return value of all instruction handlers
2018-02-16 07:57:32 +00:00
data_xfer32.cc
cleanup return value of all instruction handlers
2018-02-16 07:57:32 +00:00
data_xfer64.cc
cleanup return value of all instruction handlers
2018-02-16 07:57:32 +00:00
debugstuff.cc
fixed compilation without bochs debugger
2021-01-30 20:31:03 +00:00
descriptor.h
! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
2021-01-30 08:35:35 +00:00
event.cc
! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
2021-01-30 08:35:35 +00:00
exception.cc
fixed some MSVC wannings in CPU code
2021-02-08 13:06:44 +00:00
faststring.cc
remove pc_system.h from bochs.h and include it only where required
2021-01-30 18:29:28 +00:00
flag_ctrl_pro.cc
! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
2021-01-30 08:35:35 +00:00
flag_ctrl.cc
cleanup return value of all instruction handlers
2018-02-16 07:57:32 +00:00
fpu_emu.cc
cleanup return value of all instruction handlers
2018-02-16 07:57:32 +00:00
generic_cpuid.cc
solve code duplication between different cpudb models
2021-02-16 18:57:49 +00:00
generic_cpuid.h
solve code duplication between different cpudb models
2021-02-16 18:57:49 +00:00
gf2.cc
cleanup return value of all instruction handlers
2018-02-16 07:57:32 +00:00
i387.h
coding style changes, tab2space, macro2function or macro2const
2019-10-17 19:23:27 +00:00
icache.cc
fix compilation with SMP enabled
2021-01-31 14:03:28 +00:00
icache.h
! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
2021-01-30 08:35:35 +00:00
init.cc
remove siminterface.h from bochs.h and include it only where required
2021-01-30 19:40:18 +00:00
io.cc
! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
2021-01-30 08:35:35 +00:00
iret.cc
Add initial implementation of the CET (Control Flow Enforcement Technology) emulation according to SDM071
2019-12-20 07:42:07 +00:00
jmp_far.cc
Add initial implementation of the CET (Control Flow Enforcement Technology) emulation according to SDM071
2019-12-20 07:42:07 +00:00
lazy_flags.h
! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
2021-01-30 08:35:35 +00:00
load.cc
Fixed buffer overflow in LOAD_Wdq method when MXCSR.MM=1 -> thanks new gcc10 warning
2020-10-03 09:37:06 +00:00
logical8.cc
cleanup return value of all instruction handlers
2018-02-16 07:57:32 +00:00
logical16.cc
more faststring cleanup
2019-10-14 14:54:07 +00:00
logical32.cc
more faststring cleanup
2019-10-14 14:54:07 +00:00
logical64.cc
cleanup return value of all instruction handlers
2018-02-16 07:57:32 +00:00
Makefile.in
regen Makefile include dependencies for CPU and internal debugger
2021-01-30 20:17:15 +00:00
mmx.cc
fixed behavior of MMX PSRAW/PSRAD instructions when shift count is zero - still has to invalidate x87 tags for dest register
2020-12-15 20:05:54 +00:00
msr.cc
! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
2021-01-30 08:35:35 +00:00
msr.h
Protection Keys: Implemented Supervisor-Mode Protection Keys (PKS)
2020-05-29 12:35:30 +00:00
mult8.cc
cleanup return value of all instruction handlers
2018-02-16 07:57:32 +00:00
mult16.cc
cleanup return value of all instruction handlers
2018-02-16 07:57:32 +00:00
mult32.cc
cleanup return value of all instruction handlers
2018-02-16 07:57:32 +00:00
mult64.cc
extract Bit128 arithmetic to separate wide_int.cc/wide_int.h compiled independently of long mode emulation
2020-05-19 16:01:23 +00:00
mwait.cc
remove siminterface.h from bochs.h and include it only where required
2021-01-30 19:40:18 +00:00
paging.cc
remove bochs-memory.h from bochs.h and include it only where required
2021-01-30 20:13:34 +00:00
proc_ctrl.cc
remove gui.h from bochs.h and include it only where required
2021-01-30 18:47:25 +00:00
protect_ctrl.cc
applying SF patch #545 Speling fixes
2019-12-09 16:29:23 +00:00
rdrand.cc
VMX: Fix RDRAND/RDSEED VMEXIT Instruction-Information Field
2019-10-24 20:12:00 +00:00
ret_far.cc
Add initial implementation of the CET (Control Flow Enforcement Technology) emulation according to SDM071
2019-12-20 07:42:07 +00:00
scalar_arith.h
fix MSVC warnings
2021-02-11 15:05:06 +00:00
segment_ctrl_pro.cc
! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
2021-01-30 08:35:35 +00:00
segment_ctrl.cc
VMX: save guest CET state to VMCS on vmexit
2019-12-27 13:02:30 +00:00
sha.cc
fixed bug in SHA256RNDS2 instruction - wrong order of dwords in result
2019-12-19 19:20:13 +00:00
shift8.cc
cleanup return value of all instruction handlers
2018-02-16 07:57:32 +00:00
shift16.cc
cleanup return value of all instruction handlers
2018-02-16 07:57:32 +00:00
shift32.cc
cleanup return value of all instruction handlers
2018-02-16 07:57:32 +00:00
shift64.cc
cleanup return value of all instruction handlers
2018-02-16 07:57:32 +00:00
simd_compare.h
…
simd_int.h
fixed some MSVC wannings in CPU code
2021-02-08 13:06:44 +00:00
simd_pfp.h
…
smm.cc
! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
2021-01-30 08:35:35 +00:00
smm.h
…
soft_int.cc
cleanup return value of all instruction handlers
2018-02-16 07:57:32 +00:00
sse_move.cc
cleanup return value of all instruction handlers
2018-02-16 07:57:32 +00:00
sse_pfp.cc
cleanup return value of all instruction handlers
2018-02-16 07:57:32 +00:00
sse_rcp.cc
cleanup return value of all instruction handlers
2018-02-16 07:57:32 +00:00
sse_string.cc
! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
2021-01-30 08:35:35 +00:00
sse.cc
cleanup return value of all instruction handlers
2018-02-16 07:57:32 +00:00
stack16.cc
cleanup return value of all instruction handlers
2018-02-16 07:57:32 +00:00
stack32.cc
cleanup return value of all instruction handlers
2018-02-16 07:57:32 +00:00
stack64.cc
cleanup return value of all instruction handlers
2018-02-16 07:57:32 +00:00
stack.cc
split Bochs CPU TLB to DTLB and ITLB to avoid aliasing conflicts between them. ~5% speedup measured
2019-12-09 18:37:02 +00:00
stack.h
Add initial implementation of the CET (Control Flow Enforcement Technology) emulation according to SDM071
2019-12-20 07:42:07 +00:00
string.cc
remove pc_system.h from bochs.h and include it only where required
2021-01-30 18:29:28 +00:00
svm.cc
! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
2021-01-30 08:35:35 +00:00
svm.h
! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
2021-01-30 08:35:35 +00:00
tasking.cc
! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
2021-01-30 08:35:35 +00:00
tlb.h
fixed some MSVC wannings in CPU code
2021-02-08 13:06:44 +00:00
todo
Add initial implementation of the CET (Control Flow Enforcement Technology) emulation according to SDM071
2019-12-20 07:42:07 +00:00
vapic.cc
remove bochs-memory.h from bochs.h and include it only where required
2021-01-30 20:13:34 +00:00
vm8086.cc
Add initial implementation of the CET (Control Flow Enforcement Technology) emulation according to SDM071
2019-12-20 07:42:07 +00:00
vmcs.cc
! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
2021-01-30 08:35:35 +00:00
vmexit.cc
remove pc_system.h from bochs.h and include it only where required
2021-01-30 18:29:28 +00:00
vmfunc.cc
cleanup return value of all instruction handlers
2018-02-16 07:57:32 +00:00
vmx.cc
! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
2021-01-30 08:35:35 +00:00
vmx.h
! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
2021-01-30 08:35:35 +00:00
wide_int.cc
extract Bit128 arithmetic to separate wide_int.cc/wide_int.h compiled independently of long mode emulation
2020-05-19 16:01:23 +00:00
wide_int.h
extract Bit128 arithmetic to separate wide_int.cc/wide_int.h compiled independently of long mode emulation
2020-05-19 16:01:23 +00:00
xmm.h
implemented AVX encoded VNNI instructions published in recent SDM - not tested yet
2020-10-03 09:23:28 +00:00
xsave.cc
! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
2021-01-30 08:35:35 +00:00