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Bochs/bochs/cpu/decoder
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Stanislav Shwartsman 086f2779f5 fixed compilation with avx but without EVEX
2020-02-20 05:29:13 +00:00
..
decoder.h
Add initial implementation of the CET (Control Flow Enforcement Technology) emulation according to SDM071
2019-12-20 07:42:07 +00:00
disasm.cc
remove BX_TRUE/BX_FALSE macros, use stdc++ true/false instead
2019-12-09 16:44:36 +00:00
fetchdecode32.cc
fixed compilation with avx but without EVEX
2020-02-20 05:29:13 +00:00
fetchdecode64.cc
use enums for assign_srcs error output - help with debugging unexpected #UD cases
2019-12-27 19:34:32 +00:00
fetchdecode_avx.h
fixed bug in instruction decoding - regression before release
2019-11-20 20:18:22 +00:00
fetchdecode_evex.h
AVX512: VPBROADCASTB/W/D/Q with GPR source are only reg/reg
2019-12-21 18:29:51 +00:00
fetchdecode_opmap_0f3a.h
fix decoder: SHA1RNDS4 instruction should be with no SSE prefix
2019-12-27 13:08:20 +00:00
fetchdecode_opmap_0f38.h
Add initial implementation of the CET (Control Flow Enforcement Technology) emulation according to SDM071
2019-12-20 07:42:07 +00:00
fetchdecode_opmap.h
Add initial implementation of the CET (Control Flow Enforcement Technology) emulation according to SDM071
2019-12-20 07:42:07 +00:00
fetchdecode_x87.h
fix disasm of FISTTP opcodes
2017-12-19 20:36:55 +00:00
fetchdecode_xop.h
enable yet another Bochs new decoder. It is a bit slower than old one but it is much more extendable so adding new opcode won't be nightmare anymore
2019-02-16 15:23:24 +00:00
fetchdecode.h
use enums for assign_srcs error output - help with debugging unexpected #UD cases
2019-12-27 19:34:32 +00:00
ia_opcodes.def
SHA: SHA instructions in 128-bit memory operand require to be explicitly aligned
2019-12-27 14:24:43 +00:00
ia_opcodes.h
…
instr.h
Add initial implementation of the CET (Control Flow Enforcement Technology) emulation according to SDM071
2019-12-20 07:42:07 +00:00