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277 Commits

Author SHA1 Message Date
Stanislav Shwartsman
247aca0956 implement VMX SUPPORT FOR THE IA32_SPEC_CTRL MSR announced in 319433-052 
bugfix: "shadow stack prematurely busy" secondary vmexit control was wrongly mapped into bit2 insetad of bit3
 2024-04-27 09:44:48 +03:00
Stanislav Shwartsman
c4689f284c fix spurious read of potentially non-existing SECONDARY_VMEXIT_CTRLS 2024-01-27 18:38:14 +02:00
Stanislav Shwartsman
ae61538847 create classes for Vmexec controls for robustness 2024-01-27 18:04:00 +02:00
Stanislav Shwartsman
035fb1edaa create class for Pin-Based VMEXEC controls for robustness 
create class for Vmentry controls for robustness
create class for Vmexit controls for robustness
 2024-01-27 15:14:29 +02:00
Stanislav Shwartsman
38b1bbf4ff Implemented VMX 'Shadow Stack Prematurely Busy' and secondary VMEXIT controls 2024-01-27 13:34:51 +02:00
Shwartsman
e4deec2aca cleanups and code updates before thinking of INIT redirection implementation for AMD SVM 2024-01-14 12:55:43 +02:00
Stanislav Shwartsman
b2cf7860dc VMX: Implemented MSR IA32_SPEC_CTRL Virtualization VMX extension 
fixed few typos in error messages
 2024-01-13 21:58:23 +02:00
Stanislav Shwartsman
6977fc05d9 VMX: adjust RFLAGS saved into guest state on VMEXIT according to VMX documentation: 
For APIC-access VM exits and for VM exits caused by:
- EPT violations
- EPT misconfigurations
- page-modification log-full events or
- SPP-related events
the value saved depends on whether the VM exit occurred during delivery of an event through the IDT ...

also handle RFlags saved if VMEXIT was caused directly by an event that would normally be delivered through the IDT

should fix #215
 2024-01-12 20:01:53 +02:00
Stanislav Shwartsman
6b48d6e33f resolution for SF bug #1460 Incorrect "Blocking by NMI" bit when handling NMI VM-exit 
as well as
resolution for Test stuck due to incorrect Virtual NMI handling #211
which appear the same problem
 2024-01-12 00:19:44 +02:00
Stanislav Shwartsman
ec7ef85ed9 exclude cpuid.h from cpu.h to reduce compilation dependency 2023-12-29 21:27:24 +02:00
Shwartsman
fc919cd132 use true/false instead of 0/1 for bool in the cpu code 2023-12-19 20:44:56 +02:00
Stanislav Shwartsman
54831068df
implement RDMSRLIST/WRMSRLIST instructions (+related VMX extensions) (#176) 2023-12-16 21:59:34 +02:00
Shwartsman
3c857f2ad1 make APIC from static object to dynamic so many cc files won't need to be dependent on apic.h 2023-11-28 11:08:42 +02:00
Shwartsman
8dd9649389 fixed compilation for VMX=1 X86_64=1 
updated (c) for many files
 2023-11-28 10:36:56 +02:00
Shwartsman
4efcabb1a1 reduce code duplication with making new simpler to use physical access methods 2023-11-28 10:24:11 +02:00
Shwartsman
cc4f594ede implemented process-posted-interrupts VMX extension 2023-11-27 20:15:00 +02:00
Stanislav Shwartsman
4ee9d37a5f prevent access to non-existing VMCS fields 2023-11-26 20:29:56 +02:00
Shwartsman
b013b389ea fixed code duplication, extract some code to functions 
make special phy memory read methods which help to write cleaner code
 2023-11-26 18:25:54 +02:00
Stanislav Shwartsman
280303d76c
initial code for UINTR implementation (#138) 
First step into implementing UINTR - User Level Interrupts ISA extension
To be continued

---------

Co-authored-by: Stanislav Shwartsman <sshwarts@users.sourceforge.net>
 2023-11-25 16:43:47 +02:00
Shwartsman
62c2c877d0 rename VMEXIT controls in Bochs code to match their actual names and meaning 2023-11-23 19:58:08 +02:00
Shwartsman
6b5928f522 rename constants VMX_VM_EXEC_CTRL1 -> VMX_PIN_BASED_VMEXEC_CTRL for more correct naming 2023-11-23 19:51:17 +02:00
Shwartsman
4d08659621 Implement 'Tertiary VMEXEC Controls' for VMX 
Currently none of the controls were not enabled, all clear but infra is here
 2023-11-23 19:38:59 +02:00
Shwartsman
591e2aa79f bugfix: when CET was not compiled in the emulation behavior of non-CET CPU was altered 
CET 'change' some x86 behavior
For example EPTP[7] become not-reserved and write to it not fail anymore
VMX doesn't check error code for CP exception if CET is enabled
These behaviors these changed even when CET was not compiled in
 2023-11-21 15:35:49 +02:00
Stanislav Shwartsman
c1c102ab04 coding style, cleanups and optimizations 2023-11-19 20:31:05 +02:00
Stanislav Shwartsman
60cc8020e8 Fixed VMCS_GUEST_PENDING_DBG_EXCEPTIONS saved on VMEXIT (should be cleared after most of VMEXITs) 2023-11-13 20:02:03 +02:00
Stanislav Shwartsman
52d57a422c add VMEXIT reasons to enum, they not supported by Bochs but better to be listed for completion 2023-10-13 21:04:43 +03:00
Stanislav Shwartsman
44eea71f37
implemented SM3 instructions (#84) 
add rol/ror methods to scalar_arith.h and use in more places

---------

Co-authored-by: Stanislav Shwartsman <sshwarts@users.sourceforge.net>
 2023-10-07 21:34:04 +03:00
Stanislav Shwartsman
6481d24e06 Another cleaner way to implemented fix by rei141 
from Fixes in VM Entry Checks for Guest Segment Registers #51

Correction in checks for Code Segment (CS):
Previously, the DPL of CS was incorrectly compared with its own RPL.
According to Intel SDM, Vol. 3C, Chapter 27.3.1.2, for non-conforming code segments (type 9 or 11), the DPL of CS should be equal to the DPL of SS.
And for conforming code segments (type 13 or 15), the DPL of CS cannot be greater than the DPL of SS.

This way VMCS is not accessed multiple times which is important for some usages
 2023-08-20 19:33:37 +03:00
Stanislav Shwartsman
58c047c6d6 Merge part of PR by rei141 
Fixes in VM Entry Checks for Guest Segment Registers #51

Correction in Type range checks for DS, ES, FS, GS:
The original code erroneously applied the check for types less than 11, excluding types equal to 11.
This is not in accordance with Intel SDM, Vol. 3C, Chapter 27.3.1.2, which states that the check should include types equal to or less than 11.
This fix corrects this by including types equal to or less than 11 in the check.
 2023-08-20 18:52:53 +03:00
Shwartsman
bd51ec5f83 fixed SF #1456 Bochs does not handle NMI blocking correctly when running virtual machines 2023-04-08 08:36:28 +03:00
Stanislav Shwartsman
1e4f1624c8 remove trailing whitespace from source files 2022-08-23 21:46:04 +03:00
Stanislav Shwartsman
fac15a7d03 updates to MTF code: 
if VMEntry delivered an event of event happen right after VMEntry - MTF becomes pending immediatelly
 2022-08-16 21:37:36 +03:00
Stanislav Shwartsman
b946570838 implemented VMX Monitor Trap Flag handling 2022-08-16 21:17:05 +03:00
Stanislav Shwartsman
97a2cdd85f update VMEXIT reasons according to published docs 
update list of trap-like VMEXITs
 2022-08-13 23:25:10 +03:00
Stanislav Shwartsman
f052c0f5b2 - VMX: Implemented missing SPP Misconfiguration condition (odd bits of SPP PTE entry are reserved) 
- VMX: Fix SPP walk and VMCS access memory type to WB (match memory type listed in IA32_VMX_BASIC MSR)
 2022-07-31 19:57:38 +03:00
Stanislav Shwartsman
3f65841714
use boolean constants true/false instead of 0/1 (#26) 
* use boolean constants true/false instead of 0/1

* fix code comment

Co-authored-by: Stanislav Shwartsman <sshwarts@users.sourceforge.net>
 2022-07-30 18:38:22 +03:00
Stanislav Shwartsman
f44f4ae753
MBE (Mode Based Execution Control) emulation (#22) 
* MBE (Mode Based Execution Control) emulation
 2022-07-30 15:26:47 +03:00
Satoshi Tanda
0ae5e67894
Fix that the blocking by SMI bit maybe set when a VM-exit ends outside SMM (#15) 
* Fix that the blocking by SMI bit is set

The blocking by SMI bit of the guest interruptibility state VMCS should
not be set unless the VM-exit ends in SMM. This only happens under the
dual-monitor treatment, which is not implemented in Bochs.

* Remove trailing whitespaces
 2022-07-23 19:36:31 +03:00
Stanislav Shwartsman
7b2bb50722 fixed VMX exit qualification info for INVEPT/INVVPID/INVPCID instructions 2021-07-23 10:13:48 +00:00
Stanislav Shwartsman
097c8f13b9 minor coding style modifications 2021-05-25 06:27:49 +00:00
Stanislav Shwartsman
1bf18b8aae ! CPUID: Added TigerLake CPU definition (features CET and CLWB support) 
- CPU code refactor, remove uses of bx_bool datatype and use C++ classic bool instead.
  This enable better compiler optimizations and reduce binary size
 2021-01-30 08:35:35 +00:00
Stanislav Shwartsman
4023b640d6 Protection Keys: Implemented Supervisor-Mode Protection Keys (PKS) 2020-05-29 12:35:30 +00:00
Stanislav Shwartsman
ea6b0c766c added more VMX reasons to enum according to Intel SDM 2020-01-03 17:35:02 +00:00
Stanislav Shwartsman
f56e1aab86 VMX: save CET state to VMCS only if CET is supported 2019-12-28 15:18:55 +00:00
Stanislav Shwartsman
a2be16873c VMX: save guest CET state to VMCS on vmexit 2019-12-27 13:02:30 +00:00
Stanislav Shwartsman
edcdce927c added ability to configure hidden VMCS field mapping through CPUID 2019-12-22 18:53:07 +00:00
Stanislav Shwartsman
553a9471d1 fixed push error check for VMX injecting event vector 21 on configuration that doesn't support CET 2019-12-20 13:27:18 +00:00
Stanislav Shwartsman
f90e5f4f44 Add initial implementation of the CET (Control Flow Enforcement Technology) emulation according to SDM071 
Only missing items (to be added soon):
  - Supervisor Shadow Stack EPT Control is not implemented yet
  - SMM placing for SSP
Currently have to be added manually to some CPUID model, for example to ICL-U
To enable configure with --enable-cet
 2019-12-20 07:42:07 +00:00
Stanislav Shwartsman
7090abe1a1 fix one more place with incorrect detection of x2apic MSR space. use function instead of magic numbers in all places 2019-12-10 21:07:19 +00:00
Stanislav Shwartsman
e35fcd1782 clarify err message 2019-12-10 20:38:45 +00:00