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237 Commits

Author SHA1 Message Date
Stanislav Shwartsman
1bf18b8aae ! CPUID: Added TigerLake CPU definition (features CET and CLWB support) 
- CPU code refactor, remove uses of bx_bool datatype and use C++ classic bool instead.
  This enable better compiler optimizations and reduce binary size
 2021-01-30 08:35:35 +00:00
Stanislav Shwartsman
4023b640d6 Protection Keys: Implemented Supervisor-Mode Protection Keys (PKS) 2020-05-29 12:35:30 +00:00
Stanislav Shwartsman
ea6b0c766c added more VMX reasons to enum according to Intel SDM 2020-01-03 17:35:02 +00:00
Stanislav Shwartsman
f56e1aab86 VMX: save CET state to VMCS only if CET is supported 2019-12-28 15:18:55 +00:00
Stanislav Shwartsman
a2be16873c VMX: save guest CET state to VMCS on vmexit 2019-12-27 13:02:30 +00:00
Stanislav Shwartsman
edcdce927c added ability to configure hidden VMCS field mapping through CPUID 2019-12-22 18:53:07 +00:00
Stanislav Shwartsman
553a9471d1 fixed push error check for VMX injecting event vector 21 on configuration that doesn't support CET 2019-12-20 13:27:18 +00:00
Stanislav Shwartsman
f90e5f4f44 Add initial implementation of the CET (Control Flow Enforcement Technology) emulation according to SDM071 
Only missing items (to be added soon):
  - Supervisor Shadow Stack EPT Control is not implemented yet
  - SMM placing for SSP
Currently have to be added manually to some CPUID model, for example to ICL-U
To enable configure with --enable-cet
 2019-12-20 07:42:07 +00:00
Stanislav Shwartsman
7090abe1a1 fix one more place with incorrect detection of x2apic MSR space. use function instead of magic numbers in all places 2019-12-10 21:07:19 +00:00
Stanislav Shwartsman
e35fcd1782 clarify err message 2019-12-10 20:38:45 +00:00
Stanislav Shwartsman
12d228abde split vmx initialization to multiple methods for better code readability, improve VMX error messages 2019-12-08 20:46:51 +00:00
Stanislav Shwartsman
d766cc8112 implemented SCA (Side-Channel-Attack) Prevention reporting and corresponding MSR registers, enabled for Icelake-U CPU definition 2019-10-26 20:09:30 +00:00
Stanislav Shwartsman
27e23ad1eb give priority for VMX induced #UD in INVPCID and RDTSCP instructions over all other exeptions that could be generated there 2019-10-24 19:49:25 +00:00
Stanislav Shwartsman
eec720c62b convert bochs.h macros to inline functions with strong types 2019-10-16 20:46:00 +00:00
Stanislav Shwartsman
85780d939a extract MONITOR/MWAIT stuff to separate trsnlation unit 2019-05-25 18:32:17 +00:00
Stanislav Shwartsman
55d2dc6b0c add some CPUID and VMCS definitions from latest SDM 2019-05-22 18:22:22 +00:00
Stanislav Shwartsman
cd79d22113 fixes for 32-bit mode only compilation 2019-02-16 19:42:04 +00:00
Stanislav Shwartsman
264b797363 fixed compilation without VMX=2 2019-01-03 06:28:15 +00:00
Stanislav Shwartsman
773f1b7e42 cleanup return value of all instruction handlers 2018-02-16 07:57:32 +00:00
Stanislav Shwartsman
afc2ee6bfd Implemented SPP: EPT-Based Subpage Protection. Cleaned code duplication between FXSAVE/FXRSTORE and XSAVE/XRSTOR (save/restore of SSE code is the same) 2018-01-27 21:20:33 +00:00
Stanislav Shwartsman
5439647254 small change to extract ia_opcodes.h from instr.h to dedicated file. this would remove compilation dep of all files on ia_opcodes.h (now called ia_opcdes.def). regenerating dep ober all files in Makefiles.in 2017-10-19 21:27:25 +00:00
Stanislav Shwartsman
69f27439db added new cpuid flags mentioned in new Intel SDM future extensions rev030 doc 2017-10-13 20:27:52 +00:00
Stanislav Shwartsman
b2fdbd1274 added Skylake-X model to CPUDB -> with EVEX and AVX512 support 2017-08-09 20:36:17 +00:00
Stanislav Shwartsman
555bb8f8b6 updates to prev commit 2017-06-01 08:41:41 +00:00
Stanislav Shwartsman
6ab4fd597b implement another form of AR field packing used in SKL, in addition on present NHM format 2017-06-01 08:31:20 +00:00
Stanislav Shwartsman
22e9051716 implemented correct VM-exit instruction information for INVPCID, RDRAND/RDSEED and XSAVES/XRSTORS instruction Vmexits 2017-05-31 13:16:49 +00:00
Stanislav Shwartsman
99bfbdf139 add xss exiting bitmap to save/restore 2017-03-16 20:23:49 +00:00
Stanislav Shwartsman
3a033fa6db implemented xsaves/xrstors extensions (supported by Intel Skylake core and AMD Ryzen) 2017-03-15 21:44:15 +00:00
Stanislav Shwartsman
1543034fb7 in the latest intel docs PCOMMIT CPUID bit doesn't exists anymore 2016-10-02 11:56:18 +00:00
Stanislav Shwartsman
009bc7388b implement more correct vmentry to shutdown sanity check 2016-05-03 19:29:22 +00:00
Stanislav Shwartsman
6a35ceb51a fixed err msg description 2016-05-03 19:24:52 +00:00
Stanislav Shwartsman
405d7776e8 fixed typo 2016-05-03 19:20:26 +00:00
Stanislav Shwartsman
adc143684b implemented Intel architecture extensions published in recently published SDM 058: 
! Implemented UMIP: User Mode Instruction Prevention (don't allow execution of SLDT/SIDT/SGDT/STR/SMSW with CPL>0)
! Implemented RDPID instruction

Bugfixes in RDPKRU/WRPKRU instructions implementation (Protection Keys feature)
 2016-04-15 11:35:32 +00:00
Stanislav Shwartsman
ea3c1c77eb added vmx consistency checks related to recently implemented support for vm-entering shutdown/wait-for-sipi state 2015-10-09 06:18:14 +00:00
Stanislav Shwartsman
8d13b61319 implemented TSC Scaling VMX feature according to timestamp-counter for virtualization whitepaper published by Intel 2015-09-30 18:44:01 +00:00
Stanislav Shwartsman
dd1ec977c2 enable vmenter to wait-for-sipi state 2015-09-28 18:42:05 +00:00
Stanislav Shwartsman
ea255b5bf7 fixed VMCS memory type calculation 2015-07-12 20:10:43 +00:00
Stanislav Shwartsman
129db3bfaf fixed typo in the list of the vmcs exits 2015-07-12 15:26:34 +00:00
Stanislav Shwartsman
28c19ecec7 more interfaces to VMCS Mapping class 2015-07-06 20:14:56 +00:00
Stanislav Shwartsman
5fe1423ab6 introducr new class for VMCS mapping so it can be customized per cpuid 2015-07-06 18:46:57 +00:00
Stanislav Shwartsman
b468316250 re-style old resolve macros after resolve function inlining 2015-05-16 21:06:59 +00:00
Stanislav Shwartsman
9f18573740 Rename BX_CPU_CALL_METHODR to BX_CPU_RESOLVE_ADDR and introduce special cases BX_CPU_RESOLVE_ADDR_64 (for 64-bit mode only) and BX_CPU_RESOLVE_ADDR_32 (for 32-bit mode only) 2015-05-11 19:23:09 +00:00
Stanislav Shwartsman
0d79c5f986 Implemented Page Modification Logging VMX feature 2015-05-06 19:55:44 +00:00
Stanislav Shwartsman
239b1ae684 added missed vmexit reason to debug print 2015-04-18 19:25:58 +00:00
Stanislav Shwartsman
1e1c893041 introduce new 64bit packed register type and implement pat/mtrr and mmx registers through it 2015-02-23 21:17:33 +00:00
Stanislav Shwartsman
0917d12e8b memory type report for physical accesses and RMW acccesses. todo: consider also pat 2015-02-22 21:26:26 +00:00
Stanislav Shwartsman
7a3e340e6d implement memory type calculation by mtrr. todo: memory type from page tables 2015-02-20 21:50:59 +00:00
Stanislav Shwartsman
e16c6eb30c preparations and interface definition for memory type support 2015-02-19 20:23:08 +00:00
Stanislav Shwartsman
5e6955c5e7 Major rewrite of memory access methods to avoid massive code duplication and enable inlining of memory access methods 2015-01-25 20:55:10 +00:00
Stanislav Shwartsman
1c027b17d7 some lazy flags handling optimizations 2014-10-22 17:49:12 +00:00