Stanislav Shwartsman
0cba8b66c9
more robust handling of SVM VMCB host ptr
2021-07-23 09:30:17 +00:00
Stanislav Shwartsman
7cc9cffeed
remove siminterface.h from bochs.h and include it only where required
2021-01-30 19:40:18 +00:00
Stanislav Shwartsman
4023b640d6
Protection Keys: Implemented Supervisor-Mode Protection Keys (PKS)
2020-05-29 12:35:30 +00:00
Stanislav Shwartsman
b891789c3d
implemented (experimental) TSC Adjust MSR
2020-05-21 19:58:16 +00:00
Stanislav Shwartsman
6b691257dd
fixed compilation with VMX off
2020-01-17 11:55:59 +00:00
Stanislav Shwartsman
a24b562e32
now when bios knows to set msr ia32_feature_ctrl, no need to initialize from reset code
2020-01-15 17:18:10 +00:00
Stanislav Shwartsman
5620a4968b
set msr IA32_FEATURE_CTRL lock bit to ensure VMX is enabled - normally this should be done in Bios but init.cc can w/a
2020-01-11 07:04:44 +00:00
Stanislav Shwartsman
bac9104f73
fixed compilation of init.cc for old CPU models
2020-01-03 05:29:45 +00:00
Stanislav Shwartsman
f90e5f4f44
Add initial implementation of the CET (Control Flow Enforcement Technology) emulation according to SDM071
...
Only missing items (to be added soon):
- Supervisor Shadow Stack EPT Control is not implemented yet
- SMM placing for SSP
Currently have to be added manually to some CPUID model, for example to ICL-U
To enable configure with --enable-cet
2019-12-20 07:42:07 +00:00
Stanislav Shwartsman
4b66fecaad
split Bochs CPU TLB to DTLB and ITLB to avoid aliasing conflicts between them. ~5% speedup measured
2019-12-09 18:37:02 +00:00
Stanislav Shwartsman
0c75e0beaf
extract xcr0_support bits calculation to a function
2019-12-06 09:23:28 +00:00
Stanislav Shwartsman
c098ab7de1
take msr.ia32_spec_ctrl out of @ifdef CPU_LEVEL=6
2019-10-26 20:17:41 +00:00
Stanislav Shwartsman
d766cc8112
implemented SCA (Side-Channel-Attack) Prevention reporting and corresponding MSR registers, enabled for Icelake-U CPU definition
2019-10-26 20:09:30 +00:00
Stanislav Shwartsman
9bc7faf493
dump all supported CPU fetures into Bochs log from CPUID object
2019-01-05 20:17:39 +00:00
Stanislav Shwartsman
a51eb1cc39
added more debug info for TLB through param tree, update year in the (c)
2017-03-31 07:34:08 +00:00
Stanislav Shwartsman
172b0106ac
imvent a bochs feature for AMD TCE and enable EFER.TCE bit
2017-03-15 22:52:08 +00:00
Stanislav Shwartsman
3a033fa6db
implemented xsaves/xrstors extensions (supported by Intel Skylake core and AMD Ryzen)
2017-03-15 21:44:15 +00:00
Stanislav Shwartsman
bd24d7fb17
fixed reset value of xcr0 as published in latest Intel SDM update
2016-10-08 15:17:12 +00:00
Stanislav Shwartsman
46e932d04e
fixed INIT cpu state according to clarification published in SDM rev059
2016-07-17 19:16:58 +00:00
Stanislav Shwartsman
e4832af5ab
clean pkeys when not enabled to avoid side-effects
2016-03-19 21:15:56 +00:00
Stanislav Shwartsman
bcb36e81fa
experimental implementation of protection keys paging extension published in SDM rev054. to enable configure with --enable-protection-keys
2016-03-02 20:44:42 +00:00
Stanislav Shwartsman
591039e588
removed debug print
2016-02-21 20:14:15 +00:00
Stanislav Shwartsman
9557cafcef
revertng commit #12854 because it broke MT simulation with debugger enabled. Until investigted.
2015-12-20 22:44:54 +00:00
Stanislav Shwartsman
ad52e15860
added few tlb specific cpustat counters
2015-09-28 19:09:32 +00:00
Stanislav Shwartsman
3a0dff9b36
fixed Bochs compiled for 386 with FPU enabled
2015-06-10 20:36:46 +00:00
Stanislav Shwartsman
c43ea147bf
~1% emulation speedup by skipping pageWriteStamp check for stack writes.
...
For now the optimization is supported only when no SMP is compiled in because it doesn't handle cross-modifying code.
The current stack page will cache also current pageWriteStamp for that page and could skip pageWriteStamp access if possible.
Any code fetch access missing trace cache will invalidate current stack page.
Code fetch accesses from another SMP threads should do the same to support SMP.
Next step:
- support SMP
- support pageWriteStamp access skipping for all other memory writes from all segments
2015-05-23 19:34:59 +00:00
Stanislav Shwartsman
080ceb8293
don't crash when running on 386 with no FPU model
2015-03-27 21:39:24 +00:00
Stanislav Shwartsman
b74036d2d8
another try to fix the weird compilation error
2015-02-26 20:34:24 +00:00
Stanislav Shwartsman
4e859202a1
attemp to fix compilation issue
2015-02-25 19:43:47 +00:00
Stanislav Shwartsman
1e1c893041
introduce new 64bit packed register type and implement pat/mtrr and mmx registers through it
2015-02-23 21:17:33 +00:00
Stanislav Shwartsman
0917d12e8b
memory type report for physical accesses and RMW acccesses. todo: consider also pat
2015-02-22 21:26:26 +00:00
Stanislav Shwartsman
e16c6eb30c
preparations and interface definition for memory type support
2015-02-19 20:23:08 +00:00
Stanislav Shwartsman
b5a603c8c7
fixed %d->%u format found by cppcheck (patch by Maxim Derbasov)
2015-01-25 21:24:13 +00:00
Stanislav Shwartsman
5e6955c5e7
Major rewrite of memory access methods to avoid massive code duplication and enable inlining of memory access methods
2015-01-25 20:55:10 +00:00
Stanislav Shwartsman
6e254743c1
Added missing sanity check.
...
The sanity check would help to detect real Bochs crash issue under Win x64 with MSDEV
configure script under Mingw env decided that SIZEOF_INT_P == 4 which is terribly wrong for 64-bit host.
2014-11-04 19:00:20 +00:00
Stanislav Shwartsman
1c027b17d7
some lazy flags handling optimizations
2014-10-22 17:49:12 +00:00
Stanislav Shwartsman
8d1e3b2ac1
Added statistics collection infrastructure in Bochs and
...
implemented important CPU statistics which were used for Bochs CPU model performance analysis.
old statistics code from paging.cc and cpu.cc is replaced with new infrastructure.
In order to enale statitics collection in Bochs CPU:
- Enable statistics @ compilation time in cpu/cpustats.h
- Dump statistics periodically by adding -dumpstats N into Bochs command line
2014-10-14 15:59:10 +00:00
Stanislav Shwartsman
29efae3be3
adjust (c) in several files
2014-08-31 20:05:25 +00:00
Stanislav Shwartsman
9f57e70d5f
Rewritten handling of supported CPUID features to be able to handle large amount of CPU extensions
...
Now enable support for up to 128 CPU extensions and could easily extend it more
Also reduce memory footprint for bx_ia_opcodes.h arrays
2014-08-31 18:39:18 +00:00
Stanislav Shwartsman
bc5af269b7
Fix some more code duplication with sclaar_arith.h
...
Do not clear IA32_FEATURE_CTRL MSR on soft reset (will clear the VMX lock bit)
On real HW XSAVE/XRSTOR which is not 4-byte aligned cause #AC(0) intead of #GP(0) when alignment check is enabled
2014-03-02 16:40:13 +00:00
Stanislav Shwartsman
ca2793ac76
Debugger: fixed param tree access to 64-bit variables (need to use get64() instead of get())
...
Debugger: if AVX-512 if not supported by current configuration do not print high256 of vector registers and zmm15..zmm31 in AVX command
Implement VBROADCASTF64x4, VBROADCASTF32x4, VBROADCASTFI64x4, VBROADCASTI32x4 AVX-512 instructions
Fetchdecode optimizations and bugfixes
2013-12-05 19:17:16 +00:00
Stanislav Shwartsman
37d6403681
typo fix 2
2013-11-30 19:57:03 +00:00
Stanislav Shwartsman
32c91015a7
typo fix
2013-11-30 19:55:10 +00:00
Stanislav Shwartsman
09254eb474
avx512 implementation fixes and next steps
2013-10-08 18:31:18 +00:00
Stanislav Shwartsman
8881800b1f
enable avx-512 in init.cc
2013-09-08 19:35:37 +00:00
Stanislav Shwartsman
59c65151f5
various fixes
2013-08-29 19:43:15 +00:00
Stanislav Shwartsman
5d61c19b0b
evex support - step2
2013-08-27 20:47:24 +00:00
Stanislav Shwartsman
2dbe81db51
first infrastructure changes to support EVEX prefix and AVX-512 extensions recently published by Intel
2013-07-26 12:50:56 +00:00
Stanislav Shwartsman
fd71b03353
add some definitions introduced in recent Intel SDM extensions document (rev015)
2013-07-23 20:51:52 +00:00
Stanislav Shwartsman
a277d60d89
implemented vmentering to non-active cpu state
2013-04-09 15:43:15 +00:00
