From his patch file text:
> This patch adds Promise DC2300 VLB IDE Support.
> You may find msdos and win95 drivers on the net. Look for
> P2300W95.ZIP and DC2300VLBIDEver260b.ZIP.
>
> The good news is that now win95 natively sees my cdrom,
> and that the disks are not in msdos compatibility mode any more.
>
> The bad news is that it works only for the first ata interface.
>
> I tested that patch on msdos and win95 only.
>
> Some info on VLB IDE can be found at http://ryston.cz/petr/vlb/
I got Win95 running with 32-bit paging/filesystem using the
recommended driver and these patches. Since the patches did
such a good job bracketing code modifications with a #define,
they might as well become part of the current CVS code.
use getB_CF() etc. getB_CF() and friends are only for a relatively
small number of cases where a true boolean/binary number (0 or 1) is required
rather than 0 or non-0 as is returned by get_CF().
loadSRegLMNominal() which should be used to load a segment register
in long-mode with nominal values which are compatible with existing
checks and expectations for descriptor cache values.
Fixed 64-bit iret to not do a descriptor fetch if SS selector is null.
Also load SS with loadSRegLMNorminal() in the same case.
was not correct (used == 0, rather than s&0xffc == 0). Also,
with a null SS selector, it was fetching the descriptor anyways.
Put more code inside the if (selector != NULL) clause.
For a temporary measure I added the local INIT_64_DESCRIPTOR
from segment_ctrl_pro.cc, and used it in the case that the
SS selector is null. We need to make a real function which
sets a descriptor in long-mode to nominal values. I'm going
to do that next... I can't stand seeing the current hacks. :^)
section title, and less like the grammar that you're supposed to use.
Someone on irc was confused because it was written in uppercase, but then
bochs did not accept the uppercase ATA0-MASTER parameter.
Fixed/updated/cleaned guest2host TLB speedups for Long mode.
I now can boot the Linux x86-64 kernel to the VFS mount message,
using all the accelerations.
these from interfering from a normal compile here's what I did.
In config.h.in (which will generate config.h after a configure),
I added a #define called KPL64Hacks:
#define KPL64Hacks
*After* running configure, you must set this by hand. It will
default to off, so you won't get my hacks in a normal compile.
This will go away soon. There is also a macro just after that
called BailBigRSP(). You don't need to enabled that, but you
can. In many of the instructions which seemed like they could
be hit by the fetchdecode64() process, but which also touched
EIP/ESP, I inserted a macro. Usually this macro expands to nothing.
If you like, you can enabled it, and it will panic if it finds
the upper bits of RIP/RSP set. This helped me find bugs.
Also, I cleaned up the emulation in ctrl_xfer{8,16,32}.cc.
There were some really old legacy code snippets which directly
accessed operands on the stack with access_linear. Lots of
ugly code instead of just pop_32() etc. Cleaning those up,
minimized the number of instructions which directly manipulate
the stack pointer, which should help in refining 64-bit support.
user can turn on/off use of native host specific inline asm
statements. By default, this option is enabled, so you only
need it to disable inline asms in your compile for now.
Currently only on x86+GCC environments, will inline asm()
statements be used. Eventually, other platforms could specify
some asm()s; probably for endian issues such as byte-swapping
and unaligned memory accesses. On x86, there are some inline
asm()s which do the arithmetic EFLAGS processing so that the
lazy flags handling is somewhat bypassed. Eventually, I'll
add more, at least for the more common instructions. This
adds a little extra performance.
giving it Bit32u pointers. On MacOSX for some reason Boolean is set to
unsigned char instead of unsigned int, so it actually cares that we get the
type right.
- return model=2 so that Linux recognizes the processor as having an APIC.
We don't really know what Hammer returns.
- in SetCR4, allow bits 9 and 10 to be written
- added jump to [0x40:0x67] after reset if shutdown status is 0x05. Fixes bug [ 601166 ] CMOS Problem @ "0x0F Index 0x05 data"
- changed various occurences of "mov ax, #0000" by "xor ax, ax"
- fixed serious bugs in EDD function 0x48
- included Volker's rombios recent changes to PCIBIOS
- initialization of DMA controller on POST entry
