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591e2aa79f
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255 Commits

Author SHA1 Message Date
Shwartsman
591e2aa79f bugfix: when CET was not compiled in the emulation behavior of non-CET CPU was altered 
CET 'change' some x86 behavior
For example EPTP[7] become not-reserved and write to it not fail anymore
VMX doesn't check error code for CP exception if CET is enabled
These behaviors these changed even when CET was not compiled in
 2023-11-21 15:35:49 +02:00
Stanislav Shwartsman
c1c102ab04 coding style, cleanups and optimizations 2023-11-19 20:31:05 +02:00
Stanislav Shwartsman
60cc8020e8 Fixed VMCS_GUEST_PENDING_DBG_EXCEPTIONS saved on VMEXIT (should be cleared after most of VMEXITs) 2023-11-13 20:02:03 +02:00
Stanislav Shwartsman
52d57a422c add VMEXIT reasons to enum, they not supported by Bochs but better to be listed for completion 2023-10-13 21:04:43 +03:00
Stanislav Shwartsman
44eea71f37
implemented SM3 instructions (#84) 
add rol/ror methods to scalar_arith.h and use in more places

---------

Co-authored-by: Stanislav Shwartsman <sshwarts@users.sourceforge.net>
 2023-10-07 21:34:04 +03:00
Stanislav Shwartsman
6481d24e06 Another cleaner way to implemented fix by rei141 
from Fixes in VM Entry Checks for Guest Segment Registers #51

Correction in checks for Code Segment (CS):
Previously, the DPL of CS was incorrectly compared with its own RPL.
According to Intel SDM, Vol. 3C, Chapter 27.3.1.2, for non-conforming code segments (type 9 or 11), the DPL of CS should be equal to the DPL of SS.
And for conforming code segments (type 13 or 15), the DPL of CS cannot be greater than the DPL of SS.

This way VMCS is not accessed multiple times which is important for some usages
 2023-08-20 19:33:37 +03:00
Stanislav Shwartsman
58c047c6d6 Merge part of PR by rei141 
Fixes in VM Entry Checks for Guest Segment Registers #51

Correction in Type range checks for DS, ES, FS, GS:
The original code erroneously applied the check for types less than 11, excluding types equal to 11.
This is not in accordance with Intel SDM, Vol. 3C, Chapter 27.3.1.2, which states that the check should include types equal to or less than 11.
This fix corrects this by including types equal to or less than 11 in the check.
 2023-08-20 18:52:53 +03:00
Shwartsman
bd51ec5f83 fixed SF #1456 Bochs does not handle NMI blocking correctly when running virtual machines 2023-04-08 08:36:28 +03:00
Stanislav Shwartsman
1e4f1624c8 remove trailing whitespace from source files 2022-08-23 21:46:04 +03:00
Stanislav Shwartsman
fac15a7d03 updates to MTF code: 
if VMEntry delivered an event of event happen right after VMEntry - MTF becomes pending immediatelly
 2022-08-16 21:37:36 +03:00
Stanislav Shwartsman
b946570838 implemented VMX Monitor Trap Flag handling 2022-08-16 21:17:05 +03:00
Stanislav Shwartsman
97a2cdd85f update VMEXIT reasons according to published docs 
update list of trap-like VMEXITs
 2022-08-13 23:25:10 +03:00
Stanislav Shwartsman
f052c0f5b2 - VMX: Implemented missing SPP Misconfiguration condition (odd bits of SPP PTE entry are reserved) 
- VMX: Fix SPP walk and VMCS access memory type to WB (match memory type listed in IA32_VMX_BASIC MSR)
 2022-07-31 19:57:38 +03:00
Stanislav Shwartsman
3f65841714
use boolean constants true/false instead of 0/1 (#26) 
* use boolean constants true/false instead of 0/1

* fix code comment

Co-authored-by: Stanislav Shwartsman <sshwarts@users.sourceforge.net>
 2022-07-30 18:38:22 +03:00
Stanislav Shwartsman
f44f4ae753
MBE (Mode Based Execution Control) emulation (#22) 
* MBE (Mode Based Execution Control) emulation
 2022-07-30 15:26:47 +03:00
Satoshi Tanda
0ae5e67894
Fix that the blocking by SMI bit maybe set when a VM-exit ends outside SMM (#15) 
* Fix that the blocking by SMI bit is set

The blocking by SMI bit of the guest interruptibility state VMCS should
not be set unless the VM-exit ends in SMM. This only happens under the
dual-monitor treatment, which is not implemented in Bochs.

* Remove trailing whitespaces
 2022-07-23 19:36:31 +03:00
Stanislav Shwartsman
7b2bb50722 fixed VMX exit qualification info for INVEPT/INVVPID/INVPCID instructions 2021-07-23 10:13:48 +00:00
Stanislav Shwartsman
097c8f13b9 minor coding style modifications 2021-05-25 06:27:49 +00:00
Stanislav Shwartsman
1bf18b8aae ! CPUID: Added TigerLake CPU definition (features CET and CLWB support) 
- CPU code refactor, remove uses of bx_bool datatype and use C++ classic bool instead.
  This enable better compiler optimizations and reduce binary size
 2021-01-30 08:35:35 +00:00
Stanislav Shwartsman
4023b640d6 Protection Keys: Implemented Supervisor-Mode Protection Keys (PKS) 2020-05-29 12:35:30 +00:00
Stanislav Shwartsman
ea6b0c766c added more VMX reasons to enum according to Intel SDM 2020-01-03 17:35:02 +00:00
Stanislav Shwartsman
f56e1aab86 VMX: save CET state to VMCS only if CET is supported 2019-12-28 15:18:55 +00:00
Stanislav Shwartsman
a2be16873c VMX: save guest CET state to VMCS on vmexit 2019-12-27 13:02:30 +00:00
Stanislav Shwartsman
edcdce927c added ability to configure hidden VMCS field mapping through CPUID 2019-12-22 18:53:07 +00:00
Stanislav Shwartsman
553a9471d1 fixed push error check for VMX injecting event vector 21 on configuration that doesn't support CET 2019-12-20 13:27:18 +00:00
Stanislav Shwartsman
f90e5f4f44 Add initial implementation of the CET (Control Flow Enforcement Technology) emulation according to SDM071 
Only missing items (to be added soon):
  - Supervisor Shadow Stack EPT Control is not implemented yet
  - SMM placing for SSP
Currently have to be added manually to some CPUID model, for example to ICL-U
To enable configure with --enable-cet
 2019-12-20 07:42:07 +00:00
Stanislav Shwartsman
7090abe1a1 fix one more place with incorrect detection of x2apic MSR space. use function instead of magic numbers in all places 2019-12-10 21:07:19 +00:00
Stanislav Shwartsman
e35fcd1782 clarify err message 2019-12-10 20:38:45 +00:00
Stanislav Shwartsman
12d228abde split vmx initialization to multiple methods for better code readability, improve VMX error messages 2019-12-08 20:46:51 +00:00
Stanislav Shwartsman
d766cc8112 implemented SCA (Side-Channel-Attack) Prevention reporting and corresponding MSR registers, enabled for Icelake-U CPU definition 2019-10-26 20:09:30 +00:00
Stanislav Shwartsman
27e23ad1eb give priority for VMX induced #UD in INVPCID and RDTSCP instructions over all other exeptions that could be generated there 2019-10-24 19:49:25 +00:00
Stanislav Shwartsman
eec720c62b convert bochs.h macros to inline functions with strong types 2019-10-16 20:46:00 +00:00
Stanislav Shwartsman
85780d939a extract MONITOR/MWAIT stuff to separate trsnlation unit 2019-05-25 18:32:17 +00:00
Stanislav Shwartsman
55d2dc6b0c add some CPUID and VMCS definitions from latest SDM 2019-05-22 18:22:22 +00:00
Stanislav Shwartsman
cd79d22113 fixes for 32-bit mode only compilation 2019-02-16 19:42:04 +00:00
Stanislav Shwartsman
264b797363 fixed compilation without VMX=2 2019-01-03 06:28:15 +00:00
Stanislav Shwartsman
773f1b7e42 cleanup return value of all instruction handlers 2018-02-16 07:57:32 +00:00
Stanislav Shwartsman
afc2ee6bfd Implemented SPP: EPT-Based Subpage Protection. Cleaned code duplication between FXSAVE/FXRSTORE and XSAVE/XRSTOR (save/restore of SSE code is the same) 2018-01-27 21:20:33 +00:00
Stanislav Shwartsman
5439647254 small change to extract ia_opcodes.h from instr.h to dedicated file. this would remove compilation dep of all files on ia_opcodes.h (now called ia_opcdes.def). regenerating dep ober all files in Makefiles.in 2017-10-19 21:27:25 +00:00
Stanislav Shwartsman
69f27439db added new cpuid flags mentioned in new Intel SDM future extensions rev030 doc 2017-10-13 20:27:52 +00:00
Stanislav Shwartsman
b2fdbd1274 added Skylake-X model to CPUDB -> with EVEX and AVX512 support 2017-08-09 20:36:17 +00:00
Stanislav Shwartsman
555bb8f8b6 updates to prev commit 2017-06-01 08:41:41 +00:00
Stanislav Shwartsman
6ab4fd597b implement another form of AR field packing used in SKL, in addition on present NHM format 2017-06-01 08:31:20 +00:00
Stanislav Shwartsman
22e9051716 implemented correct VM-exit instruction information for INVPCID, RDRAND/RDSEED and XSAVES/XRSTORS instruction Vmexits 2017-05-31 13:16:49 +00:00
Stanislav Shwartsman
99bfbdf139 add xss exiting bitmap to save/restore 2017-03-16 20:23:49 +00:00
Stanislav Shwartsman
3a033fa6db implemented xsaves/xrstors extensions (supported by Intel Skylake core and AMD Ryzen) 2017-03-15 21:44:15 +00:00
Stanislav Shwartsman
1543034fb7 in the latest intel docs PCOMMIT CPUID bit doesn't exists anymore 2016-10-02 11:56:18 +00:00
Stanislav Shwartsman
009bc7388b implement more correct vmentry to shutdown sanity check 2016-05-03 19:29:22 +00:00
Stanislav Shwartsman
6a35ceb51a fixed err msg description 2016-05-03 19:24:52 +00:00
Stanislav Shwartsman
405d7776e8 fixed typo 2016-05-03 19:20:26 +00:00