8 Commits

Author	SHA1	Message	Date
Stanislav Shwartsman	9b958b3a05	allow to select CPU level = 5 from .bochsrc even when Bochs is compiled with CPU_LEVEL=6	2013-04-17 19:46:11 +00:00
Stanislav Shwartsman	bb7a648d91	Major commit ! ... ------------ Implemented SVN nested paging support - the Virtual Box boots perfectly with Nested Paging guest ! A lot of code duplication was added for now - major cleanup will follow later. ! Added AMD Phenom X3 8650 (Toliman) configuration to the CPUDB - this configuration has Nested Paging enabled. Some CPUID modules rework done to enable Toliman configuration. Ckean up 'executable' attribute from all CPU source files.	2012-02-13 23:29:01 +00:00
Stanislav Shwartsman	62d0c8abf7	- Now you could disable x86-64 from .bochsrc so now it is possible to emulate ... 32-bit CPU using Bochs binary compiled with x86-64 support. The commit also fixes some init.cc issues with initialization of SYSCALL/SYSRET MSR in AMD hosts and also includes code reorg.	2011-09-25 17:36:20 +00:00
Stanislav Shwartsman	e2f0880f1c	support more than 32-bit cpu features vector	2011-09-14 20:22:24 +00:00
Stanislav Shwartsman	b8b63ac6ea	compile CPUDB to separate library ... reduce compile-time dependencies	2011-08-18 18:55:22 +00:00
Stanislav Shwartsman	ed9b8478b5	undo RDTSC commit	2011-08-17 21:13:06 +00:00
Stanislav Shwartsman	165e6f0fdf	separate TSC to uniq feature that can be disabled in CPU configuration	2011-08-17 20:57:44 +00:00
Stanislav Shwartsman	0bc93fdc59	added pentium mmx to cpudb. for now only can be enabled when cpu-level=5	2011-08-16 19:04:36 +00:00