Stanislav Shwartsman
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134b23a809
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enable AVX512_CD for Icelake configuration
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2019-12-13 16:48:15 +00:00 |
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Stanislav Shwartsman
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d766cc8112
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implemented SCA (Side-Channel-Attack) Prevention reporting and corresponding MSR registers, enabled for Icelake-U CPU definition
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2019-10-26 20:09:30 +00:00 |
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Stanislav Shwartsman
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d6e08702e4
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add Icelake-U model to CPUDB database. TODO: verify its VMX features
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2019-09-24 20:26:14 +00:00 |
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Stanislav Shwartsman
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e387876145
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Enable PML VMX feature in Skylake-X
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2018-10-26 19:54:22 +00:00 |
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Stanislav Shwartsman
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2e192372c0
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fixes for CNL CPUID
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2018-10-26 19:46:56 +00:00 |
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Stanislav Shwartsman
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a9aa1040c1
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add Intel Cannonlake CPU model to CPUDB featuring AVF512FMA52 and SHA instructions
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2018-10-26 09:23:58 +00:00 |
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Stanislav Shwartsman
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045a1cd637
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XSAVEC/XSAVES should be supported in SKL-X CPUID
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2017-11-11 12:04:26 +00:00 |
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Stanislav Shwartsman
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7f4a9b4b08
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skylake CPUID should compile also with no EVEX
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2017-08-09 21:04:15 +00:00 |
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Stanislav Shwartsman
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7f01a7d9b6
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remove obsolete comment
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2017-08-09 20:37:43 +00:00 |
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Stanislav Shwartsman
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b2fdbd1274
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added Skylake-X model to CPUDB -> with EVEX and AVX512 support
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2017-08-09 20:36:17 +00:00 |
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Stanislav Shwartsman
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e5c64b3b56
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cleanup of warning messages from cpuid code
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2017-03-26 20:12:14 +00:00 |
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Stanislav Shwartsman
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402e2cfad0
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move cpuid warning messages to base cpuid class - reduce code cleanup
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2017-03-13 19:59:48 +00:00 |
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Stanislav Shwartsman
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07166f14b7
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reorg of cpudb folder, added AMD Ryzen CPUID placeholder module (still not 100% correct)
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2017-03-13 19:44:14 +00:00 |
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