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Support for x86-64 in x86 debugger (DR0-DR7)

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This commit is contained in:
Stanislav Shwartsman 2006-05-13 12:49:45 +00:00
parent 9a32d0e98f
commit f4c7b4074e
3 changed files with 61 additions and 67 deletions
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9
bochs/cpu/cpu.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: cpu.cc,v 1.151 2006-05-12 17:04:18 sshwarts Exp $
// $Id: cpu.cc,v 1.152 2006-05-13 12:49:45 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -670,10 +670,9 @@ unsigned BX_CPU_C::handleAsyncEvent(void)
else {
// only bother comparing if any breakpoints enabled
if (BX_CPU_THIS_PTR dr7 & 0x000000ff) {
Bit32u iaddr = BX_CPU_THIS_PTR get_segment_base(BX_SEG_REG_CS) + BX_CPU_THIS_PTR prev_eip;
Bit32u dr6_bits;
if ( (dr6_bits = hwdebug_compare(iaddr, 1, BX_HWDebugInstruction,
BX_HWDebugInstruction)) )
bx_address iaddr = BX_CPU_THIS_PTR get_segment_base(BX_SEG_REG_CS) + BX_CPU_THIS_PTR prev_eip;
Bit32u dr6_bits = hwdebug_compare(iaddr, 1, BX_HWDebugInstruction, BX_HWDebugInstruction);
if (dr6_bits)
{
// Add to the list of debug events thus far.
BX_CPU_THIS_PTR async_event = 1;

20
bochs/cpu/cpu.h
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: cpu.h,v 1.290 2006-05-12 17:04:18 sshwarts Exp $
// $Id: cpu.h,v 1.291 2006-05-13 12:49:45 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -1086,12 +1086,12 @@ public: // for now...
bx_segment_reg_t ldtr; /* local descriptor table register */
bx_segment_reg_t tr; /* task register */
/* debug registers 0-7 (unimplemented) */
/* debug registers DR0-DR7 */
#if BX_CPU_LEVEL >= 3
Bit32u dr0;
Bit32u dr1;
Bit32u dr2;
Bit32u dr3;
bx_address dr0;
bx_address dr1;
bx_address dr2;
bx_address dr3;
Bit32u dr6;
Bit32u dr7;
#endif
@ -1103,12 +1103,10 @@ public: // for now...
bx_cr0_t cr0;
Bit32u cr1;
bx_address cr2;
bx_phy_address cr3;
bx_phy_address cr3_masked;
#endif
bx_phy_address cr3, cr3_masked;
#if BX_CPU_LEVEL >= 4
bx_cr4_t cr4;
#endif
#endif
/* SMM base register */
@ -2872,7 +2870,7 @@ public: // for now...
#if BX_X86_DEBUGGER
// x86 hardware debug support
BX_SMF Bit32u hwdebug_compare(Bit32u laddr, unsigned size,
BX_SMF Bit32u hwdebug_compare(bx_address laddr, unsigned size,
unsigned opa, unsigned opb);
#endif

47
bochs/cpu/proc_ctrl.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: proc_ctrl.cc,v 1.148 2006-05-13 12:29:12 sshwarts Exp $
// $Id: proc_ctrl.cc,v 1.149 2006-05-13 12:49:45 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -2247,41 +2247,37 @@ void BX_CPU_C::SWAPGS(bxInstruction_c *i)
#endif
#if BX_X86_DEBUGGER
Bit32u BX_CPU_C::hwdebug_compare(Bit32u laddr_0, unsigned size,
Bit32u BX_CPU_C::hwdebug_compare(bx_address laddr_0, unsigned size,
unsigned opa, unsigned opb)
{
// Support x86 hardware debug facilities (DR0..DR7)
Bit32u dr7 = BX_CPU_THIS_PTR dr7;
bx_bool ibpoint_found = 0;
Bit32u laddr_n = laddr_0 + (size - 1);
Bit32u dr0, dr1, dr2, dr3;
Bit32u dr0_n, dr1_n, dr2_n, dr3_n;
Bit32u len0, len1, len2, len3;
static unsigned alignment_mask[4] =
bx_address laddr_n = laddr_0 + (size - 1);
static bx_address alignment_mask[4] =
// 00b=1 01b=2 10b=undef 11b=4
{ 0xffffffff, 0xfffffffe, 0xffffffff, 0xfffffffc };
Bit32u dr0_op, dr1_op, dr2_op, dr3_op;
{ 0x0, 0x1, 0x0, 0x3 };
len0 = (dr7>>18) & 3;
len1 = (dr7>>22) & 3;
len2 = (dr7>>26) & 3;
len3 = (dr7>>30) & 3;
Bit32u len0 = (dr7>>18) & 3;
Bit32u len1 = (dr7>>22) & 3;
Bit32u len2 = (dr7>>26) & 3;
Bit32u len3 = (dr7>>30) & 3;
dr0 = BX_CPU_THIS_PTR dr0 & alignment_mask[len0];
dr1 = BX_CPU_THIS_PTR dr1 & alignment_mask[len1];
dr2 = BX_CPU_THIS_PTR dr2 & alignment_mask[len2];
dr3 = BX_CPU_THIS_PTR dr3 & alignment_mask[len3];
bx_address dr0 = (BX_CPU_THIS_PTR dr0) & ~(alignment_mask[len0]);
bx_address dr1 = (BX_CPU_THIS_PTR dr1) & ~(alignment_mask[len1]);
bx_address dr2 = (BX_CPU_THIS_PTR dr2) & ~(alignment_mask[len2]);
bx_address dr3 = (BX_CPU_THIS_PTR dr3) & ~(alignment_mask[len3]);
dr0_n = dr0 + len0;
dr1_n = dr1 + len1;
dr2_n = dr2 + len2;
dr3_n = dr3 + len3;
bx_address dr0_n = dr0 + len0;
bx_address dr1_n = dr1 + len1;
bx_address dr2_n = dr2 + len2;
bx_address dr3_n = dr3 + len3;
dr0_op = (dr7>>16) & 3;
dr1_op = (dr7>>20) & 3;
dr2_op = (dr7>>24) & 3;
dr3_op = (dr7>>28) & 3;
Bit32u dr0_op = (dr7>>16) & 3;
Bit32u dr1_op = (dr7>>20) & 3;
Bit32u dr2_op = (dr7>>24) & 3;
Bit32u dr3_op = (dr7>>28) & 3;
// See if this instruction address matches any breakpoints
if ((dr7 & 0x00000003)) {
@ -2337,6 +2333,7 @@ Bit32u BX_CPU_C::hwdebug_compare(Bit32u laddr_0, unsigned size,
dr6_mask |= 0x08;
return(dr6_mask);
}
return(0);
}
#endif