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@ -22,7 +22,7 @@ Changes to next release:
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- fixed using invalid segment register for MOV instruction (h.johansson)
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- fixed ET bit mismatch between CR0 and SMSW instruction
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- fixed possible simulator #DIVZERO fault when executing IDIV instruction
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- fixed undocumented flags handling for BTS, BTR, SHR, MUL and IMUL
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- fixed undocumented flags handling for BTS, BTR, SHR, SHLD, MUL and IMUL
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instructions (Stanislav Shwartsman)
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- fixed CF flag handling for SHL instruction in x86-64 mode
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(Stanislav Shwartsman)
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