Fixed undocumented flags handling for SHLD instruction
Added lazy flags for SHLD instruction Bugfix and speedup in SHLD and SHRD instructions
This commit is contained in:
parent
3ee4cd39b4
commit
d142f23242
@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: shift16.cc,v 1.24 2004-09-04 19:37:37 sshwarts Exp $
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// $Id: shift16.cc,v 1.25 2004-12-24 22:44:13 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -30,11 +30,9 @@
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#define LOG_THIS BX_CPU_THIS_PTR
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void
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BX_CPU_C::SHLD_EwGw(bxInstruction_c *i)
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void BX_CPU_C::SHLD_EwGw(bxInstruction_c *i)
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{
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Bit16u op1_16, op2_16, result_16;
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Bit32u temp_32, result_32;
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unsigned count;
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/* op1:op2 << count. result stored in op1 */
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@ -45,115 +43,103 @@ BX_CPU_C::SHLD_EwGw(bxInstruction_c *i)
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count &= 0x1f; // use only 5 LSB's
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if (!count) return; /* NOP */
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// count is 1..31
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/* op1 is a register or memory reference */
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if (i->modC0()) {
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op1_16 = BX_READ_16BIT_REG(i->rm());
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}
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else {
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/* pointer, segment address pair */
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read_RMW_virtual_word(i->seg(), RMAddr(i), &op1_16);
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}
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/* op1 is a register or memory reference */
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if (i->modC0()) {
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op1_16 = BX_READ_16BIT_REG(i->rm());
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}
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else {
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/* pointer, segment address pair */
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read_RMW_virtual_word(i->seg(), RMAddr(i), &op1_16);
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}
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op2_16 = BX_READ_16BIT_REG(i->nnn());
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if (!count) return;
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// count is 1..31
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temp_32 = ((Bit32u)(op1_16) << 16) | (op2_16); // double formed by op1:op2
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result_32 = temp_32 << count;
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if (count > 16) {
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// hack to act like x86 SHLD when count > 16
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// actually shifting op1:op2:op2 << count
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result_32 |= (op2_16 << (count - 16));
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}
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result_16 = result_32 >> 16;
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op2_16 = BX_READ_16BIT_REG(i->nnn());
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/* now write result back to destination */
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if (i->modC0()) {
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BX_WRITE_16BIT_REG(i->rm(), result_16);
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}
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else {
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Write_RMW_virtual_word(result_16);
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}
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// Hack to act like x86 SHLD when count > 16
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if (count > 16) {
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// when count > 16 actually shifting op1:op2:op2 << count,
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// it is the same as shifting op2:op2 by count-16
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op1_16 = op2_16;
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count -= 16;
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}
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/* set eflags:
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* SHLD count affects the following flags: S,Z,P,C,O
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*/
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set_CF( (temp_32 >> (32 - count)) & 0x01 );
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if (count == 1)
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set_OF(((op1_16 ^ result_16) & 0x8000) > 0);
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set_AF(0);
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set_ZF(result_16 == 0);
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set_SF(result_16 >> 15);
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set_PF_base((Bit8u) result_16);
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result_16 = (op1_16 << count) | (op2_16 >> (16 - count));
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/* now write result back to destination */
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if (i->modC0()) {
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BX_WRITE_16BIT_REG(i->rm(), result_16);
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}
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else {
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Write_RMW_virtual_word(result_16);
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}
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/* set eflags:
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* SHLD count affects the following flags: O,S,Z,A,P,C
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*/
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SET_FLAGS_OSZAPC_16(op1_16, count, result_16, BX_INSTR_SHL16);
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}
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void
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BX_CPU_C::SHRD_EwGw(bxInstruction_c *i)
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void BX_CPU_C::SHRD_EwGw(bxInstruction_c *i)
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{
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#if BX_CPU_LEVEL < 3
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BX_INFO(("SHRD_EwGw: not supported on < 386"));
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UndefinedOpcode(i)
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#else
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Bit16u op1_16, op2_16, result_16;
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Bit32u temp_32, result_32;
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unsigned count;
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if (i->b1() == 0x1ac)
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count = i->Ib();
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else // 0x1ad
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count = CL;
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count &= 0x1F; /* use only 5 LSB's */
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if (!count) return; /* NOP */
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count &= 0x1f; /* use only 5 LSB's */
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// count is 1..31
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/* op1 is a register or memory reference */
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if (i->modC0()) {
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op1_16 = BX_READ_16BIT_REG(i->rm());
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}
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else {
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/* pointer, segment address pair */
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read_RMW_virtual_word(i->seg(), RMAddr(i), &op1_16);
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}
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/* op1 is a register or memory reference */
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if (i->modC0()) {
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op1_16 = BX_READ_16BIT_REG(i->rm());
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}
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else {
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/* pointer, segment address pair */
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read_RMW_virtual_word(i->seg(), RMAddr(i), &op1_16);
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}
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op2_16 = BX_READ_16BIT_REG(i->nnn());
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if (!count) return;
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// count is 1..31
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temp_32 = (op2_16 << 16) | op1_16; // double formed by op2:op1
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result_32 = temp_32 >> count;
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if (count > 16) {
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// hack to act like x86 SHLD when count > 16
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// actually shifting op2:op2:op1 >> count
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result_32 |= (op2_16 << (32 - count));
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}
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result_16 = result_32;
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op2_16 = BX_READ_16BIT_REG(i->nnn());
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/* now write result back to destination */
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if (i->modC0()) {
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BX_WRITE_16BIT_REG(i->rm(), result_16);
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}
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else {
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Write_RMW_virtual_word(result_16);
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}
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// Hack to act like x86 SHLD when count > 16
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if (count > 16) {
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// when count > 16 actually shifting op2:op2:op1 >> count,
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// it is the same as shifting op2:op2 by count-16
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op1_16 = op2_16;
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count -= 16;
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}
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result_16 = (op2_16 << (16 - count)) | (op1_16 >> count);
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/* set eflags:
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* SHRD count affects the following flags: S,Z,P,C,O
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*/
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/* now write result back to destination */
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if (i->modC0()) {
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BX_WRITE_16BIT_REG(i->rm(), result_16);
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}
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else {
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Write_RMW_virtual_word(result_16);
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}
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set_CF((temp_32 >> (count - 1)) & 0x01);
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set_ZF(result_16 == 0);
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set_SF(result_16 >> 15);
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set_AF(0);
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/* for shift of 1, OF set if sign change occurred. */
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if (count == 1)
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set_OF(((op1_16 ^ result_16) & 0x8000) > 0);
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set_PF_base((Bit8u) result_16);
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#endif /* BX_CPU_LEVEL >= 3 */
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/* set eflags:
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* SHRD count affects the following flags: S,Z,P,C,O
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*/
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set_CF((op1_16 >> (count - 1)) & 0x01);
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set_ZF(result_16 == 0);
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set_SF(result_16 >> 15);
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set_AF(0);
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/* for shift of 1, OF set if sign change occurred. */
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if (count == 1)
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set_OF(((op1_16 ^ result_16) & 0x8000) > 0);
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set_PF_base((Bit8u) result_16);
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}
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void
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BX_CPU_C::ROL_Ew(bxInstruction_c *i)
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void BX_CPU_C::ROL_Ew(bxInstruction_c *i)
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{
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Bit16u op1_16, result_16;
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unsigned count;
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@ -165,189 +151,183 @@ BX_CPU_C::ROL_Ew(bxInstruction_c *i)
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else // 0xd3
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count = CL;
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count &= 0x0f; // only use bottom 4 bits
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count &= 0x0f; // only use bottom 4 bits
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/* op1 is a register or memory reference */
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if (i->modC0()) {
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op1_16 = BX_READ_16BIT_REG(i->rm());
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}
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else {
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/* pointer, segment address pair */
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read_RMW_virtual_word(i->seg(), RMAddr(i), &op1_16);
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}
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if (! count) return;
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result_16 = (op1_16 << count) | (op1_16 >> (16 - count));
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/* now write result back to destination */
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if (i->modC0()) {
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BX_WRITE_16BIT_REG(i->rm(), result_16);
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}
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else {
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Write_RMW_virtual_word(result_16);
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}
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/* set eflags:
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* ROL count affects the following flags: C, O
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*/
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bx_bool temp_CF = (result_16 & 0x01);
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set_CF(temp_CF);
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set_OF(temp_CF ^ (result_16 >> 15));
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}
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void
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BX_CPU_C::ROR_Ew(bxInstruction_c *i)
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{
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Bit16u op1_16, result_16;
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unsigned count;
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if ( i->b1() == 0xc1 )
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count = i->Ib();
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else if ( i->b1() == 0xd1 )
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count = 1;
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else // 0xd3
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count = CL;
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count &= 0x0f; // use only 4 LSB's
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/* op1 is a register or memory reference */
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if (i->modC0()) {
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op1_16 = BX_READ_16BIT_REG(i->rm());
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}
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else {
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/* pointer, segment address pair */
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read_RMW_virtual_word(i->seg(), RMAddr(i), &op1_16);
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}
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if (! count) return;
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result_16 = (op1_16 >> count) | (op1_16 << (16 - count));
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/* now write result back to destination */
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if (i->modC0()) {
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BX_WRITE_16BIT_REG(i->rm(), result_16);
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}
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else {
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Write_RMW_virtual_word(result_16);
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}
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/* set eflags:
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* ROR count affects the following flags: C, O
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*/
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bx_bool result_b15 = (result_16 & 0x8000) != 0;
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set_CF(result_b15);
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if (count == 1)
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set_OF(((op1_16 ^ result_16) & 0x8000) > 0);
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}
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void
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BX_CPU_C::RCL_Ew(bxInstruction_c *i)
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{
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Bit16u op1_16, result_16;
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unsigned count;
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if ( i->b1() == 0xc1 )
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count = i->Ib();
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else if ( i->b1() == 0xd1 )
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count = 1;
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else // 0xd3
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count = CL;
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count %= 17;
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/* op1 is a register or memory reference */
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if (i->modC0()) {
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op1_16 = BX_READ_16BIT_REG(i->rm());
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}
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else {
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/* pointer, segment address pair */
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read_RMW_virtual_word(i->seg(), RMAddr(i), &op1_16);
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}
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if (!count) return;
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if (count==1) {
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result_16 = (op1_16 << 1) | getB_CF();
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}
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else if (count==16) {
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result_16 = (getB_CF() << 15) |
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(op1_16 >> 1);
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}
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else { // 2..15
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result_16 = (op1_16 << count) |
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(getB_CF() << (count - 1)) |
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(op1_16 >> (17 - count));
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}
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/* now write result back to destination */
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if (i->modC0()) {
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BX_WRITE_16BIT_REG(i->rm(), result_16);
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}
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else {
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Write_RMW_virtual_word(result_16);
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}
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/* set eflags:
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* RCL count affects the following flags: C, O
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*/
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bx_bool temp_CF = (op1_16 >> (16 - count)) & 0x01;
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set_CF(temp_CF);
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set_OF(temp_CF ^ (result_16 >> 15));
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}
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void
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BX_CPU_C::RCR_Ew(bxInstruction_c *i)
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{
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Bit16u op1_16, result_16;
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unsigned count;
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if ( i->b1() == 0xc1 )
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count = i->Ib();
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else if ( i->b1() == 0xd1 )
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count = 1;
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else // 0xd3
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count = CL;
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count %= 17;
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/* op1 is a register or memory reference */
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if (i->modC0()) {
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op1_16 = BX_READ_16BIT_REG(i->rm());
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}
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else {
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/* pointer, segment address pair */
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read_RMW_virtual_word(i->seg(), RMAddr(i), &op1_16);
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}
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/* op1 is a register or memory reference */
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if (i->modC0()) {
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op1_16 = BX_READ_16BIT_REG(i->rm());
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}
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else {
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/* pointer, segment address pair */
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read_RMW_virtual_word(i->seg(), RMAddr(i), &op1_16);
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}
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if (! count) return;
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result_16 = (op1_16 >> count) |
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result_16 = (op1_16 << count) | (op1_16 >> (16 - count));
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/* now write result back to destination */
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if (i->modC0()) {
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BX_WRITE_16BIT_REG(i->rm(), result_16);
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}
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else {
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Write_RMW_virtual_word(result_16);
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}
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/* set eflags:
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* ROL count affects the following flags: C, O
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*/
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bx_bool temp_CF = (result_16 & 0x01);
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set_CF(temp_CF);
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set_OF(temp_CF ^ (result_16 >> 15));
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}
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void BX_CPU_C::ROR_Ew(bxInstruction_c *i)
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{
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Bit16u op1_16, result_16;
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unsigned count;
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if ( i->b1() == 0xc1 )
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count = i->Ib();
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else if ( i->b1() == 0xd1 )
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count = 1;
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else // 0xd3
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count = CL;
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count &= 0x0f; // use only 4 LSB's
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/* op1 is a register or memory reference */
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if (i->modC0()) {
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op1_16 = BX_READ_16BIT_REG(i->rm());
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}
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else {
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/* pointer, segment address pair */
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read_RMW_virtual_word(i->seg(), RMAddr(i), &op1_16);
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}
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if (! count) return;
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result_16 = (op1_16 >> count) | (op1_16 << (16 - count));
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/* now write result back to destination */
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if (i->modC0()) {
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BX_WRITE_16BIT_REG(i->rm(), result_16);
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}
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else {
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Write_RMW_virtual_word(result_16);
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}
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/* set eflags:
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* ROR count affects the following flags: C, O
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*/
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bx_bool result_b15 = (result_16 & 0x8000) != 0;
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set_CF(result_b15);
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if (count == 1)
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set_OF(((op1_16 ^ result_16) & 0x8000) > 0);
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}
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void BX_CPU_C::RCL_Ew(bxInstruction_c *i)
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{
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Bit16u op1_16, result_16;
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unsigned count;
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if ( i->b1() == 0xc1 )
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count = i->Ib();
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else if ( i->b1() == 0xd1 )
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count = 1;
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else // 0xd3
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count = CL;
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count &= 0x0f; // use only 4 LSB's
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/* op1 is a register or memory reference */
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if (i->modC0()) {
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op1_16 = BX_READ_16BIT_REG(i->rm());
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}
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else {
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/* pointer, segment address pair */
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read_RMW_virtual_word(i->seg(), RMAddr(i), &op1_16);
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}
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if (!count) return;
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if (count==1) {
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result_16 = (op1_16 << 1) | getB_CF();
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}
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else if (count==16) {
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result_16 = (getB_CF() << 15) | (op1_16 >> 1);
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}
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else { // 2..15
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result_16 = (op1_16 << count) | (getB_CF() << (count - 1)) |
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(op1_16 >> (17 - count));
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}
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|
||||
/* now write result back to destination */
|
||||
if (i->modC0()) {
|
||||
BX_WRITE_16BIT_REG(i->rm(), result_16);
|
||||
}
|
||||
else {
|
||||
Write_RMW_virtual_word(result_16);
|
||||
}
|
||||
|
||||
/* set eflags:
|
||||
* RCL count affects the following flags: C, O
|
||||
*/
|
||||
bx_bool temp_CF = (op1_16 >> (16 - count)) & 0x01;
|
||||
|
||||
set_CF(temp_CF);
|
||||
set_OF(temp_CF ^ (result_16 >> 15));
|
||||
}
|
||||
|
||||
void BX_CPU_C::RCR_Ew(bxInstruction_c *i)
|
||||
{
|
||||
Bit16u op1_16, result_16;
|
||||
unsigned count;
|
||||
|
||||
if ( i->b1() == 0xc1 )
|
||||
count = i->Ib();
|
||||
else if ( i->b1() == 0xd1 )
|
||||
count = 1;
|
||||
else // 0xd3
|
||||
count = CL;
|
||||
|
||||
count &= 0x0f; // use only 4 LSB's
|
||||
|
||||
/* op1 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op1_16 = BX_READ_16BIT_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
read_RMW_virtual_word(i->seg(), RMAddr(i), &op1_16);
|
||||
}
|
||||
|
||||
if (! count) return;
|
||||
|
||||
result_16 = (op1_16 >> count) |
|
||||
(getB_CF() << (16 - count)) |
|
||||
(op1_16 << (17 - count));
|
||||
|
||||
/* now write result back to destination */
|
||||
if (i->modC0()) {
|
||||
BX_WRITE_16BIT_REG(i->rm(), result_16);
|
||||
}
|
||||
else {
|
||||
Write_RMW_virtual_word(result_16);
|
||||
}
|
||||
/* now write result back to destination */
|
||||
if (i->modC0()) {
|
||||
BX_WRITE_16BIT_REG(i->rm(), result_16);
|
||||
}
|
||||
else {
|
||||
Write_RMW_virtual_word(result_16);
|
||||
}
|
||||
|
||||
/* set eflags:
|
||||
* RCR count affects the following flags: C, O
|
||||
*/
|
||||
/* set eflags:
|
||||
* RCR count affects the following flags: C, O
|
||||
*/
|
||||
|
||||
set_CF((op1_16 >> (count - 1)) & 0x01);
|
||||
if (count == 1)
|
||||
set_OF(((op1_16 ^ result_16) & 0x8000) > 0);
|
||||
set_CF((op1_16 >> (count - 1)) & 0x01);
|
||||
if (count == 1)
|
||||
set_OF(((op1_16 ^ result_16) & 0x8000) > 0);
|
||||
}
|
||||
|
||||
void
|
||||
BX_CPU_C::SHL_Ew(bxInstruction_c *i)
|
||||
void BX_CPU_C::SHL_Ew(bxInstruction_c *i)
|
||||
{
|
||||
Bit16u op1_16, result_16;
|
||||
unsigned count;
|
||||
@ -359,34 +339,33 @@ BX_CPU_C::SHL_Ew(bxInstruction_c *i)
|
||||
else // 0xd3
|
||||
count = CL;
|
||||
|
||||
count &= 0x1F; /* use only 5 LSB's */
|
||||
count &= 0x1f; /* use only 5 LSB's */
|
||||
|
||||
/* op1 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op1_16 = BX_READ_16BIT_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
read_RMW_virtual_word(i->seg(), RMAddr(i), &op1_16);
|
||||
}
|
||||
/* op1 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op1_16 = BX_READ_16BIT_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
read_RMW_virtual_word(i->seg(), RMAddr(i), &op1_16);
|
||||
}
|
||||
|
||||
if (!count) return;
|
||||
if (!count) return;
|
||||
|
||||
result_16 = (op1_16 << count);
|
||||
result_16 = (op1_16 << count);
|
||||
|
||||
/* now write result back to destination */
|
||||
if (i->modC0()) {
|
||||
BX_WRITE_16BIT_REG(i->rm(), result_16);
|
||||
}
|
||||
else {
|
||||
Write_RMW_virtual_word(result_16);
|
||||
}
|
||||
/* now write result back to destination */
|
||||
if (i->modC0()) {
|
||||
BX_WRITE_16BIT_REG(i->rm(), result_16);
|
||||
}
|
||||
else {
|
||||
Write_RMW_virtual_word(result_16);
|
||||
}
|
||||
|
||||
SET_FLAGS_OSZAPC_16(op1_16, count, result_16, BX_INSTR_SHL16);
|
||||
SET_FLAGS_OSZAPC_16(op1_16, count, result_16, BX_INSTR_SHL16);
|
||||
}
|
||||
|
||||
void
|
||||
BX_CPU_C::SHR_Ew(bxInstruction_c *i)
|
||||
void BX_CPU_C::SHR_Ew(bxInstruction_c *i)
|
||||
{
|
||||
Bit16u op1_16, result_16;
|
||||
unsigned count;
|
||||
@ -398,40 +377,38 @@ BX_CPU_C::SHR_Ew(bxInstruction_c *i)
|
||||
else // 0xd3
|
||||
count = CL;
|
||||
|
||||
count &= 0x1F; /* use only 5 LSB's */
|
||||
count &= 0x1f; /* use only 5 LSB's */
|
||||
|
||||
/* op1 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op1_16 = BX_READ_16BIT_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
read_RMW_virtual_word(i->seg(), RMAddr(i), &op1_16);
|
||||
}
|
||||
/* op1 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op1_16 = BX_READ_16BIT_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
read_RMW_virtual_word(i->seg(), RMAddr(i), &op1_16);
|
||||
}
|
||||
|
||||
if (!count) return;
|
||||
if (!count) return;
|
||||
|
||||
#if defined(BX_HostAsm_Shr16)
|
||||
Bit32u flags32;
|
||||
asmShr16(result_16, op1_16, count, flags32);
|
||||
setEFlagsOSZAPC(flags32);
|
||||
Bit32u flags32;
|
||||
asmShr16(result_16, op1_16, count, flags32);
|
||||
setEFlagsOSZAPC(flags32);
|
||||
#else
|
||||
result_16 = (op1_16 >> count);
|
||||
SET_FLAGS_OSZAPC_16(op1_16, count, result_16, BX_INSTR_SHR16);
|
||||
result_16 = (op1_16 >> count);
|
||||
SET_FLAGS_OSZAPC_16(op1_16, count, result_16, BX_INSTR_SHR16);
|
||||
#endif
|
||||
|
||||
/* now write result back to destination */
|
||||
if (i->modC0()) {
|
||||
BX_WRITE_16BIT_REG(i->rm(), result_16);
|
||||
}
|
||||
else {
|
||||
Write_RMW_virtual_word(result_16);
|
||||
}
|
||||
/* now write result back to destination */
|
||||
if (i->modC0()) {
|
||||
BX_WRITE_16BIT_REG(i->rm(), result_16);
|
||||
}
|
||||
else {
|
||||
Write_RMW_virtual_word(result_16);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
BX_CPU_C::SAR_Ew(bxInstruction_c *i)
|
||||
void BX_CPU_C::SAR_Ew(bxInstruction_c *i)
|
||||
{
|
||||
Bit16u op1_16, result_16;
|
||||
unsigned count;
|
||||
@ -443,43 +420,43 @@ BX_CPU_C::SAR_Ew(bxInstruction_c *i)
|
||||
else // 0xd3
|
||||
count = CL;
|
||||
|
||||
count &= 0x1F; /* use only 5 LSB's */
|
||||
count &= 0x1f; /* use only 5 LSB's */
|
||||
|
||||
/* op1 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op1_16 = BX_READ_16BIT_REG(i->rm());
|
||||
}
|
||||
/* op1 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op1_16 = BX_READ_16BIT_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
read_RMW_virtual_word(i->seg(), RMAddr(i), &op1_16);
|
||||
}
|
||||
|
||||
if (!count) return;
|
||||
|
||||
if (count < 16) {
|
||||
if (op1_16 & 0x8000) {
|
||||
result_16 = (op1_16 >> count) | (0xffff << (16 - count));
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
read_RMW_virtual_word(i->seg(), RMAddr(i), &op1_16);
|
||||
}
|
||||
|
||||
if (!count) return;
|
||||
|
||||
if (count < 16) {
|
||||
if (op1_16 & 0x8000) {
|
||||
result_16 = (op1_16 >> count) | (0xffff << (16 - count));
|
||||
}
|
||||
else {
|
||||
result_16 = (op1_16 >> count);
|
||||
}
|
||||
}
|
||||
result_16 = (op1_16 >> count);
|
||||
}
|
||||
}
|
||||
else {
|
||||
if (op1_16 & 0x8000) {
|
||||
result_16 = 0xffff;
|
||||
}
|
||||
else {
|
||||
if (op1_16 & 0x8000) {
|
||||
result_16 = 0xffff;
|
||||
}
|
||||
else {
|
||||
result_16 = 0;
|
||||
}
|
||||
}
|
||||
result_16 = 0;
|
||||
}
|
||||
}
|
||||
|
||||
/* now write result back to destination */
|
||||
if (i->modC0()) {
|
||||
BX_WRITE_16BIT_REG(i->rm(), result_16);
|
||||
}
|
||||
else {
|
||||
Write_RMW_virtual_word(result_16);
|
||||
}
|
||||
/* now write result back to destination */
|
||||
if (i->modC0()) {
|
||||
BX_WRITE_16BIT_REG(i->rm(), result_16);
|
||||
}
|
||||
else {
|
||||
Write_RMW_virtual_word(result_16);
|
||||
}
|
||||
|
||||
SET_FLAGS_OSZAPC_16(op1_16, count, result_16, BX_INSTR_SAR16);
|
||||
SET_FLAGS_OSZAPC_16(op1_16, count, result_16, BX_INSTR_SAR16);
|
||||
}
|
||||
|
@ -1,5 +1,5 @@
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
// $Id: shift32.cc,v 1.25 2004-11-02 16:10:02 sshwarts Exp $
|
||||
// $Id: shift32.cc,v 1.26 2004-12-24 22:44:13 sshwarts Exp $
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Copyright (C) 2001 MandrakeSoft S.A.
|
||||
@ -30,8 +30,7 @@
|
||||
#define LOG_THIS BX_CPU_THIS_PTR
|
||||
|
||||
|
||||
void
|
||||
BX_CPU_C::SHLD_EdGd(bxInstruction_c *i)
|
||||
void BX_CPU_C::SHLD_EdGd(bxInstruction_c *i)
|
||||
{
|
||||
Bit32u op1_32, op2_32, result_32;
|
||||
unsigned count;
|
||||
@ -43,43 +42,36 @@ BX_CPU_C::SHLD_EdGd(bxInstruction_c *i)
|
||||
else // 0x1a5
|
||||
count = CL & 0x1f;
|
||||
|
||||
if (!count) return; /* NOP */
|
||||
/* op1 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op1_32 = BX_READ_32BIT_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
|
||||
}
|
||||
|
||||
/* op1 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op1_32 = BX_READ_32BIT_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
|
||||
}
|
||||
op2_32 = BX_READ_32BIT_REG(i->nnn());
|
||||
if (!count) return;
|
||||
|
||||
result_32 = (op1_32 << count) | (op2_32 >> (32 - count));
|
||||
op2_32 = BX_READ_32BIT_REG(i->nnn());
|
||||
|
||||
/* now write result back to destination */
|
||||
if (i->modC0()) {
|
||||
BX_WRITE_32BIT_REGZ(i->rm(), result_32);
|
||||
}
|
||||
else {
|
||||
Write_RMW_virtual_dword(result_32);
|
||||
}
|
||||
result_32 = (op1_32 << count) | (op2_32 >> (32 - count));
|
||||
|
||||
/* set eflags:
|
||||
* SHLD count affects the following flags: S,Z,P,C,O
|
||||
*/
|
||||
set_CF((op1_32 >> (32 - count)) & 0x01);
|
||||
if (count == 1)
|
||||
set_OF(((op1_32 ^ result_32) & 0x80000000) > 0);
|
||||
set_AF(0);
|
||||
set_ZF(result_32 == 0);
|
||||
set_PF_base(result_32);
|
||||
set_SF(result_32 >> 31);
|
||||
/* now write result back to destination */
|
||||
if (i->modC0()) {
|
||||
BX_WRITE_32BIT_REGZ(i->rm(), result_32);
|
||||
}
|
||||
else {
|
||||
Write_RMW_virtual_dword(result_32);
|
||||
}
|
||||
|
||||
/* set eflags:
|
||||
* SHLD count affects the following flags: O,S,Z,A,P,C
|
||||
*/
|
||||
SET_FLAGS_OSZAPC_32(op1_32, count, result_32, BX_INSTR_SHL32);
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
BX_CPU_C::SHRD_EdGd(bxInstruction_c *i)
|
||||
void BX_CPU_C::SHRD_EdGd(bxInstruction_c *i)
|
||||
{
|
||||
Bit32u op1_32, op2_32, result_32;
|
||||
unsigned count;
|
||||
@ -89,45 +81,44 @@ BX_CPU_C::SHRD_EdGd(bxInstruction_c *i)
|
||||
else // 0x1ad
|
||||
count = CL & 0x1f;
|
||||
|
||||
if (!count) return; /* NOP */
|
||||
/* op1 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op1_32 = BX_READ_32BIT_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
|
||||
}
|
||||
|
||||
/* op1 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op1_32 = BX_READ_32BIT_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
|
||||
}
|
||||
op2_32 = BX_READ_32BIT_REG(i->nnn());
|
||||
if (!count) return;
|
||||
|
||||
result_32 = (op2_32 << (32 - count)) | (op1_32 >> count);
|
||||
op2_32 = BX_READ_32BIT_REG(i->nnn());
|
||||
|
||||
/* now write result back to destination */
|
||||
if (i->modC0()) {
|
||||
BX_WRITE_32BIT_REGZ(i->rm(), result_32);
|
||||
}
|
||||
else {
|
||||
Write_RMW_virtual_dword(result_32);
|
||||
}
|
||||
result_32 = (op2_32 << (32 - count)) | (op1_32 >> count);
|
||||
|
||||
/* set eflags:
|
||||
* SHRD count affects the following flags: S,Z,P,C,O
|
||||
*/
|
||||
/* now write result back to destination */
|
||||
if (i->modC0()) {
|
||||
BX_WRITE_32BIT_REGZ(i->rm(), result_32);
|
||||
}
|
||||
else {
|
||||
Write_RMW_virtual_dword(result_32);
|
||||
}
|
||||
|
||||
set_CF((op1_32 >> (count - 1)) & 0x01);
|
||||
set_ZF(result_32 == 0);
|
||||
set_SF(result_32 >> 31);
|
||||
set_AF(0);
|
||||
/* for shift of 1, OF set if sign change occurred. */
|
||||
if (count == 1)
|
||||
set_OF(((op1_32 ^ result_32) & 0x80000000) > 0);
|
||||
set_PF_base(result_32);
|
||||
/* set eflags:
|
||||
* SHRD count affects the following flags: S,Z,P,C,O
|
||||
*/
|
||||
|
||||
set_CF((op1_32 >> (count - 1)) & 0x01);
|
||||
set_ZF(result_32 == 0);
|
||||
set_SF(result_32 >> 31);
|
||||
set_AF(0);
|
||||
/* for shift of 1, OF set if sign change occurred. */
|
||||
if (count == 1)
|
||||
set_OF(((op1_32 ^ result_32) & 0x80000000) > 0);
|
||||
set_PF_base(result_32);
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
BX_CPU_C::ROL_Ed(bxInstruction_c *i)
|
||||
void BX_CPU_C::ROL_Ed(bxInstruction_c *i)
|
||||
{
|
||||
Bit32u op1_32, result_32;
|
||||
unsigned count;
|
||||
@ -139,38 +130,37 @@ BX_CPU_C::ROL_Ed(bxInstruction_c *i)
|
||||
else // (i->b1() == 0xd3)
|
||||
count = CL & 0x1f;
|
||||
|
||||
/* op1 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op1_32 = BX_READ_32BIT_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
|
||||
}
|
||||
/* op1 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op1_32 = BX_READ_32BIT_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
|
||||
}
|
||||
|
||||
if (! count) return;
|
||||
if (! count) return;
|
||||
|
||||
result_32 = (op1_32 << count) | (op1_32 >> (32 - count));
|
||||
result_32 = (op1_32 << count) | (op1_32 >> (32 - count));
|
||||
|
||||
/* now write result back to destination */
|
||||
if (i->modC0()) {
|
||||
BX_WRITE_32BIT_REGZ(i->rm(), result_32);
|
||||
}
|
||||
else {
|
||||
Write_RMW_virtual_dword(result_32);
|
||||
}
|
||||
/* now write result back to destination */
|
||||
if (i->modC0()) {
|
||||
BX_WRITE_32BIT_REGZ(i->rm(), result_32);
|
||||
}
|
||||
else {
|
||||
Write_RMW_virtual_dword(result_32);
|
||||
}
|
||||
|
||||
/* set eflags:
|
||||
* ROL count affects the following flags: C, O
|
||||
*/
|
||||
bx_bool temp_CF = (result_32 & 0x01);
|
||||
/* set eflags:
|
||||
* ROL count affects the following flags: C, O
|
||||
*/
|
||||
bx_bool temp_CF = (result_32 & 0x01);
|
||||
|
||||
set_CF(temp_CF);
|
||||
set_OF(temp_CF ^ (result_32 >> 31));
|
||||
set_CF(temp_CF);
|
||||
set_OF(temp_CF ^ (result_32 >> 31));
|
||||
}
|
||||
|
||||
void
|
||||
BX_CPU_C::ROR_Ed(bxInstruction_c *i)
|
||||
void BX_CPU_C::ROR_Ed(bxInstruction_c *i)
|
||||
{
|
||||
Bit32u op1_32, result_32;
|
||||
unsigned count;
|
||||
@ -182,39 +172,38 @@ BX_CPU_C::ROR_Ed(bxInstruction_c *i)
|
||||
else // (i->b1() == 0xd3)
|
||||
count = CL & 0x1f;
|
||||
|
||||
/* op1 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op1_32 = BX_READ_32BIT_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
|
||||
}
|
||||
/* op1 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op1_32 = BX_READ_32BIT_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
|
||||
}
|
||||
|
||||
if (! count) return;
|
||||
if (! count) return;
|
||||
|
||||
result_32 = (op1_32 >> count) | (op1_32 << (32 - count));
|
||||
result_32 = (op1_32 >> count) | (op1_32 << (32 - count));
|
||||
|
||||
/* now write result back to destination */
|
||||
if (i->modC0()) {
|
||||
BX_WRITE_32BIT_REGZ(i->rm(), result_32);
|
||||
}
|
||||
else {
|
||||
Write_RMW_virtual_dword(result_32);
|
||||
}
|
||||
/* now write result back to destination */
|
||||
if (i->modC0()) {
|
||||
BX_WRITE_32BIT_REGZ(i->rm(), result_32);
|
||||
}
|
||||
else {
|
||||
Write_RMW_virtual_dword(result_32);
|
||||
}
|
||||
|
||||
/* set eflags:
|
||||
* ROR count affects the following flags: C, O
|
||||
*/
|
||||
bx_bool result_b31 = (result_32 & 0x80000000) != 0;
|
||||
/* set eflags:
|
||||
* ROR count affects the following flags: C, O
|
||||
*/
|
||||
bx_bool result_b31 = (result_32 & 0x80000000) != 0;
|
||||
|
||||
set_CF(result_b31);
|
||||
if (count == 1)
|
||||
set_OF(((op1_32 ^ result_32) & 0x80000000) > 0);
|
||||
set_CF(result_b31);
|
||||
if (count == 1)
|
||||
set_OF(((op1_32 ^ result_32) & 0x80000000) > 0);
|
||||
}
|
||||
|
||||
void
|
||||
BX_CPU_C::RCL_Ed(bxInstruction_c *i)
|
||||
void BX_CPU_C::RCL_Ed(bxInstruction_c *i)
|
||||
{
|
||||
Bit32u op1_32, result_32;
|
||||
unsigned count;
|
||||
@ -226,45 +215,43 @@ BX_CPU_C::RCL_Ed(bxInstruction_c *i)
|
||||
else // (i->b1() == 0xd3)
|
||||
count = CL & 0x1f;
|
||||
|
||||
/* op1 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op1_32 = BX_READ_32BIT_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
|
||||
}
|
||||
/* op1 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op1_32 = BX_READ_32BIT_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
|
||||
}
|
||||
|
||||
if (!count) return;
|
||||
if (!count) return;
|
||||
|
||||
if (count==1) {
|
||||
result_32 = (op1_32 << 1) | getB_CF();
|
||||
}
|
||||
else {
|
||||
result_32 = (op1_32 << count) |
|
||||
(getB_CF() << (count - 1)) |
|
||||
if (count==1) {
|
||||
result_32 = (op1_32 << 1) | getB_CF();
|
||||
}
|
||||
else {
|
||||
result_32 = (op1_32 << count) | (getB_CF() << (count - 1)) |
|
||||
(op1_32 >> (33 - count));
|
||||
}
|
||||
}
|
||||
|
||||
/* now write result back to destination */
|
||||
if (i->modC0()) {
|
||||
BX_WRITE_32BIT_REGZ(i->rm(), result_32);
|
||||
}
|
||||
else {
|
||||
Write_RMW_virtual_dword(result_32);
|
||||
}
|
||||
/* now write result back to destination */
|
||||
if (i->modC0()) {
|
||||
BX_WRITE_32BIT_REGZ(i->rm(), result_32);
|
||||
}
|
||||
else {
|
||||
Write_RMW_virtual_dword(result_32);
|
||||
}
|
||||
|
||||
/* set eflags:
|
||||
* RCL count affects the following flags: C, O
|
||||
*/
|
||||
bx_bool temp_CF = (op1_32 >> (32 - count)) & 0x01;
|
||||
/* set eflags:
|
||||
* RCL count affects the following flags: C, O
|
||||
*/
|
||||
bx_bool temp_CF = (op1_32 >> (32 - count)) & 0x01;
|
||||
|
||||
set_CF(temp_CF);
|
||||
set_OF(temp_CF ^ (result_32 >> 31));
|
||||
set_CF(temp_CF);
|
||||
set_OF(temp_CF ^ (result_32 >> 31));
|
||||
}
|
||||
|
||||
void
|
||||
BX_CPU_C::RCR_Ed(bxInstruction_c *i)
|
||||
void BX_CPU_C::RCR_Ed(bxInstruction_c *i)
|
||||
{
|
||||
Bit32u op1_32, result_32;
|
||||
unsigned count;
|
||||
@ -276,45 +263,43 @@ BX_CPU_C::RCR_Ed(bxInstruction_c *i)
|
||||
else // (i->b1() == 0xd3)
|
||||
count = CL & 0x1f;
|
||||
|
||||
/* op1 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op1_32 = BX_READ_32BIT_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
|
||||
}
|
||||
/* op1 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op1_32 = BX_READ_32BIT_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
|
||||
}
|
||||
|
||||
if (!count) return;
|
||||
if (!count) return;
|
||||
|
||||
if (count==1) {
|
||||
result_32 = (op1_32 >> 1) | (getB_CF() << 31);
|
||||
}
|
||||
else {
|
||||
result_32 = (op1_32 >> count) |
|
||||
(getB_CF() << (32 - count)) |
|
||||
if (count==1) {
|
||||
result_32 = (op1_32 >> 1) | (getB_CF() << 31);
|
||||
}
|
||||
else {
|
||||
result_32 = (op1_32 >> count) | (getB_CF() << (32 - count)) |
|
||||
(op1_32 << (33 - count));
|
||||
}
|
||||
}
|
||||
|
||||
/* now write result back to destination */
|
||||
if (i->modC0()) {
|
||||
BX_WRITE_32BIT_REGZ(i->rm(), result_32);
|
||||
}
|
||||
else {
|
||||
Write_RMW_virtual_dword(result_32);
|
||||
}
|
||||
/* now write result back to destination */
|
||||
if (i->modC0()) {
|
||||
BX_WRITE_32BIT_REGZ(i->rm(), result_32);
|
||||
}
|
||||
else {
|
||||
Write_RMW_virtual_dword(result_32);
|
||||
}
|
||||
|
||||
/* set eflags:
|
||||
* RCR count affects the following flags: C, O
|
||||
*/
|
||||
/* set eflags:
|
||||
* RCR count affects the following flags: C, O
|
||||
*/
|
||||
|
||||
set_CF((op1_32 >> (count - 1)) & 0x01);
|
||||
if (count == 1)
|
||||
set_OF(((op1_32 ^ result_32) & 0x80000000) > 0);
|
||||
set_CF((op1_32 >> (count - 1)) & 0x01);
|
||||
if (count == 1)
|
||||
set_OF(((op1_32 ^ result_32) & 0x80000000) > 0);
|
||||
}
|
||||
|
||||
void
|
||||
BX_CPU_C::SHL_Ed(bxInstruction_c *i)
|
||||
void BX_CPU_C::SHL_Ed(bxInstruction_c *i)
|
||||
{
|
||||
Bit32u op1_32, result_32;
|
||||
unsigned count;
|
||||
@ -326,32 +311,31 @@ BX_CPU_C::SHL_Ed(bxInstruction_c *i)
|
||||
else // (i->b1() == 0xd3)
|
||||
count = CL & 0x1f;
|
||||
|
||||
/* op1 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op1_32 = BX_READ_32BIT_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
|
||||
}
|
||||
/* op1 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op1_32 = BX_READ_32BIT_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
|
||||
}
|
||||
|
||||
if (!count) return;
|
||||
if (!count) return;
|
||||
|
||||
result_32 = (op1_32 << count);
|
||||
result_32 = (op1_32 << count);
|
||||
|
||||
/* now write result back to destination */
|
||||
if (i->modC0()) {
|
||||
BX_WRITE_32BIT_REGZ(i->rm(), result_32);
|
||||
}
|
||||
else {
|
||||
Write_RMW_virtual_dword(result_32);
|
||||
}
|
||||
/* now write result back to destination */
|
||||
if (i->modC0()) {
|
||||
BX_WRITE_32BIT_REGZ(i->rm(), result_32);
|
||||
}
|
||||
else {
|
||||
Write_RMW_virtual_dword(result_32);
|
||||
}
|
||||
|
||||
SET_FLAGS_OSZAPC_32(op1_32, count, result_32, BX_INSTR_SHL32);
|
||||
SET_FLAGS_OSZAPC_32(op1_32, count, result_32, BX_INSTR_SHL32);
|
||||
}
|
||||
|
||||
void
|
||||
BX_CPU_C::SHR_Ed(bxInstruction_c *i)
|
||||
void BX_CPU_C::SHR_Ed(bxInstruction_c *i)
|
||||
{
|
||||
Bit32u op1_32, result_32;
|
||||
unsigned count;
|
||||
@ -363,37 +347,36 @@ BX_CPU_C::SHR_Ed(bxInstruction_c *i)
|
||||
else // (i->b1() == 0xd3)
|
||||
count = CL & 0x1f;
|
||||
|
||||
/* op1 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op1_32 = BX_READ_32BIT_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
|
||||
}
|
||||
/* op1 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op1_32 = BX_READ_32BIT_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
|
||||
}
|
||||
|
||||
if (!count) return;
|
||||
|
||||
#if defined(BX_HostAsm_Shr32)
|
||||
Bit32u flags32;
|
||||
asmShr32(result_32, op1_32, count, flags32);
|
||||
setEFlagsOSZAPC(flags32);
|
||||
Bit32u flags32;
|
||||
asmShr32(result_32, op1_32, count, flags32);
|
||||
setEFlagsOSZAPC(flags32);
|
||||
#else
|
||||
result_32 = (op1_32 >> count);
|
||||
SET_FLAGS_OSZAPC_32(op1_32, count, result_32, BX_INSTR_SHR32);
|
||||
result_32 = (op1_32 >> count);
|
||||
SET_FLAGS_OSZAPC_32(op1_32, count, result_32, BX_INSTR_SHR32);
|
||||
#endif
|
||||
|
||||
/* now write result back to destination */
|
||||
if (i->modC0()) {
|
||||
BX_WRITE_32BIT_REGZ(i->rm(), result_32);
|
||||
}
|
||||
else {
|
||||
Write_RMW_virtual_dword(result_32);
|
||||
}
|
||||
/* now write result back to destination */
|
||||
if (i->modC0()) {
|
||||
BX_WRITE_32BIT_REGZ(i->rm(), result_32);
|
||||
}
|
||||
else {
|
||||
Write_RMW_virtual_dword(result_32);
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
BX_CPU_C::SAR_Ed(bxInstruction_c *i)
|
||||
void BX_CPU_C::SAR_Ed(bxInstruction_c *i)
|
||||
{
|
||||
Bit32u op1_32, result_32;
|
||||
unsigned count;
|
||||
@ -405,32 +388,32 @@ BX_CPU_C::SAR_Ed(bxInstruction_c *i)
|
||||
else // (i->b1() == 0xd3)
|
||||
count = CL & 0x1f;
|
||||
|
||||
/* op1 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op1_32 = BX_READ_32BIT_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
|
||||
}
|
||||
/* op1 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op1_32 = BX_READ_32BIT_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
|
||||
}
|
||||
|
||||
if (!count) return;
|
||||
if (!count) return;
|
||||
|
||||
/* count < 32, since only lower 5 bits used */
|
||||
if (op1_32 & 0x80000000) {
|
||||
result_32 = (op1_32 >> count) | (0xffffffff << (32 - count));
|
||||
}
|
||||
else {
|
||||
result_32 = (op1_32 >> count);
|
||||
}
|
||||
if (op1_32 & 0x80000000) {
|
||||
result_32 = (op1_32 >> count) | (0xffffffff << (32 - count));
|
||||
}
|
||||
else {
|
||||
result_32 = (op1_32 >> count);
|
||||
}
|
||||
|
||||
/* now write result back to destination */
|
||||
if (i->modC0()) {
|
||||
BX_WRITE_32BIT_REGZ(i->rm(), result_32);
|
||||
}
|
||||
else {
|
||||
Write_RMW_virtual_dword(result_32);
|
||||
}
|
||||
/* now write result back to destination */
|
||||
if (i->modC0()) {
|
||||
BX_WRITE_32BIT_REGZ(i->rm(), result_32);
|
||||
}
|
||||
else {
|
||||
Write_RMW_virtual_dword(result_32);
|
||||
}
|
||||
|
||||
SET_FLAGS_OSZAPC_32(op1_32, count, result_32, BX_INSTR_SAR32);
|
||||
SET_FLAGS_OSZAPC_32(op1_32, count, result_32, BX_INSTR_SAR32);
|
||||
}
|
||||
|
@ -1,5 +1,5 @@
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
// $Id: shift64.cc,v 1.15 2004-08-27 20:13:32 sshwarts Exp $
|
||||
// $Id: shift64.cc,v 1.16 2004-12-24 22:44:13 sshwarts Exp $
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Copyright (C) 2001 MandrakeSoft S.A.
|
||||
@ -32,8 +32,7 @@
|
||||
|
||||
#if BX_SUPPORT_X86_64
|
||||
|
||||
void
|
||||
BX_CPU_C::SHLD_EqGq(bxInstruction_c *i)
|
||||
void BX_CPU_C::SHLD_EqGq(bxInstruction_c *i)
|
||||
{
|
||||
Bit64u op1_64, op2_64, result_64;
|
||||
unsigned count;
|
||||
@ -45,42 +44,36 @@ BX_CPU_C::SHLD_EqGq(bxInstruction_c *i)
|
||||
else // 0x1a5
|
||||
count = CL & 0x3f;
|
||||
|
||||
if (!count) return; /* NOP */
|
||||
/* op1 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op1_64 = BX_READ_64BIT_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
read_RMW_virtual_qword(i->seg(), RMAddr(i), &op1_64);
|
||||
}
|
||||
|
||||
/* op1 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op1_64 = BX_READ_64BIT_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
read_RMW_virtual_qword(i->seg(), RMAddr(i), &op1_64);
|
||||
}
|
||||
op2_64 = BX_READ_64BIT_REG(i->nnn());
|
||||
if (!count) return;
|
||||
|
||||
result_64 = (op1_64 << count) | (op2_64 >> (64 - count));
|
||||
op2_64 = BX_READ_64BIT_REG(i->nnn());
|
||||
|
||||
/* now write result back to destination */
|
||||
if (i->modC0()) {
|
||||
BX_WRITE_64BIT_REG(i->rm(), result_64);
|
||||
}
|
||||
else {
|
||||
Write_RMW_virtual_qword(result_64);
|
||||
}
|
||||
result_64 = (op1_64 << count) | (op2_64 >> (64 - count));
|
||||
|
||||
/* set eflags:
|
||||
* SHLD count affects the following flags: S,Z,P,C,O
|
||||
*/
|
||||
set_CF((op1_64 >> (64 - count)) & 0x01);
|
||||
if (count == 1)
|
||||
set_OF(((op1_64 ^ result_64) & BX_CONST64(0x8000000000000000)) > 0);
|
||||
set_AF(0);
|
||||
set_ZF(result_64 == 0);
|
||||
set_PF_base(result_64);
|
||||
set_SF(result_64 >> 63);
|
||||
/* now write result back to destination */
|
||||
if (i->modC0()) {
|
||||
BX_WRITE_64BIT_REG(i->rm(), result_64);
|
||||
}
|
||||
else {
|
||||
Write_RMW_virtual_qword(result_64);
|
||||
}
|
||||
|
||||
/* set eflags:
|
||||
* SHLD count affects the following flags: O,S,Z,A,P,C
|
||||
*/
|
||||
SET_FLAGS_OSZAPC_64(op1_64, count, result_64, BX_INSTR_SHL64);
|
||||
}
|
||||
|
||||
void
|
||||
BX_CPU_C::SHRD_EqGq(bxInstruction_c *i)
|
||||
void BX_CPU_C::SHRD_EqGq(bxInstruction_c *i)
|
||||
{
|
||||
Bit64u op1_64, op2_64, result_64;
|
||||
unsigned count;
|
||||
@ -90,44 +83,44 @@ BX_CPU_C::SHRD_EqGq(bxInstruction_c *i)
|
||||
else // 0x1ad
|
||||
count = CL & 0x3f;
|
||||
|
||||
if (!count) return; /* NOP */
|
||||
/* op1 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op1_64 = BX_READ_64BIT_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
read_RMW_virtual_qword(i->seg(), RMAddr(i), &op1_64);
|
||||
}
|
||||
|
||||
/* op1 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op1_64 = BX_READ_64BIT_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
read_RMW_virtual_qword(i->seg(), RMAddr(i), &op1_64);
|
||||
}
|
||||
op2_64 = BX_READ_64BIT_REG(i->nnn());
|
||||
if (!count) return;
|
||||
|
||||
result_64 = (op2_64 << (64 - count)) | (op1_64 >> count);
|
||||
op2_64 = BX_READ_64BIT_REG(i->nnn());
|
||||
|
||||
/* now write result back to destination */
|
||||
if (i->modC0()) {
|
||||
BX_WRITE_64BIT_REG(i->rm(), result_64);
|
||||
}
|
||||
else {
|
||||
Write_RMW_virtual_qword(result_64);
|
||||
}
|
||||
result_64 = (op2_64 << (64 - count)) | (op1_64 >> count);
|
||||
|
||||
/* set eflags:
|
||||
* SHRD count affects the following flags: S,Z,P,C,O
|
||||
*/
|
||||
/* now write result back to destination */
|
||||
if (i->modC0()) {
|
||||
BX_WRITE_64BIT_REG(i->rm(), result_64);
|
||||
}
|
||||
else {
|
||||
Write_RMW_virtual_qword(result_64);
|
||||
}
|
||||
|
||||
set_CF((op1_64 >> (count - 1)) & 0x01);
|
||||
set_ZF(result_64 == 0);
|
||||
set_SF(result_64 >> 63);
|
||||
set_AF(0);
|
||||
/* for shift of 1, OF set if sign change occurred. */
|
||||
if (count == 1)
|
||||
set_OF(((op1_64 ^ result_64) & BX_CONST64(0x8000000000000000)) > 0);
|
||||
set_PF_base(result_64);
|
||||
/* set eflags:
|
||||
* SHRD count affects the following flags: S,Z,P,C,O
|
||||
*/
|
||||
|
||||
set_CF((op1_64 >> (count - 1)) & 0x01);
|
||||
set_ZF(result_64 == 0);
|
||||
set_SF(result_64 >> 63);
|
||||
set_AF(0);
|
||||
/* for shift of 1, OF set if sign change occurred. */
|
||||
if (count == 1)
|
||||
set_OF(((op1_64 ^ result_64) & BX_CONST64(0x8000000000000000)) > 0);
|
||||
set_PF_base(result_64);
|
||||
}
|
||||
|
||||
void
|
||||
BX_CPU_C::ROL_Eq(bxInstruction_c *i)
|
||||
void BX_CPU_C::ROL_Eq(bxInstruction_c *i)
|
||||
{
|
||||
Bit64u op1_64, result_64;
|
||||
unsigned count;
|
||||
@ -139,38 +132,37 @@ BX_CPU_C::ROL_Eq(bxInstruction_c *i)
|
||||
else // (i->b1() == 0xd3)
|
||||
count = CL & 0x3f;
|
||||
|
||||
/* op1 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op1_64 = BX_READ_64BIT_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
read_RMW_virtual_qword(i->seg(), RMAddr(i), &op1_64);
|
||||
}
|
||||
/* op1 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op1_64 = BX_READ_64BIT_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
read_RMW_virtual_qword(i->seg(), RMAddr(i), &op1_64);
|
||||
}
|
||||
|
||||
if (! count) return;
|
||||
if (! count) return;
|
||||
|
||||
result_64 = (op1_64 << count) | (op1_64 >> (64 - count));
|
||||
result_64 = (op1_64 << count) | (op1_64 >> (64 - count));
|
||||
|
||||
/* now write result back to destination */
|
||||
if (i->modC0()) {
|
||||
BX_WRITE_64BIT_REG(i->rm(), result_64);
|
||||
}
|
||||
else {
|
||||
Write_RMW_virtual_qword(result_64);
|
||||
}
|
||||
/* now write result back to destination */
|
||||
if (i->modC0()) {
|
||||
BX_WRITE_64BIT_REG(i->rm(), result_64);
|
||||
}
|
||||
else {
|
||||
Write_RMW_virtual_qword(result_64);
|
||||
}
|
||||
|
||||
/* set eflags:
|
||||
* ROL count affects the following flags: C, O
|
||||
*/
|
||||
bx_bool temp_CF = (result_64 & 0x01);
|
||||
/* set eflags:
|
||||
* ROL count affects the following flags: C, O
|
||||
*/
|
||||
bx_bool temp_CF = (result_64 & 0x01);
|
||||
|
||||
set_CF(temp_CF);
|
||||
set_OF(temp_CF ^ (result_64 >> 63));
|
||||
set_CF(temp_CF);
|
||||
set_OF(temp_CF ^ (result_64 >> 63));
|
||||
}
|
||||
|
||||
void
|
||||
BX_CPU_C::ROR_Eq(bxInstruction_c *i)
|
||||
void BX_CPU_C::ROR_Eq(bxInstruction_c *i)
|
||||
{
|
||||
Bit64u op1_64, result_64;
|
||||
unsigned count;
|
||||
@ -182,39 +174,38 @@ BX_CPU_C::ROR_Eq(bxInstruction_c *i)
|
||||
else // (i->b1() == 0xd3)
|
||||
count = CL & 0x3f;
|
||||
|
||||
/* op1 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op1_64 = BX_READ_64BIT_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
read_RMW_virtual_qword(i->seg(), RMAddr(i), &op1_64);
|
||||
}
|
||||
/* op1 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op1_64 = BX_READ_64BIT_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
read_RMW_virtual_qword(i->seg(), RMAddr(i), &op1_64);
|
||||
}
|
||||
|
||||
if (! count) return;
|
||||
if (! count) return;
|
||||
|
||||
result_64 = (op1_64 >> count) | (op1_64 << (64 - count));
|
||||
result_64 = (op1_64 >> count) | (op1_64 << (64 - count));
|
||||
|
||||
/* now write result back to destination */
|
||||
if (i->modC0()) {
|
||||
BX_WRITE_64BIT_REG(i->rm(), result_64);
|
||||
}
|
||||
else {
|
||||
Write_RMW_virtual_qword(result_64);
|
||||
}
|
||||
/* now write result back to destination */
|
||||
if (i->modC0()) {
|
||||
BX_WRITE_64BIT_REG(i->rm(), result_64);
|
||||
}
|
||||
else {
|
||||
Write_RMW_virtual_qword(result_64);
|
||||
}
|
||||
|
||||
/* set eflags:
|
||||
* ROR count affects the following flags: C, O
|
||||
*/
|
||||
bx_bool result_b63 = (result_64 & BX_CONST64(0x8000000000000000)) != 0;
|
||||
/* set eflags:
|
||||
* ROR count affects the following flags: C, O
|
||||
*/
|
||||
bx_bool result_b63 = (result_64 & BX_CONST64(0x8000000000000000)) != 0;
|
||||
|
||||
set_CF(result_b63);
|
||||
if (count == 1)
|
||||
set_OF(((op1_64 ^ result_64) & BX_CONST64(0x8000000000000000)) > 0);
|
||||
set_CF(result_b63);
|
||||
if (count == 1)
|
||||
set_OF(((op1_64 ^ result_64) & BX_CONST64(0x8000000000000000)) > 0);
|
||||
}
|
||||
|
||||
void
|
||||
BX_CPU_C::RCL_Eq(bxInstruction_c *i)
|
||||
void BX_CPU_C::RCL_Eq(bxInstruction_c *i)
|
||||
{
|
||||
Bit64u op1_64, result_64;
|
||||
unsigned count;
|
||||
@ -226,45 +217,43 @@ BX_CPU_C::RCL_Eq(bxInstruction_c *i)
|
||||
else // (i->b1() == 0xd3)
|
||||
count = CL & 0x3f;
|
||||
|
||||
/* op1 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op1_64 = BX_READ_64BIT_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
read_RMW_virtual_qword(i->seg(), RMAddr(i), &op1_64);
|
||||
}
|
||||
/* op1 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op1_64 = BX_READ_64BIT_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
read_RMW_virtual_qword(i->seg(), RMAddr(i), &op1_64);
|
||||
}
|
||||
|
||||
if (!count) return;
|
||||
if (!count) return;
|
||||
|
||||
if (count==1) {
|
||||
result_64 = (op1_64 << 1) | getB_CF();
|
||||
}
|
||||
else {
|
||||
result_64 = (op1_64 << count) |
|
||||
(getB_CF() << (count - 1)) |
|
||||
if (count==1) {
|
||||
result_64 = (op1_64 << 1) | getB_CF();
|
||||
}
|
||||
else {
|
||||
result_64 = (op1_64 << count) | (getB_CF() << (count - 1)) |
|
||||
(op1_64 >> (65 - count));
|
||||
}
|
||||
}
|
||||
|
||||
/* now write result back to destination */
|
||||
if (i->modC0()) {
|
||||
BX_WRITE_64BIT_REG(i->rm(), result_64);
|
||||
}
|
||||
else {
|
||||
Write_RMW_virtual_qword(result_64);
|
||||
}
|
||||
/* now write result back to destination */
|
||||
if (i->modC0()) {
|
||||
BX_WRITE_64BIT_REG(i->rm(), result_64);
|
||||
}
|
||||
else {
|
||||
Write_RMW_virtual_qword(result_64);
|
||||
}
|
||||
|
||||
/* set eflags:
|
||||
* RCL count affects the following flags: C, O
|
||||
*/
|
||||
bx_bool temp_CF = (op1_64 >> (64 - count)) & 0x01;
|
||||
/* set eflags:
|
||||
* RCL count affects the following flags: C, O
|
||||
*/
|
||||
bx_bool temp_CF = (op1_64 >> (64 - count)) & 0x01;
|
||||
|
||||
set_CF(temp_CF);
|
||||
set_OF(temp_CF ^ (result_64 >> 63));
|
||||
set_CF(temp_CF);
|
||||
set_OF(temp_CF ^ (result_64 >> 63));
|
||||
}
|
||||
|
||||
void
|
||||
BX_CPU_C::RCR_Eq(bxInstruction_c *i)
|
||||
void BX_CPU_C::RCR_Eq(bxInstruction_c *i)
|
||||
{
|
||||
Bit64u op1_64, result_64;
|
||||
unsigned count;
|
||||
@ -276,45 +265,43 @@ BX_CPU_C::RCR_Eq(bxInstruction_c *i)
|
||||
else // (i->b1() == 0xd3)
|
||||
count = CL & 0x3f;
|
||||
|
||||
/* op1 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op1_64 = BX_READ_64BIT_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
read_RMW_virtual_qword(i->seg(), RMAddr(i), &op1_64);
|
||||
}
|
||||
/* op1 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op1_64 = BX_READ_64BIT_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
read_RMW_virtual_qword(i->seg(), RMAddr(i), &op1_64);
|
||||
}
|
||||
|
||||
if (!count) return;
|
||||
if (!count) return;
|
||||
|
||||
if (count==1) {
|
||||
result_64 = (op1_64 >> 1) | (((Bit64u) getB_CF()) << 63);
|
||||
}
|
||||
else {
|
||||
result_64 = (op1_64 >> count) |
|
||||
(getB_CF() << (64 - count)) |
|
||||
if (count==1) {
|
||||
result_64 = (op1_64 >> 1) | (((Bit64u) getB_CF()) << 63);
|
||||
}
|
||||
else {
|
||||
result_64 = (op1_64 >> count) | (getB_CF() << (64 - count)) |
|
||||
(op1_64 << (65 - count));
|
||||
}
|
||||
}
|
||||
|
||||
/* now write result back to destination */
|
||||
if (i->modC0()) {
|
||||
BX_WRITE_64BIT_REG(i->rm(), result_64);
|
||||
}
|
||||
else {
|
||||
Write_RMW_virtual_qword(result_64);
|
||||
}
|
||||
/* now write result back to destination */
|
||||
if (i->modC0()) {
|
||||
BX_WRITE_64BIT_REG(i->rm(), result_64);
|
||||
}
|
||||
else {
|
||||
Write_RMW_virtual_qword(result_64);
|
||||
}
|
||||
|
||||
/* set eflags:
|
||||
* RCR count affects the following flags: C, O
|
||||
*/
|
||||
/* set eflags:
|
||||
* RCR count affects the following flags: C, O
|
||||
*/
|
||||
|
||||
set_CF((op1_64 >> (count - 1)) & 0x01);
|
||||
if (count == 1)
|
||||
set_OF(((op1_64 ^ result_64) & BX_CONST64(0x8000000000000000)) > 0);
|
||||
set_CF((op1_64 >> (count - 1)) & 0x01);
|
||||
if (count == 1)
|
||||
set_OF(((op1_64 ^ result_64) & BX_CONST64(0x8000000000000000)) > 0);
|
||||
}
|
||||
|
||||
void
|
||||
BX_CPU_C::SHL_Eq(bxInstruction_c *i)
|
||||
void BX_CPU_C::SHL_Eq(bxInstruction_c *i)
|
||||
{
|
||||
Bit64u op1_64, result_64;
|
||||
unsigned count;
|
||||
@ -326,32 +313,31 @@ BX_CPU_C::SHL_Eq(bxInstruction_c *i)
|
||||
else // (i->b1() == 0xd3)
|
||||
count = CL & 0x3f;
|
||||
|
||||
/* op1 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op1_64 = BX_READ_64BIT_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
read_RMW_virtual_qword(i->seg(), RMAddr(i), &op1_64);
|
||||
}
|
||||
/* op1 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op1_64 = BX_READ_64BIT_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
read_RMW_virtual_qword(i->seg(), RMAddr(i), &op1_64);
|
||||
}
|
||||
|
||||
if (!count) return;
|
||||
if (!count) return;
|
||||
|
||||
result_64 = (op1_64 << count);
|
||||
result_64 = (op1_64 << count);
|
||||
|
||||
/* now write result back to destination */
|
||||
if (i->modC0()) {
|
||||
BX_WRITE_64BIT_REG(i->rm(), result_64);
|
||||
}
|
||||
else {
|
||||
Write_RMW_virtual_qword(result_64);
|
||||
}
|
||||
/* now write result back to destination */
|
||||
if (i->modC0()) {
|
||||
BX_WRITE_64BIT_REG(i->rm(), result_64);
|
||||
}
|
||||
else {
|
||||
Write_RMW_virtual_qword(result_64);
|
||||
}
|
||||
|
||||
SET_FLAGS_OSZAPC_64(op1_64, count, result_64, BX_INSTR_SHL64);
|
||||
SET_FLAGS_OSZAPC_64(op1_64, count, result_64, BX_INSTR_SHL64);
|
||||
}
|
||||
|
||||
void
|
||||
BX_CPU_C::SHR_Eq(bxInstruction_c *i)
|
||||
void BX_CPU_C::SHR_Eq(bxInstruction_c *i)
|
||||
{
|
||||
Bit64u op1_64, result_64;
|
||||
unsigned count;
|
||||
@ -363,71 +349,70 @@ BX_CPU_C::SHR_Eq(bxInstruction_c *i)
|
||||
else // (i->b1() == 0xd3)
|
||||
count = CL & 0x3f;
|
||||
|
||||
/* op1 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
/* op1 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op1_64 = BX_READ_64BIT_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
read_RMW_virtual_qword(i->seg(), RMAddr(i), &op1_64);
|
||||
}
|
||||
|
||||
if (!count) return;
|
||||
|
||||
result_64 = (op1_64 >> count);
|
||||
|
||||
/* now write result back to destination */
|
||||
if (i->modC0()) {
|
||||
BX_WRITE_64BIT_REG(i->rm(), result_64);
|
||||
}
|
||||
else {
|
||||
Write_RMW_virtual_qword(result_64);
|
||||
}
|
||||
|
||||
SET_FLAGS_OSZAPC_64(op1_64, count, result_64, BX_INSTR_SHR64);
|
||||
}
|
||||
|
||||
void BX_CPU_C::SAR_Eq(bxInstruction_c *i)
|
||||
{
|
||||
Bit64u op1_64, result_64;
|
||||
unsigned count;
|
||||
|
||||
if (i->b1() == 0xc1)
|
||||
count = i->Ib() & 0x3f;
|
||||
else if (i->b1() == 0xd1)
|
||||
count = 1;
|
||||
else // (i->b1() == 0xd3)
|
||||
count = CL & 0x3f;
|
||||
|
||||
/* op1 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op1_64 = BX_READ_64BIT_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
read_RMW_virtual_qword(i->seg(), RMAddr(i), &op1_64);
|
||||
}
|
||||
}
|
||||
|
||||
if (!count) return;
|
||||
if (!count) return;
|
||||
|
||||
/* count < 64, since only lower 5 bits used */
|
||||
if (op1_64 & BX_CONST64(0x8000000000000000)) {
|
||||
result_64 = (op1_64 >> count) | (BX_CONST64(0xffffffffffffffff) << (64 - count));
|
||||
}
|
||||
else {
|
||||
result_64 = (op1_64 >> count);
|
||||
}
|
||||
|
||||
/* now write result back to destination */
|
||||
if (i->modC0()) {
|
||||
BX_WRITE_64BIT_REG(i->rm(), result_64);
|
||||
}
|
||||
else {
|
||||
Write_RMW_virtual_qword(result_64);
|
||||
}
|
||||
/* now write result back to destination */
|
||||
if (i->modC0()) {
|
||||
BX_WRITE_64BIT_REG(i->rm(), result_64);
|
||||
}
|
||||
else {
|
||||
Write_RMW_virtual_qword(result_64);
|
||||
}
|
||||
|
||||
SET_FLAGS_OSZAPC_64(op1_64, count, result_64, BX_INSTR_SHR64);
|
||||
}
|
||||
|
||||
void
|
||||
BX_CPU_C::SAR_Eq(bxInstruction_c *i)
|
||||
{
|
||||
Bit64u op1_64, result_64;
|
||||
unsigned count;
|
||||
|
||||
if (i->b1() == 0xc1)
|
||||
count = i->Ib() & 0x3f;
|
||||
else if (i->b1() == 0xd1)
|
||||
count = 1;
|
||||
else // (i->b1() == 0xd3)
|
||||
count = CL & 0x3f;
|
||||
|
||||
/* op1 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op1_64 = BX_READ_64BIT_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
read_RMW_virtual_qword(i->seg(), RMAddr(i), &op1_64);
|
||||
}
|
||||
|
||||
if (!count) return;
|
||||
|
||||
/* count < 64, since only lower 5 bits used */
|
||||
if (op1_64 & BX_CONST64(0x8000000000000000)) {
|
||||
result_64 = (op1_64 >> count) | (BX_CONST64(0xffffffffffffffff) << (64 - count));
|
||||
}
|
||||
else {
|
||||
result_64 = (op1_64 >> count);
|
||||
}
|
||||
|
||||
/* now write result back to destination */
|
||||
if (i->modC0()) {
|
||||
BX_WRITE_64BIT_REG(i->rm(), result_64);
|
||||
}
|
||||
else {
|
||||
Write_RMW_virtual_qword(result_64);
|
||||
}
|
||||
|
||||
SET_FLAGS_OSZAPC_64(op1_64, count, result_64, BX_INSTR_SAR64);
|
||||
SET_FLAGS_OSZAPC_64(op1_64, count, result_64, BX_INSTR_SAR64);
|
||||
}
|
||||
|
||||
#endif /* if BX_SUPPORT_X86_64 */
|
||||
|
@ -1,5 +1,5 @@
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
// $Id: shift8.cc,v 1.19 2004-09-04 19:37:37 sshwarts Exp $
|
||||
// $Id: shift8.cc,v 1.20 2004-12-24 22:44:13 sshwarts Exp $
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Copyright (C) 2001 MandrakeSoft S.A.
|
||||
@ -30,53 +30,7 @@
|
||||
#define LOG_THIS BX_CPU_THIS_PTR
|
||||
|
||||
|
||||
void
|
||||
BX_CPU_C::ROL_Eb(bxInstruction_c *i)
|
||||
{
|
||||
Bit8u op1_8, result_8;
|
||||
unsigned count;
|
||||
|
||||
if (i->b1() == 0xc0)
|
||||
count = i->Ib();
|
||||
else if (i->b1() == 0xd0)
|
||||
count = 1;
|
||||
else // 0xd2
|
||||
count = CL;
|
||||
|
||||
count &= 0x07; // use only lowest 3 bits
|
||||
|
||||
/* op1 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op1_8 = BX_READ_8BIT_REGx(i->rm(),i->extend8bitL());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
read_RMW_virtual_byte(i->seg(), RMAddr(i), &op1_8);
|
||||
}
|
||||
|
||||
if (! count) return;
|
||||
|
||||
result_8 = (op1_8 << count) | (op1_8 >> (8 - count));
|
||||
|
||||
/* now write result back to destination */
|
||||
if (i->modC0()) {
|
||||
BX_WRITE_8BIT_REGx(i->rm(), i->extend8bitL(), result_8);
|
||||
}
|
||||
else {
|
||||
Write_RMW_virtual_byte(result_8);
|
||||
}
|
||||
|
||||
/* set eflags:
|
||||
* ROL count affects the following flags: C, O
|
||||
*/
|
||||
bx_bool temp_CF = (result_8 & 0x01);
|
||||
|
||||
set_CF(temp_CF);
|
||||
set_OF(temp_CF ^ (result_8 >> 7));
|
||||
}
|
||||
|
||||
void
|
||||
BX_CPU_C::ROR_Eb(bxInstruction_c *i)
|
||||
void BX_CPU_C::ROL_Eb(bxInstruction_c *i)
|
||||
{
|
||||
Bit8u op1_8, result_8;
|
||||
unsigned count;
|
||||
@ -93,36 +47,34 @@ BX_CPU_C::ROR_Eb(bxInstruction_c *i)
|
||||
/* op1 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op1_8 = BX_READ_8BIT_REGx(i->rm(),i->extend8bitL());
|
||||
}
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
read_RMW_virtual_byte(i->seg(), RMAddr(i), &op1_8);
|
||||
}
|
||||
}
|
||||
|
||||
if (! count) return;
|
||||
if (! count) return;
|
||||
|
||||
result_8 = (op1_8 >> count) | (op1_8 << (8 - count));
|
||||
result_8 = (op1_8 << count) | (op1_8 >> (8 - count));
|
||||
|
||||
/* now write result back to destination */
|
||||
if (i->modC0()) {
|
||||
BX_WRITE_8BIT_REGx(i->rm(), i->extend8bitL(), result_8);
|
||||
}
|
||||
else {
|
||||
Write_RMW_virtual_byte(result_8);
|
||||
}
|
||||
/* now write result back to destination */
|
||||
if (i->modC0()) {
|
||||
BX_WRITE_8BIT_REGx(i->rm(), i->extend8bitL(), result_8);
|
||||
}
|
||||
else {
|
||||
Write_RMW_virtual_byte(result_8);
|
||||
}
|
||||
|
||||
/* set eflags:
|
||||
* ROR count affects the following flags: C, O
|
||||
*/
|
||||
bx_bool result_b7 = (result_8 & 0x80) != 0;
|
||||
/* set eflags:
|
||||
* ROL count affects the following flags: C, O
|
||||
*/
|
||||
bx_bool temp_CF = (result_8 & 0x01);
|
||||
|
||||
set_CF(result_b7);
|
||||
if (count == 1)
|
||||
set_OF(((op1_8 ^ result_8) & 0x80) > 0);
|
||||
set_CF(temp_CF);
|
||||
set_OF(temp_CF ^ (result_8 >> 7));
|
||||
}
|
||||
|
||||
void
|
||||
BX_CPU_C::RCL_Eb(bxInstruction_c *i)
|
||||
void BX_CPU_C::ROR_Eb(bxInstruction_c *i)
|
||||
{
|
||||
Bit8u op1_8, result_8;
|
||||
unsigned count;
|
||||
@ -134,16 +86,61 @@ BX_CPU_C::RCL_Eb(bxInstruction_c *i)
|
||||
else // 0xd2
|
||||
count = CL;
|
||||
|
||||
count %= 9;
|
||||
count &= 0x07; /* use only bottom 3 bits */
|
||||
|
||||
/* op1 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op1_8 = BX_READ_8BIT_REGx(i->rm(),i->extend8bitL());
|
||||
}
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
read_RMW_virtual_byte(i->seg(), RMAddr(i), &op1_8);
|
||||
}
|
||||
}
|
||||
|
||||
if (! count) return;
|
||||
|
||||
result_8 = (op1_8 >> count) | (op1_8 << (8 - count));
|
||||
|
||||
/* now write result back to destination */
|
||||
if (i->modC0()) {
|
||||
BX_WRITE_8BIT_REGx(i->rm(), i->extend8bitL(), result_8);
|
||||
}
|
||||
else {
|
||||
Write_RMW_virtual_byte(result_8);
|
||||
}
|
||||
|
||||
/* set eflags:
|
||||
* ROR count affects the following flags: C, O
|
||||
*/
|
||||
bx_bool result_b7 = (result_8 & 0x80) != 0;
|
||||
|
||||
set_CF(result_b7);
|
||||
if (count == 1)
|
||||
set_OF(((op1_8 ^ result_8) & 0x80) > 0);
|
||||
}
|
||||
|
||||
void BX_CPU_C::RCL_Eb(bxInstruction_c *i)
|
||||
{
|
||||
Bit8u op1_8, result_8;
|
||||
unsigned count;
|
||||
|
||||
if (i->b1() == 0xc0)
|
||||
count = i->Ib();
|
||||
else if (i->b1() == 0xd0)
|
||||
count = 1;
|
||||
else // 0xd2
|
||||
count = CL;
|
||||
|
||||
count &= 0x07; /* use only bottom 3 bits */
|
||||
|
||||
/* op1 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op1_8 = BX_READ_8BIT_REGx(i->rm(),i->extend8bitL());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
read_RMW_virtual_byte(i->seg(), RMAddr(i), &op1_8);
|
||||
}
|
||||
|
||||
if (! count) return;
|
||||
|
||||
@ -151,18 +148,17 @@ BX_CPU_C::RCL_Eb(bxInstruction_c *i)
|
||||
result_8 = (op1_8 << 1) | getB_CF();
|
||||
}
|
||||
else {
|
||||
result_8 = (op1_8 << count) |
|
||||
(getB_CF() << (count - 1)) |
|
||||
result_8 = (op1_8 << count) | (getB_CF() << (count - 1)) |
|
||||
(op1_8 >> (9 - count));
|
||||
}
|
||||
|
||||
/* now write result back to destination */
|
||||
if (i->modC0()) {
|
||||
BX_WRITE_8BIT_REGx(i->rm(), i->extend8bitL(), result_8);
|
||||
}
|
||||
}
|
||||
else {
|
||||
Write_RMW_virtual_byte(result_8);
|
||||
}
|
||||
}
|
||||
|
||||
/* set eflags:
|
||||
* RCL count affects the following flags: C, O
|
||||
@ -173,8 +169,7 @@ BX_CPU_C::RCL_Eb(bxInstruction_c *i)
|
||||
set_OF(temp_CF ^ (result_8 >> 7));
|
||||
}
|
||||
|
||||
void
|
||||
BX_CPU_C::RCR_Eb(bxInstruction_c *i)
|
||||
void BX_CPU_C::RCR_Eb(bxInstruction_c *i)
|
||||
{
|
||||
Bit8u op1_8, result_8;
|
||||
unsigned count;
|
||||
@ -186,42 +181,40 @@ BX_CPU_C::RCR_Eb(bxInstruction_c *i)
|
||||
else // 0xd2
|
||||
count = CL;
|
||||
|
||||
count %= 9;
|
||||
count &= 0x07; /* use only bottom 3 bits */
|
||||
|
||||
/* op1 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op1_8 = BX_READ_8BIT_REGx(i->rm(),i->extend8bitL());
|
||||
}
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
read_RMW_virtual_byte(i->seg(), RMAddr(i), &op1_8);
|
||||
}
|
||||
}
|
||||
|
||||
if (! count) return;
|
||||
|
||||
result_8 = (op1_8 >> count) |
|
||||
(getB_CF() << (8 - count)) |
|
||||
result_8 = (op1_8 >> count) | (getB_CF() << (8 - count)) |
|
||||
(op1_8 << (9 - count));
|
||||
|
||||
/* now write result back to destination */
|
||||
if (i->modC0()) {
|
||||
BX_WRITE_8BIT_REGx(i->rm(), i->extend8bitL(), result_8);
|
||||
}
|
||||
else {
|
||||
Write_RMW_virtual_byte(result_8);
|
||||
}
|
||||
/* now write result back to destination */
|
||||
if (i->modC0()) {
|
||||
BX_WRITE_8BIT_REGx(i->rm(), i->extend8bitL(), result_8);
|
||||
}
|
||||
else {
|
||||
Write_RMW_virtual_byte(result_8);
|
||||
}
|
||||
|
||||
/* set eflags:
|
||||
* RCR count affects the following flags: C, O
|
||||
*/
|
||||
/* set eflags:
|
||||
* RCR count affects the following flags: C, O
|
||||
*/
|
||||
|
||||
set_CF((op1_8 >> (count - 1)) & 0x01);
|
||||
if (count == 1)
|
||||
set_OF(((op1_8 ^ result_8) & 0x80) > 0);
|
||||
set_CF((op1_8 >> (count - 1)) & 0x01);
|
||||
if (count == 1)
|
||||
set_OF(((op1_8 ^ result_8) & 0x80) > 0);
|
||||
}
|
||||
|
||||
void
|
||||
BX_CPU_C::SHL_Eb(bxInstruction_c *i)
|
||||
void BX_CPU_C::SHL_Eb(bxInstruction_c *i)
|
||||
{
|
||||
Bit8u op1_8, result_8;
|
||||
unsigned count;
|
||||
@ -233,16 +226,16 @@ BX_CPU_C::SHL_Eb(bxInstruction_c *i)
|
||||
else // 0xd2
|
||||
count = CL;
|
||||
|
||||
count &= 0x1F;
|
||||
count &= 0x1f;
|
||||
|
||||
/* op1 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op1_8 = BX_READ_8BIT_REGx(i->rm(),i->extend8bitL());
|
||||
}
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
read_RMW_virtual_byte(i->seg(), RMAddr(i), &op1_8);
|
||||
}
|
||||
}
|
||||
|
||||
if (!count) return;
|
||||
|
||||
@ -251,17 +244,16 @@ BX_CPU_C::SHL_Eb(bxInstruction_c *i)
|
||||
/* now write result back to destination */
|
||||
if (i->modC0()) {
|
||||
BX_WRITE_8BIT_REGx(i->rm(), i->extend8bitL(), result_8);
|
||||
}
|
||||
}
|
||||
else {
|
||||
Write_RMW_virtual_byte(result_8);
|
||||
}
|
||||
}
|
||||
|
||||
SET_FLAGS_OSZAPC_8(op1_8, count, result_8, BX_INSTR_SHL8);
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
BX_CPU_C::SHR_Eb(bxInstruction_c *i)
|
||||
void BX_CPU_C::SHR_Eb(bxInstruction_c *i)
|
||||
{
|
||||
Bit8u op1_8, result_8;
|
||||
unsigned count;
|
||||
@ -273,16 +265,16 @@ BX_CPU_C::SHR_Eb(bxInstruction_c *i)
|
||||
else // 0xd2
|
||||
count = CL;
|
||||
|
||||
count &= 0x1F;
|
||||
count &= 0x1f;
|
||||
|
||||
/* op1 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op1_8 = BX_READ_8BIT_REGx(i->rm(),i->extend8bitL());
|
||||
}
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
read_RMW_virtual_byte(i->seg(), RMAddr(i), &op1_8);
|
||||
}
|
||||
}
|
||||
|
||||
if (!count) return;
|
||||
|
||||
@ -291,16 +283,15 @@ BX_CPU_C::SHR_Eb(bxInstruction_c *i)
|
||||
/* now write result back to destination */
|
||||
if (i->modC0()) {
|
||||
BX_WRITE_8BIT_REGx(i->rm(), i->extend8bitL(), result_8);
|
||||
}
|
||||
}
|
||||
else {
|
||||
Write_RMW_virtual_byte(result_8);
|
||||
}
|
||||
}
|
||||
|
||||
SET_FLAGS_OSZAPC_8(op1_8, count, result_8, BX_INSTR_SHR8);
|
||||
}
|
||||
|
||||
void
|
||||
BX_CPU_C::SAR_Eb(bxInstruction_c *i)
|
||||
void BX_CPU_C::SAR_Eb(bxInstruction_c *i)
|
||||
{
|
||||
Bit8u op1_8, result_8;
|
||||
unsigned count;
|
||||
@ -312,43 +303,43 @@ BX_CPU_C::SAR_Eb(bxInstruction_c *i)
|
||||
else // 0xd2
|
||||
count = CL;
|
||||
|
||||
count &= 0x1F;
|
||||
count &= 0x1f;
|
||||
|
||||
/* op1 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op1_8 = BX_READ_8BIT_REGx(i->rm(),i->extend8bitL());
|
||||
}
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
read_RMW_virtual_byte(i->seg(), RMAddr(i), &op1_8);
|
||||
}
|
||||
}
|
||||
|
||||
if (!count) return;
|
||||
|
||||
if (count < 8) {
|
||||
if (op1_8 & 0x80) {
|
||||
result_8 = (op1_8 >> count) | (0xff << (8 - count));
|
||||
}
|
||||
}
|
||||
else {
|
||||
result_8 = (op1_8 >> count);
|
||||
}
|
||||
}
|
||||
}
|
||||
else {
|
||||
if (op1_8 & 0x80) {
|
||||
result_8 = 0xff;
|
||||
}
|
||||
}
|
||||
else {
|
||||
result_8 = 0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* now write result back to destination */
|
||||
if (i->modC0()) {
|
||||
BX_WRITE_8BIT_REGx(i->rm(), i->extend8bitL(), result_8);
|
||||
}
|
||||
}
|
||||
else {
|
||||
Write_RMW_virtual_byte(result_8);
|
||||
}
|
||||
}
|
||||
|
||||
SET_FLAGS_OSZAPC_8(op1_8, count, result_8, BX_INSTR_SAR8);
|
||||
}
|
||||
|
Loading…
x
Reference in New Issue
Block a user