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- added comment clarifying that Greg wrote it, and that it's not linked 

with the rest of Bochs yet.
This commit is contained in:
Bryce Denney 2001-05-25 13:11:52 +00:00
parent 5e2d6aba63
commit 8d3c28d3de
1 changed files with 13 additions and 8 deletions
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21
bochs/iodev/pit82c54.cc
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@ -1,8 +1,13 @@
/*
*Emulator of an Intel 8254/82C54 Programmable Interval Timer.
* Emulator of an Intel 8254/82C54 Programmable Interval Timer.
* Greg Alexander <yakovlev@usa.com>
*
*Things I am unclear on:
*1.)What happens if both the status and count registers are latched,
* This code is not yet linked into Bochs, but has been included so
* that you can experiment with it. (bbd)
*
*
* Things I am unclear on (greg):
* 1.)What happens if both the status and count registers are latched,
* but the first of the two count registers has already been read?
* I.E.:
* latch count 0 (16-bit)
@ -10,13 +15,13 @@
* READ_BACK status of count 0
* Read count 0 - do you get MSByte or status?
* This will be flagged as an error.
*2.)What happens when we latch the output in the middle of a 2-part
* 2.)What happens when we latch the output in the middle of a 2-part
* unlatched read?
*3.)I assumed that programming a counter removes a latched status.
*4.)I implemented the 8254 description of mode 0, not the 82C54 one.
*5.)clock() calls represent a rising clock edge followed by a falling
* 3.)I assumed that programming a counter removes a latched status.
* 4.)I implemented the 8254 description of mode 0, not the 82C54 one.
* 5.)clock() calls represent a rising clock edge followed by a falling
* clock edge.
*6.)What happens when we trigger mode 1 in the middle of a 2-part
* 6.)What happens when we trigger mode 1 in the middle of a 2-part
* write?
*/