diff --git a/bochs/iodev/pit82c54.cc b/bochs/iodev/pit82c54.cc
index ab8135c87..06e7974e3 100644
--- a/bochs/iodev/pit82c54.cc
+++ b/bochs/iodev/pit82c54.cc
@@ -1,8 +1,13 @@
 /*
- *Emulator of an Intel 8254/82C54 Programmable Interval Timer.
+ * Emulator of an Intel 8254/82C54 Programmable Interval Timer.
+ * Greg Alexander <yakovlev@usa.com>
  *
- *Things I am unclear on:
- *1.)What happens if both the status and count registers are latched,
+ * This code is not yet linked into Bochs, but has been included so
+ * that you can experiment with it.  (bbd)
+ *
+ * 
+ * Things I am unclear on (greg):
+ * 1.)What happens if both the status and count registers are latched,
  *  but the first of the two count registers has already been read?
  *  I.E.: 
  *   latch count 0 (16-bit)
@@ -10,13 +15,13 @@
  *   READ_BACK status of count 0
  *   Read count 0 - do you get MSByte or status?
  *  This will be flagged as an error.
- *2.)What happens when we latch the output in the middle of a 2-part
+ * 2.)What happens when we latch the output in the middle of a 2-part
  *  unlatched read?
- *3.)I assumed that programming a counter removes a latched status.
- *4.)I implemented the 8254 description of mode 0, not the 82C54 one.
- *5.)clock() calls represent a rising clock edge followed by a falling
+ * 3.)I assumed that programming a counter removes a latched status.
+ * 4.)I implemented the 8254 description of mode 0, not the 82C54 one.
+ * 5.)clock() calls represent a rising clock edge followed by a falling
  *  clock edge.
- *6.)What happens when we trigger mode 1 in the middle of a 2-part 
+ * 6.)What happens when we trigger mode 1 in the middle of a 2-part 
  *  write?
  */