mirror of https://github.com/bochs-emu/Bochs
Imlemented CR8 register for X86-64 mode
This commit is contained in:
Stanislav Shwartsman
parent
c7f205a6e9
commit
80ee150d83
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@ -149,6 +149,13 @@ Changes to next release:
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- patch.apic-zwane (APIC fixes) (Zwane Mwaikambo)
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- these S.F. bugs were closed
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#708847 CR8 access should not panic X86-64
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#1039499 Compile error pcipnic.cc (cygwin)
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#978024 compile against wxGTK-2.5.2 fails
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#639073 MacOSX: Networking not implemented
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#639074 MacOSX: Soundblaster not implemented
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#963264 Latest CVS --enable-pcidev fails to configue on YDL Linux
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#586282 Mac OS X, will not "make"
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#699532 CVS (as of 2003/03/07) cannot read disk images
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#639275 wrong more than 2GB size DVD-ROM
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#766020 info registers / dump_cpu get old eflags
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: apic.cc,v 1.32 2004-09-15 21:48:56 sshwarts Exp $
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// $Id: apic.cc,v 1.33 2004-10-13 20:58:15 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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#define NEED_CPU_REG_SHORTCUTS 1
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@ -729,8 +729,7 @@ void bx_local_apic_c::read_aligned (Bit32u addr, Bit32u *data, unsigned len)
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BX_INFO(("%s: read from APIC address %08x = %08x", cpu->name, addr, *data));
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}
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int
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bx_local_apic_c::highest_priority_int (Bit8u *array)
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int bx_local_apic_c::highest_priority_int (Bit8u *array)
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{
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for (int i=0; i<BX_LOCAL_APIC_MAX_INTS; i++)
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if (array[i]) return i;
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@ -897,6 +896,16 @@ Bit8u bx_local_apic_c::get_ppr ()
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return (Bit8u) proc_priority;
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}
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Bit8u bx_local_apic_c::get_tpr ()
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{
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return task_priority;
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}
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void bx_local_apic_c::set_tpr (Bit8u priority)
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{
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task_priority = priority;
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}
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Bit8u bx_local_apic_c::get_apr ()
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{
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return arb_id;
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@ -168,6 +168,8 @@ public:
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virtual Bit32u get_delivery_bitmask (Bit8u dest, Bit8u dest_mode);
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virtual bx_bool deliver (Bit8u destination, Bit8u dest_mode, Bit8u delivery_mode, Bit8u vector, Bit8u polarity, Bit8u trig_mode);
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Bit8u get_ppr ();
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Bit8u get_tpr ();
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void set_tpr (Bit8u tpr);
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Bit8u get_apr ();
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Bit8u get_apr_lowpri();
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bx_bool is_focus(Bit32u vector);
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: init.cc,v 1.53 2004-07-29 20:15:18 sshwarts Exp $
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// $Id: init.cc,v 1.54 2004-10-13 20:58:16 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -168,7 +168,7 @@ cpu_param_handler (bx_param_c *param, int set, Bit64s val)
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void BX_CPU_C::init(BX_MEM_C *addrspace)
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{
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BX_DEBUG(( "Init $Id: init.cc,v 1.53 2004-07-29 20:15:18 sshwarts Exp $"));
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BX_DEBUG(( "Init $Id: init.cc,v 1.54 2004-10-13 20:58:16 sshwarts Exp $"));
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// BX_CPU_C constructor
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BX_CPU_THIS_PTR set_INTR (0);
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#if BX_SUPPORT_APIC
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@ -508,8 +508,7 @@ BX_CPU_C::reset(unsigned source)
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/* instruction pointer */
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#if BX_CPU_LEVEL < 2
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BX_CPU_THIS_PTR prev_eip =
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EIP = 0x00000000;
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BX_CPU_THIS_PTR prev_eip = EIP = 0x00000000;
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#else /* from 286 up */
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BX_CPU_THIS_PTR prev_eip =
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#if BX_SUPPORT_X86_64
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@ -565,7 +564,6 @@ BX_CPU_C::reset(unsigned source)
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.avl = 0;
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#endif
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/* SS (Stack Segment) and descriptor cache */
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector.value = 0x0000;
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#if BX_CPU_LEVEL >= 2
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@ -593,7 +591,6 @@ BX_CPU_C::reset(unsigned source)
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.avl = 0;
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#endif
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/* DS (Data Segment) and descriptor cache */
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].selector.value = 0x0000;
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#if BX_CPU_LEVEL >= 2
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@ -621,7 +618,6 @@ BX_CPU_C::reset(unsigned source)
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.u.segment.avl = 0;
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#endif
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/* ES (Extra Segment) and descriptor cache */
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].selector.value = 0x0000;
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#if BX_CPU_LEVEL >= 2
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@ -649,7 +645,6 @@ BX_CPU_C::reset(unsigned source)
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.u.segment.avl = 0;
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#endif
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/* FS and descriptor cache */
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#if BX_CPU_LEVEL >= 3
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].selector.value = 0x0000;
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@ -675,7 +670,6 @@ BX_CPU_C::reset(unsigned source)
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].cache.u.segment.avl = 0;
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#endif
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/* GS and descriptor cache */
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#if BX_CPU_LEVEL >= 3
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].selector.value = 0x0000;
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@ -845,7 +839,6 @@ BX_CPU_C::reset(unsigned source)
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#endif
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BX_CPU_THIS_PTR EXT = 0;
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//BX_INTR = 0;
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#if BX_SUPPORT_PAGING
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#if BX_USE_TLB
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: proc_ctrl.cc,v 1.83 2004-10-03 21:52:10 sshwarts Exp $
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// $Id: proc_ctrl.cc,v 1.84 2004-10-13 20:58:16 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -685,17 +685,14 @@ void BX_CPU_C::MOV_CdRd(bxInstruction_c *i)
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// invalidate_prefetch_q(); // Already done.
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break;
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case 4: // CR4
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{
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#if BX_CPU_LEVEL == 3
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BX_PANIC(("MOV_CdRd: write to CR4 of 0x%08x on 386", val_32));
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UndefinedOpcode(i);
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#else
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// Protected mode: #GP(0) if attempt to write a 1 to
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// any reserved bit of CR4
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SetCR4(val_32);
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#endif
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}
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break;
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default:
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BX_PANIC(("MOV_CdRd: control register index out of range"));
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@ -712,7 +709,7 @@ void BX_CPU_C::MOV_RdCd(bxInstruction_c *i)
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#else
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Bit32u val_32;
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if (v8086_mode()) {
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if (v8086_mode()){
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BX_INFO(("MOV_RdCd: v8086 mode causes #GP(0)"));
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exception(BX_GP_EXCEPTION, 0, 0);
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}
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@ -772,7 +769,7 @@ void BX_CPU_C::MOV_RdCd(bxInstruction_c *i)
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default:
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BX_PANIC(("MOV_RdCd: control register index out of range"));
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val_32 = 0;
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}
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}
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BX_WRITE_32BIT_REGZ(i->rm(), val_32);
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#endif
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}
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@ -783,7 +780,8 @@ void BX_CPU_C::MOV_CqRq(bxInstruction_c *i)
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// mov general register data to control register
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Bit64u val_64;
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if (v8086_mode()) {
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if (v8086_mode())
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{
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BX_INFO(("MOV_CqRq: v8086 mode causes #GP(0)"));
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exception(BX_GP_EXCEPTION, 0, 0);
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}
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@ -818,7 +816,6 @@ void BX_CPU_C::MOV_CqRq(bxInstruction_c *i)
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// (unsigned) EIP));
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SetCR0(val_64);
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break;
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case 1: /* CR1 */
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BX_PANIC(("MOV_CqRq: CR1 not implemented yet"));
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break;
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@ -847,7 +844,16 @@ void BX_CPU_C::MOV_CqRq(bxInstruction_c *i)
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// returns not-supported for all of these features.
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SetCR4(val_64);
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break;
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#if BX_SUPPORT_APIC
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case 7: // CR8
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// CR8 is aliased to APIC->TASK PRIORITY register
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// APIC.TPR[7:4] = CR8[3:0]
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// APIC.TPR[3:0] = 0
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// Reads of CR8 return zero extended APIC.TPR[7:4]
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// Write to CR8 update APIC.TPR[7:4]
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BX_CPU_THIS_PTR local_apic.set_tpr((val_64 & 0xF) << 0x4);
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break;
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#endif
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default:
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BX_PANIC(("MOV_CqRq: control register index out of range"));
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break;
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@ -910,16 +916,25 @@ void BX_CPU_C::MOV_RqCq(bxInstruction_c *i)
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BX_INFO(("MOV_RqCq: read of CR4"));
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val_64 = BX_CPU_THIS_PTR cr4.getRegister();
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break;
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#if BX_SUPPORT_APIC
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case 7: // CR8
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// CR8 is aliased to APIC->TASK PRIORITY register
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// APIC.TPR[7:4] = CR8[3:0]
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// APIC.TPR[3:0] = 0
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// Reads of CR8 return zero extended APIC.TPR[7:4]
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// Write to CR8 update APIC.TPR[7:4]
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val_64 = (BX_CPU_THIS_PTR local_apic.get_tpr() & 0xF) >> 4;
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break;
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#endif
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default:
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BX_PANIC(("MOV_RqCq: control register index out of range"));
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val_64 = 0;
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}
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}
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BX_WRITE_64BIT_REG(i->rm(), val_64);
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}
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#endif // #if BX_SUPPORT_X86_64
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void BX_CPU_C::MOV_TdRd(bxInstruction_c *i)
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{
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#if BX_CPU_LEVEL <= 4
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