diff --git a/bochs/CHANGES b/bochs/CHANGES
index fd0317d1c..ef06a9a72 100644
--- a/bochs/CHANGES
+++ b/bochs/CHANGES
@@ -149,6 +149,13 @@ Changes to next release:
   - patch.apic-zwane (APIC fixes) (Zwane Mwaikambo)
 
 - these S.F. bugs were closed
+  #708847 CR8 access should not panic X86-64
+ #1039499 Compile error pcipnic.cc (cygwin)
+  #978024 compile against wxGTK-2.5.2 fails
+  #639073 MacOSX: Networking not implemented
+  #639074 MacOSX: Soundblaster not implemented
+  #963264 Latest CVS --enable-pcidev fails to configue on YDL Linux
+  #586282 Mac OS X, will not "make"
   #699532 CVS (as of 2003/03/07) cannot read disk images
   #639275 wrong more than 2GB size DVD-ROM
   #766020 info registers / dump_cpu get old eflags
diff --git a/bochs/cpu/apic.cc b/bochs/cpu/apic.cc
index 3a2b9ac48..0cc19bd2d 100644
--- a/bochs/cpu/apic.cc
+++ b/bochs/cpu/apic.cc
@@ -1,5 +1,5 @@
 /////////////////////////////////////////////////////////////////////////
-// $Id: apic.cc,v 1.32 2004-09-15 21:48:56 sshwarts Exp $
+// $Id: apic.cc,v 1.33 2004-10-13 20:58:15 sshwarts Exp $
 /////////////////////////////////////////////////////////////////////////
 
 #define NEED_CPU_REG_SHORTCUTS 1
@@ -729,8 +729,7 @@ void bx_local_apic_c::read_aligned (Bit32u addr, Bit32u *data, unsigned len)
     BX_INFO(("%s: read from APIC address %08x = %08x", cpu->name, addr, *data));
 }
 
-int 
-bx_local_apic_c::highest_priority_int (Bit8u *array)
+int bx_local_apic_c::highest_priority_int (Bit8u *array)
 {
   for (int i=0; i<BX_LOCAL_APIC_MAX_INTS; i++)
     if (array[i]) return i;
@@ -897,6 +896,16 @@ Bit8u bx_local_apic_c::get_ppr ()
   return (Bit8u) proc_priority;
 }
 
+Bit8u bx_local_apic_c::get_tpr ()
+{
+  return task_priority;
+}
+
+void  bx_local_apic_c::set_tpr (Bit8u priority)
+{
+  task_priority = priority;
+}
+
 Bit8u bx_local_apic_c::get_apr ()
 {
   return arb_id;
diff --git a/bochs/cpu/apic.h b/bochs/cpu/apic.h
index c6a7a7fe1..73aa99782 100644
--- a/bochs/cpu/apic.h
+++ b/bochs/cpu/apic.h
@@ -168,6 +168,8 @@ public:
   virtual Bit32u get_delivery_bitmask (Bit8u dest, Bit8u dest_mode);
   virtual bx_bool deliver (Bit8u destination, Bit8u dest_mode, Bit8u delivery_mode, Bit8u vector, Bit8u polarity, Bit8u trig_mode);
   Bit8u get_ppr ();
+  Bit8u get_tpr ();
+  void  set_tpr (Bit8u tpr);
   Bit8u get_apr ();
   Bit8u get_apr_lowpri();
   bx_bool is_focus(Bit32u vector);
diff --git a/bochs/cpu/init.cc b/bochs/cpu/init.cc
index 805a1680c..a1d042a61 100644
--- a/bochs/cpu/init.cc
+++ b/bochs/cpu/init.cc
@@ -1,5 +1,5 @@
 /////////////////////////////////////////////////////////////////////////
-// $Id: init.cc,v 1.53 2004-07-29 20:15:18 sshwarts Exp $
+// $Id: init.cc,v 1.54 2004-10-13 20:58:16 sshwarts Exp $
 /////////////////////////////////////////////////////////////////////////
 //
 //  Copyright (C) 2001  MandrakeSoft S.A.
@@ -168,7 +168,7 @@ cpu_param_handler (bx_param_c *param, int set, Bit64s val)
 
 void BX_CPU_C::init(BX_MEM_C *addrspace)
 {
-  BX_DEBUG(( "Init $Id: init.cc,v 1.53 2004-07-29 20:15:18 sshwarts Exp $"));
+  BX_DEBUG(( "Init $Id: init.cc,v 1.54 2004-10-13 20:58:16 sshwarts Exp $"));
   // BX_CPU_C constructor
   BX_CPU_THIS_PTR set_INTR (0);
 #if BX_SUPPORT_APIC
@@ -508,8 +508,7 @@ BX_CPU_C::reset(unsigned source)
 
   /* instruction pointer */
 #if BX_CPU_LEVEL < 2
-  BX_CPU_THIS_PTR prev_eip =
-  EIP = 0x00000000;
+  BX_CPU_THIS_PTR prev_eip = EIP = 0x00000000;
 #else /* from 286 up */
   BX_CPU_THIS_PTR prev_eip =
 #if BX_SUPPORT_X86_64
@@ -565,7 +564,6 @@ BX_CPU_C::reset(unsigned source)
   BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.avl = 0;
 #endif
 
-
   /* SS (Stack Segment) and descriptor cache */
   BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector.value =     0x0000;
 #if BX_CPU_LEVEL >= 2
@@ -593,7 +591,6 @@ BX_CPU_C::reset(unsigned source)
   BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.avl = 0;
 #endif
 
-
   /* DS (Data Segment) and descriptor cache */
   BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].selector.value =     0x0000;
 #if BX_CPU_LEVEL >= 2
@@ -621,7 +618,6 @@ BX_CPU_C::reset(unsigned source)
   BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.u.segment.avl = 0;
 #endif
 
-
   /* ES (Extra Segment) and descriptor cache */
   BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].selector.value =     0x0000;
 #if BX_CPU_LEVEL >= 2
@@ -649,7 +645,6 @@ BX_CPU_C::reset(unsigned source)
   BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.u.segment.avl = 0;
 #endif
 
-
   /* FS and descriptor cache */
 #if BX_CPU_LEVEL >= 3
   BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].selector.value =     0x0000;
@@ -675,7 +670,6 @@ BX_CPU_C::reset(unsigned source)
   BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].cache.u.segment.avl = 0;
 #endif
 
-
   /* GS and descriptor cache */
 #if BX_CPU_LEVEL >= 3
   BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].selector.value =     0x0000;
@@ -845,7 +839,6 @@ BX_CPU_C::reset(unsigned source)
 #endif
 
   BX_CPU_THIS_PTR EXT = 0;
-  //BX_INTR = 0;
 
 #if BX_SUPPORT_PAGING
 #if BX_USE_TLB
diff --git a/bochs/cpu/proc_ctrl.cc b/bochs/cpu/proc_ctrl.cc
index ca4405f33..42412b825 100644
--- a/bochs/cpu/proc_ctrl.cc
+++ b/bochs/cpu/proc_ctrl.cc
@@ -1,5 +1,5 @@
 /////////////////////////////////////////////////////////////////////////
-// $Id: proc_ctrl.cc,v 1.83 2004-10-03 21:52:10 sshwarts Exp $
+// $Id: proc_ctrl.cc,v 1.84 2004-10-13 20:58:16 sshwarts Exp $
 /////////////////////////////////////////////////////////////////////////
 //
 //  Copyright (C) 2001  MandrakeSoft S.A.
@@ -685,17 +685,14 @@ void BX_CPU_C::MOV_CdRd(bxInstruction_c *i)
       // invalidate_prefetch_q(); // Already done.
       break;
     case 4: // CR4
-      {
 #if BX_CPU_LEVEL == 3
       BX_PANIC(("MOV_CdRd: write to CR4 of 0x%08x on 386", val_32));
       UndefinedOpcode(i);
 #else
       //  Protected mode: #GP(0) if attempt to write a 1 to
       //  any reserved bit of CR4
-
       SetCR4(val_32);
 #endif
-      }
       break;
     default:
       BX_PANIC(("MOV_CdRd: control register index out of range"));
@@ -712,7 +709,7 @@ void BX_CPU_C::MOV_RdCd(bxInstruction_c *i)
 #else
   Bit32u val_32;
 
-  if (v8086_mode()) {
+  if (v8086_mode()){
     BX_INFO(("MOV_RdCd: v8086 mode causes #GP(0)"));
     exception(BX_GP_EXCEPTION, 0, 0);
   }
@@ -772,7 +769,7 @@ void BX_CPU_C::MOV_RdCd(bxInstruction_c *i)
     default:
       BX_PANIC(("MOV_RdCd: control register index out of range"));
       val_32 = 0;
-    }
+  }
   BX_WRITE_32BIT_REGZ(i->rm(), val_32);
 #endif
 }
@@ -783,7 +780,8 @@ void BX_CPU_C::MOV_CqRq(bxInstruction_c *i)
   // mov general register data to control register
   Bit64u val_64;
 
-  if (v8086_mode()) {
+  if (v8086_mode())
+  {
     BX_INFO(("MOV_CqRq: v8086 mode causes #GP(0)"));
     exception(BX_GP_EXCEPTION, 0, 0);
   }
@@ -818,7 +816,6 @@ void BX_CPU_C::MOV_CqRq(bxInstruction_c *i)
       //   (unsigned) EIP));
       SetCR0(val_64);
       break;
-
     case 1: /* CR1 */
       BX_PANIC(("MOV_CqRq: CR1 not implemented yet"));
       break;
@@ -847,7 +844,16 @@ void BX_CPU_C::MOV_CqRq(bxInstruction_c *i)
       // returns not-supported for all of these features.
       SetCR4(val_64);
       break;
-
+#if BX_SUPPORT_APIC
+    case 7: // CR8
+      // CR8 is aliased to APIC->TASK PRIORITY register
+      //   APIC.TPR[7:4] = CR8[3:0]
+      //   APIC.TPR[3:0] = 0
+      // Reads of CR8 return zero extended APIC.TPR[7:4]
+      // Write to CR8 update APIC.TPR[7:4]
+      BX_CPU_THIS_PTR local_apic.set_tpr((val_64 & 0xF) << 0x4);
+      break;
+#endif
     default:
       BX_PANIC(("MOV_CqRq: control register index out of range"));
       break;
@@ -910,16 +916,25 @@ void BX_CPU_C::MOV_RqCq(bxInstruction_c *i)
       BX_INFO(("MOV_RqCq: read of CR4"));
       val_64 = BX_CPU_THIS_PTR cr4.getRegister();
       break;
+#if BX_SUPPORT_APIC
+    case 7: // CR8
+      // CR8 is aliased to APIC->TASK PRIORITY register
+      //   APIC.TPR[7:4] = CR8[3:0]
+      //   APIC.TPR[3:0] = 0
+      // Reads of CR8 return zero extended APIC.TPR[7:4]
+      // Write to CR8 update APIC.TPR[7:4]
+      val_64 = (BX_CPU_THIS_PTR local_apic.get_tpr() & 0xF) >> 4;
+      break;
+#endif
     default:
       BX_PANIC(("MOV_RqCq: control register index out of range"));
       val_64 = 0;
-    }
+  }
 
   BX_WRITE_64BIT_REG(i->rm(), val_64);
 }
 #endif  // #if BX_SUPPORT_X86_64
 
-
 void BX_CPU_C::MOV_TdRd(bxInstruction_c *i)
 {
 #if BX_CPU_LEVEL <= 4