Separate fetch/decode instruction block to stand-alone method.
The method could be reused when building instruction trace for DT
This commit is contained in:
Stanislav Shwartsman
parent
0150904e9d
commit
79306b851c
176
bochs/cpu/cpu.cc
176
bochs/cpu/cpu.cc
@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: cpu.cc,v 1.131 2006-02-14 20:03:14 sshwarts Exp $
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// $Id: cpu.cc,v 1.132 2006-02-23 18:23:31 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -122,9 +122,7 @@ static unsigned iCacheMisses=0;
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void BX_CPU_C::cpu_loop(Bit32s max_instr_count)
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{
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unsigned ret;
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bxInstruction_c iStorage BX_CPP_AlignN(32);
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bxInstruction_c *i = &iStorage;
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#if BX_DEBUGGER
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BX_CPU_THIS_PTR break_point = 0;
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@ -205,86 +203,8 @@ void BX_CPU_C::cpu_loop(Bit32s max_instr_count)
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eipBiased = RIP + BX_CPU_THIS_PTR eipPageBias;
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}
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#if BX_SUPPORT_ICACHE
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Bit32u pAddr = BX_CPU_THIS_PTR pAddrA20Page + eipBiased;
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unsigned iCacheHash = BX_CPU_THIS_PTR iCache.hash(pAddr);
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bxICacheEntry_c *cache_entry = &(BX_CPU_THIS_PTR iCache.entry[iCacheHash]);
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i = &(cache_entry->i);
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Bit32u pageWriteStamp = *(BX_CPU_THIS_PTR currPageWriteStampPtr);
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#if BX_SUPPORT_ICACHE
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InstrICache_Increment(iCacheLookups);
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InstrICache_Stats();
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#endif
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if ((cache_entry->pAddr == pAddr) &&
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(cache_entry->writeStamp == pageWriteStamp))
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{
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// iCache hit. Instruction is already decoded and stored in the
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// instruction cache.
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#if BX_INSTRUMENTATION
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// An instruction was found in the iCache.
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BX_INSTR_OPCODE(BX_CPU_ID, BX_CPU_THIS_PTR eipFetchPtr + eipBiased,
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i->ilen(), BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.d_b, Is64BitMode());
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#endif
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}
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else
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#endif
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{
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// iCache miss. No validated instruction with matching fetch parameters
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// is in the iCache. Or we're not compiling iCache support in, in which
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// case we always have an iCache miss. :^)
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bx_address remainingInPage;
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remainingInPage = (BX_CPU_THIS_PTR eipPageWindowSize - eipBiased);
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unsigned maxFetch = 15;
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if (remainingInPage < 15) maxFetch = remainingInPage;
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Bit8u *fetchPtr = BX_CPU_THIS_PTR eipFetchPtr + eipBiased;
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#if BX_SUPPORT_ICACHE
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// The entry will be marked valid if fetchdecode will succeed
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cache_entry->writeStamp = ICacheWriteStampInvalid;
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InstrICache_Increment(iCacheMisses);
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#endif
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#if BX_SUPPORT_X86_64
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if (BX_CPU_THIS_PTR cpu_mode == BX_MODE_LONG_64)
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ret = fetchDecode64(fetchPtr, i, maxFetch);
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else
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#endif
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ret = fetchDecode(fetchPtr, i, maxFetch);
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if (ret==0) {
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#if BX_SUPPORT_ICACHE
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i = &iStorage; // Leave entry invalid
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#endif
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boundaryFetch(fetchPtr, remainingInPage, i);
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}
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else
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{
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#if BX_SUPPORT_ICACHE
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// In the case where the page is marked ICacheWriteStampInvalid, all
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// counter bits will be high, being eqivalent to ICacheWriteStampMax.
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// In the case where the page is marked as possibly having associated
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// iCache entries, we need to leave the counter as-is, unless we're
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// willing to dump all iCache entries which can hash to this page.
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// Therefore, in either case, we can keep the counter as-is and
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// replace the fetch mode bits.
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Bit32u fetchModeMask = BX_CPU_THIS_PTR iCache.fetchModeMask;
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pageWriteStamp &= ICacheWriteStampMask; // Clear out old fetch mode bits.
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pageWriteStamp |= fetchModeMask; // Add in new ones.
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pageWriteStampTable.setPageWriteStamp(pAddr, pageWriteStamp);
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cache_entry->pAddr = pAddr;
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cache_entry->writeStamp = pageWriteStamp;
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#endif
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#if BX_INSTRUMENTATION
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// An instruction was either fetched, or found in the iCache.
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BX_INSTR_OPCODE(BX_CPU_ID, fetchPtr, i->ilen(),
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.d_b, Is64BitMode());
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#endif
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}
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}
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// fetch and decode next instruction
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bxInstruction_c *i = fetchInstruction(&iStorage, eipBiased);
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bx_address next_RIP = RIP + i->ilen();
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if (! Is64BitMode()) {
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@ -497,6 +417,93 @@ debugger_check:
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} // while (1)
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}
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bxInstruction_c* BX_CPU_C::fetchInstruction(bxInstruction_c *iStorage, bx_address eipBiased)
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{
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unsigned ret;
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bxInstruction_c *i = iStorage;
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#if BX_SUPPORT_ICACHE
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bx_phy_address pAddr = BX_CPU_THIS_PTR pAddrA20Page + eipBiased;
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unsigned iCacheHash = BX_CPU_THIS_PTR iCache.hash(pAddr);
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bxICacheEntry_c *cache_entry = &(BX_CPU_THIS_PTR iCache.entry[iCacheHash]);
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i = &(cache_entry->i);
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Bit32u pageWriteStamp = *(BX_CPU_THIS_PTR currPageWriteStampPtr);
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InstrICache_Increment(iCacheLookups);
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InstrICache_Stats();
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if ((cache_entry->pAddr == pAddr) &&
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(cache_entry->writeStamp == pageWriteStamp))
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{
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// iCache hit. Instruction is already decoded and stored in the
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// instruction cache.
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#if BX_INSTRUMENTATION
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// An instruction was found in the iCache.
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BX_INSTR_OPCODE(BX_CPU_ID, BX_CPU_THIS_PTR eipFetchPtr + eipBiased,
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i->ilen(), BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.d_b, Is64BitMode());
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#endif
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}
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else
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#endif
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{
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// iCache miss. No validated instruction with matching fetch parameters
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// is in the iCache. Or we're not compiling iCache support in, in which
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// case we always have an iCache miss. :^)
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bx_address remainingInPage;
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remainingInPage = (BX_CPU_THIS_PTR eipPageWindowSize - eipBiased);
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unsigned maxFetch = 15;
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if (remainingInPage < 15) maxFetch = remainingInPage;
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Bit8u *fetchPtr = BX_CPU_THIS_PTR eipFetchPtr + eipBiased;
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#if BX_SUPPORT_ICACHE
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// The entry will be marked valid if fetchdecode will succeed
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cache_entry->writeStamp = ICacheWriteStampInvalid;
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InstrICache_Increment(iCacheMisses);
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#endif
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#if BX_SUPPORT_X86_64
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if (BX_CPU_THIS_PTR cpu_mode == BX_MODE_LONG_64)
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ret = fetchDecode64(fetchPtr, i, maxFetch);
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else
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#endif
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ret = fetchDecode(fetchPtr, i, maxFetch);
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if (ret==0) {
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#if BX_SUPPORT_ICACHE
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i = iStorage; // Leave entry invalid
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#endif
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boundaryFetch(fetchPtr, remainingInPage, i);
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}
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else
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{
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#if BX_SUPPORT_ICACHE
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// In the case where the page is marked ICacheWriteStampInvalid, all
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// counter bits will be high, being eqivalent to ICacheWriteStampMax.
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// In the case where the page is marked as possibly having associated
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// iCache entries, we need to leave the counter as-is, unless we're
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// willing to dump all iCache entries which can hash to this page.
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// Therefore, in either case, we can keep the counter as-is and
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// replace the fetch mode bits.
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Bit32u fetchModeMask = BX_CPU_THIS_PTR iCache.fetchModeMask;
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pageWriteStamp &= ICacheWriteStampMask; // Clear out old fetch mode bits.
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pageWriteStamp |= fetchModeMask; // Add in new ones.
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pageWriteStampTable.setPageWriteStamp(pAddr, pageWriteStamp);
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cache_entry->pAddr = pAddr;
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cache_entry->writeStamp = pageWriteStamp;
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#endif
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#if BX_INSTRUMENTATION
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// An instruction was either fetched, or found in the iCache.
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BX_INSTR_OPCODE(BX_CPU_ID, fetchPtr, i->ilen(),
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.d_b, Is64BitMode());
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#endif
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}
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}
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return i;
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}
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unsigned BX_CPU_C::handleAsyncEvent(void)
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{
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//
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@ -727,8 +734,9 @@ unsigned BX_CPU_C::handleAsyncEvent(void)
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void BX_CPU_C::prefetch(void)
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{
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bx_phy_address pAddr;
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// prefetch QSIZE byte quantity aligned on corresponding boundary
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Bit32u pAddr;
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bx_address laddrPageOffset0, eipPageOffset0;
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bx_address temp_rip = RIP;
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: cpu.h,v 1.261 2006-02-17 13:34:30 sshwarts Exp $
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// $Id: cpu.h,v 1.262 2006-02-23 18:23:31 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -1166,7 +1166,7 @@ public: // for now...
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bx_address eipPageBias;
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bx_address eipPageWindowSize;
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Bit8u *eipFetchPtr;
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Bit32u pAddrA20Page; // Guest physical address of current instruction
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bx_phy_address pAddrA20Page; // Guest physical address of current instruction
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// page with A20() already applied.
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#if BX_SUPPORT_ICACHE
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const Bit32u *currPageWriteStampPtr;
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@ -2469,6 +2469,7 @@ public: // for now...
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#if BX_SUPPORT_X86_64
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BX_SMF unsigned fetchDecode64(Bit8u *, bxInstruction_c *, unsigned);
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#endif
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BX_SMF bxInstruction_c* fetchInstruction(bxInstruction_c *, bx_address);
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BX_SMF void UndefinedOpcode(bxInstruction_c *);
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BX_SMF void BxError(bxInstruction_c *i);
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: main.cc,v 1.315 2006-02-22 19:18:28 vruppert Exp $
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// $Id: main.cc,v 1.316 2006-02-23 18:23:30 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2002 MandrakeSoft S.A.
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@ -868,7 +868,10 @@ int bx_init_hardware()
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BX_INFO((" fpu support: %s",BX_SUPPORT_FPU?"yes":"no"));
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BX_INFO((" paging support: %s, tlb enabled: %s",BX_SUPPORT_PAGING?"yes":"no",BX_USE_TLB?"yes":"no"));
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BX_INFO((" mmx support: %s",BX_SUPPORT_MMX?"yes":"no"));
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BX_INFO((" sse support: %s",BX_SUPPORT_SSE==2?"2":BX_SUPPORT_SSE==1?"1":"no"));
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if (BX_SUPPORT_SSE == 0)
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BX_INFO((" sse support: no"));
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else
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BX_INFO((" sse support: %d",BX_SUPPORT_SSE));
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BX_INFO((" v8086 mode support: %s",BX_SUPPORT_V8086_MODE?"yes":"no"));
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BX_INFO((" VME support: %s",BX_SUPPORT_VME?"yes":"no"));
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BX_INFO((" 3dnow! support: %s",BX_SUPPORT_3DNOW?"yes":"no"));
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