cleanups and optimizations
This commit is contained in:
parent
5e1229b3b1
commit
6d71bdb785
@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: apic.cc,v 1.130 2009-10-14 20:45:29 sshwarts Exp $
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// $Id: apic.cc,v 1.131 2009-11-02 15:00:47 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (c) 2002-2009 Zwane Mwaikambo, Stanislav Shwartsman
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@ -991,6 +991,7 @@ void bx_local_apic_c::register_state(bx_param_c *parent)
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BXRS_HEX_PARAM_SIMPLE(lapic, timer_current);
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BXRS_HEX_PARAM_SIMPLE(lapic, timer_divconf);
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BXRS_DEC_PARAM_SIMPLE(lapic, timer_divide_factor);
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BXRS_DEC_PARAM_SIMPLE(lapic, timer_handle);
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BXRS_PARAM_BOOL(lapic, timer_active, timer_active);
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BXRS_HEX_PARAM_SIMPLE(lapic, ticksInitial);
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BXRS_PARAM_BOOL(lapic, INTR, INTR);
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: bit.cc,v 1.63 2009-03-22 21:23:12 sshwarts Exp $
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// $Id: bit.cc,v 1.64 2009-11-02 15:00:47 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -437,7 +437,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVBE_EqGq(bxInstruction_c *i)
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}
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else {
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bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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write_virtual_qword(i->seg(), eaddr, val64);
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write_virtual_qword_64(i->seg(), eaddr, val64);
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}
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#else
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BX_INFO(("MOVBE_EqGq: required MOVBE support, use --enable-movbe option"));
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: crregs.h,v 1.19 2009-10-14 20:45:29 sshwarts Exp $
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// $Id: crregs.h,v 1.20 2009-11-02 15:00:47 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (c) 2007-2009 Stanislav Shwartsman
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@ -105,12 +105,6 @@ struct bx_cr4_t {
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extern bx_address get_cr4_allow_mask(void);
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#if BX_CPU_LEVEL >= 5
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#define BX_CR4_VME_ENABLED (BX_CPU_THIS_PTR cr4.get_VME())
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#else
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#define BX_CR4_VME_ENABLED (0)
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#endif
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#if BX_SUPPORT_X86_64
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struct bx_efer_t {
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: flag_ctrl.cc,v 1.46 2009-08-10 15:44:50 sshwarts Exp $
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// $Id: flag_ctrl.cc,v 1.47 2009-11-02 15:00:47 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2002 MandrakeSoft S.A.
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@ -86,7 +86,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CLI(bxInstruction_c *i)
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{
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if (IOPL != 3) {
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#if BX_CPU_LEVEL >= 5
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if (BX_CR4_VME_ENABLED) {
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if (BX_CPU_THIS_PTR cr4.get_VME()) {
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BX_CPU_THIS_PTR clear_VIF();
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return;
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}
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@ -129,7 +129,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::STI(bxInstruction_c *i)
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{
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if (IOPL != 3) {
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#if BX_CPU_LEVEL >= 5
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if (BX_CR4_VME_ENABLED && BX_CPU_THIS_PTR get_VIP() == 0)
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if (BX_CPU_THIS_PTR cr4.get_VME() && BX_CPU_THIS_PTR get_VIP() == 0)
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{
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BX_CPU_THIS_PTR assert_VIF();
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return;
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@ -167,19 +167,22 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PUSHF_Fw(bxInstruction_c *i)
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Bit16u flags = (Bit16u) read_eflags();
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if (v8086_mode()) {
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if ((BX_CPU_THIS_PTR get_IOPL() < 3) && (BX_CR4_VME_ENABLED == 0)) {
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BX_DEBUG(("PUSHFW: #GP(0) in v8086 (no VME) mode"));
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exception(BX_GP_EXCEPTION, 0, 0);
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}
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if (BX_CPU_THIS_PTR get_IOPL() < 3) {
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#if BX_CPU_LEVEL >= 5
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if (BX_CR4_VME_ENABLED && BX_CPU_THIS_PTR get_IOPL() < 3) {
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flags |= EFlagsIOPLMask;
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if (BX_CPU_THIS_PTR get_VIF())
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flags |= EFlagsIFMask;
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if (BX_CPU_THIS_PTR cr4.get_VME()) {
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flags |= EFlagsIOPLMask;
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if (BX_CPU_THIS_PTR get_VIF())
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flags |= EFlagsIFMask;
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else
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flags &= ~EFlagsIFMask;
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}
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else
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flags &= ~EFlagsIFMask;
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}
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#endif
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{
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BX_DEBUG(("PUSHFW: #GP(0) in v8086 (no VME) mode"));
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exception(BX_GP_EXCEPTION, 0, 0);
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}
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}
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}
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push_16(flags);
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@ -189,10 +192,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::POPF_Fw(bxInstruction_c *i)
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{
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// Build a mask of the following bits:
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// x,NT,IOPL,OF,DF,IF,TF,SF,ZF,x,AF,x,PF,x,CF
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Bit32u changeMask = EFlagsOSZAPCMask | EFlagsTFMask | EFlagsDFMask;
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#if BX_CPU_LEVEL >= 3
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changeMask |= EFlagsNTMask; // NT could be modified
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#endif
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Bit32u changeMask = EFlagsOSZAPCMask | EFlagsTFMask | EFlagsDFMask | EFlagsNTMask;
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RSP_SPECULATIVE;
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@ -205,31 +205,31 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::POPF_Fw(bxInstruction_c *i)
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changeMask |= EFlagsIFMask;
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}
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else if (v8086_mode()) {
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if ((BX_CPU_THIS_PTR get_IOPL() < 3) && (BX_CR4_VME_ENABLED == 0)) {
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if (BX_CPU_THIS_PTR get_IOPL() < 3) {
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#if BX_CPU_LEVEL >= 5
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if (BX_CPU_THIS_PTR cr4.get_VME()) {
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if (((flags16 & EFlagsIFMask) && BX_CPU_THIS_PTR get_VIP()) ||
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(flags16 & EFlagsTFMask))
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{
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BX_ERROR(("POPFW: #GP(0) in VME mode"));
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exception(BX_GP_EXCEPTION, 0, 0);
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}
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// IF, IOPL unchanged, EFLAGS.VIF = TMP_FLAGS.IF
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changeMask |= EFlagsVIFMask;
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Bit32u flags32 = (Bit32u) flags16;
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if (BX_CPU_THIS_PTR get_IF()) flags32 |= EFlagsVIFMask;
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writeEFlags(flags32, changeMask);
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RSP_COMMIT;
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return;
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}
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#endif
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BX_DEBUG(("POPFW: #GP(0) in v8086 (no VME) mode"));
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exception(BX_GP_EXCEPTION, 0, 0);
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}
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#if BX_CPU_LEVEL >= 5
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if (BX_CR4_VME_ENABLED && BX_CPU_THIS_PTR get_IOPL() < 3) {
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if (((flags16 & EFlagsIFMask) && BX_CPU_THIS_PTR get_VIP()) ||
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(flags16 & EFlagsTFMask))
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{
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BX_ERROR(("POPFW: #GP(0) in VME mode"));
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exception(BX_GP_EXCEPTION, 0, 0);
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}
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// IF, IOPL unchanged, EFLAGS.VIF = TMP_FLAGS.IF
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changeMask |= EFlagsVIFMask;
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Bit32u flags32 = (Bit32u) flags16;
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if (BX_CPU_THIS_PTR get_IF()) flags32 |= EFlagsVIFMask;
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writeEFlags(flags32, changeMask);
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RSP_COMMIT;
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return;
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}
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#endif
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changeMask |= EFlagsIFMask;
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}
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else {
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// All non-reserved flags can be modified
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/////////////////////////////////////////////////////////////////////////
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// $Id: soft_int.cc,v 1.54 2009-08-10 15:44:50 sshwarts Exp $
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// $Id: soft_int.cc,v 1.55 2009-11-02 15:00:47 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -37,13 +37,12 @@
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::BOUND_GwMa(bxInstruction_c *i)
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{
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Bit16s bound_min, bound_max;
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Bit16s op1_16 = BX_READ_16BIT_REG(i->nnn());
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bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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Bit32u eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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bound_min = (Bit16s) read_virtual_word(i->seg(), eaddr);
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bound_max = (Bit16s) read_virtual_word(i->seg(), eaddr+2);
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Bit16s bound_min = (Bit16s) read_virtual_word_32(i->seg(), eaddr);
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Bit16s bound_max = (Bit16s) read_virtual_word_32(i->seg(), eaddr+2);
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if (op1_16 < bound_min || op1_16 > bound_max) {
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BX_INFO(("BOUND_GdMa: fails bounds test"));
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@ -53,13 +52,12 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::BOUND_GwMa(bxInstruction_c *i)
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::BOUND_GdMa(bxInstruction_c *i)
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{
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Bit32s bound_min, bound_max;
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Bit32s op1_32 = BX_READ_32BIT_REG(i->nnn());
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bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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Bit32u eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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bound_min = (Bit32s) read_virtual_dword(i->seg(), eaddr);
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bound_max = (Bit32s) read_virtual_dword(i->seg(), eaddr+4);
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Bit32s bound_min = (Bit32s) read_virtual_dword_32(i->seg(), eaddr);
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Bit32s bound_max = (Bit32s) read_virtual_dword_32(i->seg(), eaddr+4);
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if (op1_32 < bound_min || op1_32 > bound_max) {
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BX_INFO(("BOUND_GdMa: fails bounds test"));
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/////////////////////////////////////////////////////////////////////////
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// $Id: stack32.cc,v 1.62 2009-08-06 14:50:38 sshwarts Exp $
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// $Id: stack32.cc,v 1.63 2009-11-02 15:00:47 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -44,9 +44,9 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::POP_EdM(bxInstruction_c *i)
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// Note: there is one little weirdism here. It is possible to use
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// ESP in the modrm addressing. If used, the value of ESP after the
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// pop is used to calculate the address.
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bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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Bit32u eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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write_virtual_dword(i->seg(), eaddr, val32);
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write_virtual_dword_32(i->seg(), eaddr, val32);
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RSP_COMMIT;
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}
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/////////////////////////////////////////////////////////////////////////
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// $Id: vm8086.cc,v 1.56 2009-08-10 15:44:50 sshwarts Exp $
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// $Id: vm8086.cc,v 1.57 2009-11-02 15:00:47 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -98,6 +98,12 @@ void BX_CPU_C::stack_return_to_v86(Bit32u new_eip, Bit32u raw_cs_selector, Bit32
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init_v8086_mode();
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}
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#if BX_CPU_LEVEL >= 5
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#define BX_CR4_VME_ENABLED (BX_CPU_THIS_PTR cr4.get_VME())
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#else
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#define BX_CR4_VME_ENABLED (0)
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#endif
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void BX_CPU_C::iret16_stack_return_from_v86(bxInstruction_c *i)
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{
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if ((BX_CPU_THIS_PTR get_IOPL() < 3) && (BX_CR4_VME_ENABLED == 0)) {
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@ -113,7 +119,7 @@ void BX_CPU_C::iret16_stack_return_from_v86(bxInstruction_c *i)
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flags16 = pop_16();
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#if BX_CPU_LEVEL >= 5
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if (BX_CR4_VME_ENABLED && BX_CPU_THIS_PTR get_IOPL() < 3)
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if (BX_CPU_THIS_PTR cr4.get_VME() && BX_CPU_THIS_PTR get_IOPL() < 3)
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{
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if (((flags16 & EFlagsIFMask) && BX_CPU_THIS_PTR get_VIP()) ||
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(flags16 & EFlagsTFMask))
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@ -199,7 +205,7 @@ void BX_CPU_C::v86_redirect_interrupt(Bit32u vector)
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BX_CPU_THIS_PTR clear_TF();
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BX_CPU_THIS_PTR clear_RF();
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if (BX_CPU_THIS_PTR get_IOPL() == 3)
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BX_CPU_THIS_PTR clear_IF ();
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BX_CPU_THIS_PTR clear_IF();
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else
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BX_CPU_THIS_PTR clear_VIF();
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}
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@ -207,90 +213,27 @@ void BX_CPU_C::v86_redirect_interrupt(Bit32u vector)
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void BX_CPU_C::init_v8086_mode(void)
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{
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.valid = SegValidCache | SegAccessROK | SegAccessWOK;
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.p = 1;
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.dpl = 3;
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.segment = 1;
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.type = BX_DATA_READ_WRITE_ACCESSED;
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for(unsigned sreg = 0; sreg < 6; sreg++) {
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BX_CPU_THIS_PTR sregs[sreg].cache.valid = SegValidCache | SegAccessROK | SegAccessWOK;
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BX_CPU_THIS_PTR sregs[sreg].cache.p = 1;
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BX_CPU_THIS_PTR sregs[sreg].cache.dpl = 3;
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BX_CPU_THIS_PTR sregs[sreg].cache.segment = 1;
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BX_CPU_THIS_PTR sregs[sreg].cache.type = BX_DATA_READ_WRITE_ACCESSED;
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.base =
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value << 4;
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit_scaled = 0xffff;
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.g = 0;
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.d_b = 0;
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.avl = 0;
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.rpl = 3;
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BX_CPU_THIS_PTR sregs[sreg].cache.u.segment.base =
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BX_CPU_THIS_PTR sregs[sreg].selector.value << 4;
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BX_CPU_THIS_PTR sregs[sreg].cache.u.segment.limit_scaled = 0xffff;
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BX_CPU_THIS_PTR sregs[sreg].cache.u.segment.g = 0;
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BX_CPU_THIS_PTR sregs[sreg].cache.u.segment.d_b = 0;
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BX_CPU_THIS_PTR sregs[sreg].cache.u.segment.avl = 0;
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BX_CPU_THIS_PTR sregs[sreg].selector.rpl = 3;
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}
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handleCpuModeChange();
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#if BX_CPU_LEVEL >= 4 && BX_SUPPORT_ALIGNMENT_CHECK
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handleAlignmentCheck(); // CPL was modified
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#endif
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.valid = SegValidCache | SegAccessROK | SegAccessWOK;
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.p = 1;
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.dpl = 3;
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.segment = 1;
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.type = BX_DATA_READ_WRITE_ACCESSED;
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.base =
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector.value << 4;
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.limit_scaled = 0xffff;
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.g = 0;
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.d_b = 0;
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.avl = 0;
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector.rpl = 3;
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.valid = SegValidCache | SegAccessROK | SegAccessWOK;
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.p = 1;
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.dpl = 3;
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.segment = 1;
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.type = BX_DATA_READ_WRITE_ACCESSED;
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.u.segment.base =
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].selector.value << 4;
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.u.segment.limit_scaled = 0xffff;
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.u.segment.g = 0;
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.u.segment.d_b = 0;
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.u.segment.avl = 0;
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].selector.rpl = 3;
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.valid = SegValidCache | SegAccessROK | SegAccessWOK;
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.p = 1;
|
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.dpl = 3;
|
||||
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.segment = 1;
|
||||
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.type = BX_DATA_READ_WRITE_ACCESSED;
|
||||
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.u.segment.base =
|
||||
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].selector.value << 4;
|
||||
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.u.segment.limit_scaled = 0xffff;
|
||||
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.u.segment.g = 0;
|
||||
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.u.segment.d_b = 0;
|
||||
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.u.segment.avl = 0;
|
||||
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].selector.rpl = 3;
|
||||
|
||||
BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].cache.valid = SegValidCache | SegAccessROK | SegAccessWOK;
|
||||
BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].cache.p = 1;
|
||||
BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].cache.dpl = 3;
|
||||
BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].cache.segment = 1;
|
||||
BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].cache.type = BX_DATA_READ_WRITE_ACCESSED;
|
||||
BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].cache.u.segment.base =
|
||||
BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].selector.value << 4;
|
||||
BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].cache.u.segment.limit_scaled = 0xffff;
|
||||
BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].cache.u.segment.g = 0;
|
||||
BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].cache.u.segment.d_b = 0;
|
||||
BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].cache.u.segment.avl = 0;
|
||||
BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].selector.rpl = 3;
|
||||
|
||||
BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].cache.valid = SegValidCache | SegAccessROK | SegAccessWOK;
|
||||
BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].cache.p = 1;
|
||||
BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].cache.dpl = 3;
|
||||
BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].cache.segment = 1;
|
||||
BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].cache.type = BX_DATA_READ_WRITE_ACCESSED;
|
||||
BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].cache.u.segment.base =
|
||||
BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].selector.value << 4;
|
||||
BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].cache.u.segment.limit_scaled = 0xffff;
|
||||
BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].cache.u.segment.g = 0;
|
||||
BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].cache.u.segment.d_b = 0;
|
||||
BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].cache.u.segment.avl = 0;
|
||||
BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].selector.rpl = 3;
|
||||
}
|
||||
|
||||
#endif /* BX_CPU_LEVEL >= 3 */
|
||||
|
Loading…
Reference in New Issue
Block a user