Some changes in the Bochs BIOS.
- Disable i/o and memory access in PCI command register before probing and setting up base addresses and re-enable it when complete for selected device. - Legacy BIOS should not enable busmaster function in PCI init.
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@ -10214,7 +10214,7 @@ enable_iomem_space:
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call pcibios_init_sel_reg
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mov dx, #0x0cfc
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in al, dx
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or al, #0x07
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or al, #0x03
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out dx, al
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next_pci_dev:
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mov byte ptr[bp-8], #0x10
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@ -664,30 +664,17 @@ static uint32_t pci_config_readb(PCIDevice *d, uint32_t addr)
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static void pci_set_io_region_addr(PCIDevice *d, int region_num, uint32_t addr)
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{
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uint16_t cmd;
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uint32_t ofs, old_addr;
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uint32_t ofs;
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if ( region_num == PCI_ROM_SLOT ) {
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if (region_num == PCI_ROM_SLOT) {
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ofs = PCI_ROM_ADDRESS;
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addr |= PCI_ROM_ADDRESS_ENABLE;
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}else{
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} else {
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ofs = PCI_BASE_ADDRESS_0 + region_num * 4;
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}
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old_addr = pci_config_readl(d, ofs);
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pci_config_writel(d, ofs, addr);
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BX_INFO("region %d: 0x%08x\n", region_num, addr & ~0x01);
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/* enable memory mappings */
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cmd = pci_config_readw(d, PCI_COMMAND);
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if ( region_num == PCI_ROM_SLOT )
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cmd |= PCI_COMMAND_MEMORY;
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else if (old_addr & PCI_ADDRESS_SPACE_IO)
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cmd |= PCI_COMMAND_IO;
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else
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cmd |= PCI_COMMAND_MEMORY;
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pci_config_writew(d, PCI_COMMAND, cmd);
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}
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/* return the global irq number corresponding to a given device irq
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@ -938,7 +925,7 @@ static void pci_bios_init_pcirom(PCIDevice *d, uint32_t paddr)
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static void pci_bios_init_device(PCIDevice *d)
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{
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PCIDevice d1, *bridge = &d1;
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uint16_t class;
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uint16_t class, cmd;
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uint32_t *paddr;
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int headt, i, pin, pic_irq, vendor_id, device_id, is_i440bx = 0;
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@ -993,6 +980,10 @@ static void pci_bios_init_device(PCIDevice *d)
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default_map:
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if ((headt & 0x03) != 0)
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break;
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/* disable i/o and memory access */
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cmd = pci_config_readw(d, PCI_COMMAND);
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cmd &= 0xfffc;
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pci_config_writew(d, PCI_COMMAND, cmd);
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/* default memory mappings */
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for(i = 0; i < PCI_NUM_REGIONS; i++) {
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int ofs;
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@ -1035,6 +1026,10 @@ static void pci_bios_init_device(PCIDevice *d)
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}
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}
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}
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/* enable i/o and memory access */
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cmd = pci_config_readw(d, PCI_COMMAND);
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cmd |= (PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
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pci_config_writew(d, PCI_COMMAND, cmd);
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break;
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}
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