From 49f8624898867222e13c39f5fd408ef969c15839 Mon Sep 17 00:00:00 2001 From: Volker Ruppert Date: Tue, 13 Oct 2020 07:55:56 +0000 Subject: [PATCH] Some changes in the Bochs BIOS. - Disable i/o and memory access in PCI command register before probing and setting up base addresses and re-enable it when complete for selected device. - Legacy BIOS should not enable busmaster function in PCI init. --- bochs/bios/rombios.c | 2 +- bochs/bios/rombios32.c | 29 ++++++++++++----------------- 2 files changed, 13 insertions(+), 18 deletions(-) diff --git a/bochs/bios/rombios.c b/bochs/bios/rombios.c index 34e613bbc..18f005eb1 100644 --- a/bochs/bios/rombios.c +++ b/bochs/bios/rombios.c @@ -10214,7 +10214,7 @@ enable_iomem_space: call pcibios_init_sel_reg mov dx, #0x0cfc in al, dx - or al, #0x07 + or al, #0x03 out dx, al next_pci_dev: mov byte ptr[bp-8], #0x10 diff --git a/bochs/bios/rombios32.c b/bochs/bios/rombios32.c index f5174efaa..5f7c3a30f 100644 --- a/bochs/bios/rombios32.c +++ b/bochs/bios/rombios32.c @@ -664,30 +664,17 @@ static uint32_t pci_config_readb(PCIDevice *d, uint32_t addr) static void pci_set_io_region_addr(PCIDevice *d, int region_num, uint32_t addr) { - uint16_t cmd; - uint32_t ofs, old_addr; + uint32_t ofs; - if ( region_num == PCI_ROM_SLOT ) { + if (region_num == PCI_ROM_SLOT) { ofs = PCI_ROM_ADDRESS; addr |= PCI_ROM_ADDRESS_ENABLE; - }else{ + } else { ofs = PCI_BASE_ADDRESS_0 + region_num * 4; } - - old_addr = pci_config_readl(d, ofs); - pci_config_writel(d, ofs, addr); BX_INFO("region %d: 0x%08x\n", region_num, addr & ~0x01); - /* enable memory mappings */ - cmd = pci_config_readw(d, PCI_COMMAND); - if ( region_num == PCI_ROM_SLOT ) - cmd |= PCI_COMMAND_MEMORY; - else if (old_addr & PCI_ADDRESS_SPACE_IO) - cmd |= PCI_COMMAND_IO; - else - cmd |= PCI_COMMAND_MEMORY; - pci_config_writew(d, PCI_COMMAND, cmd); } /* return the global irq number corresponding to a given device irq @@ -938,7 +925,7 @@ static void pci_bios_init_pcirom(PCIDevice *d, uint32_t paddr) static void pci_bios_init_device(PCIDevice *d) { PCIDevice d1, *bridge = &d1; - uint16_t class; + uint16_t class, cmd; uint32_t *paddr; int headt, i, pin, pic_irq, vendor_id, device_id, is_i440bx = 0; @@ -993,6 +980,10 @@ static void pci_bios_init_device(PCIDevice *d) default_map: if ((headt & 0x03) != 0) break; + /* disable i/o and memory access */ + cmd = pci_config_readw(d, PCI_COMMAND); + cmd &= 0xfffc; + pci_config_writew(d, PCI_COMMAND, cmd); /* default memory mappings */ for(i = 0; i < PCI_NUM_REGIONS; i++) { int ofs; @@ -1035,6 +1026,10 @@ static void pci_bios_init_device(PCIDevice *d) } } } + /* enable i/o and memory access */ + cmd = pci_config_readw(d, PCI_COMMAND); + cmd |= (PCI_COMMAND_MEMORY | PCI_COMMAND_IO); + pci_config_writew(d, PCI_COMMAND, cmd); break; }