mirrors/Bochs
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Enhanced my previous updates, by making sure that both operands

Browse Source 
to byte operations in asm() statements use either a byte-accessible
  register (eax,ebx,ecx,edx) or a memory operand with "q" and "mq"
  constraints.
This commit is contained in:
Kevin Lawton 2002-09-23 00:40:58 +00:00
parent 9100d1ab1e
commit 30de048055
2 changed files with 17 additions and 17 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
bochs/cpu/arith8.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: arith8.cc,v 1.14 2002-09-23 00:27:18 kevinlawton Exp $
// $Id: arith8.cc,v 1.15 2002-09-23 00:40:58 kevinlawton Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -427,7 +427,7 @@ BX_CPU_C::CMP_EbGb(bxInstruction_c *i)
"pushfl \n\t"
"popl %0"
: "=g" (flags32)
: "q" (op1_8), "g" (op2_8)
: "q" (op1_8), "mq" (op2_8)
: "cc"
);
BX_CPU_THIS_PTR eflags.val32 =
@ -463,7 +463,7 @@ BX_CPU_C::CMP_GbEb(bxInstruction_c *i)
"pushfl \n\t"
"popl %0"
: "=g" (flags32)
: "q" (op1_8), "g" (op2_8)
: "q" (op1_8), "mq" (op2_8)
: "cc"
);
BX_CPU_THIS_PTR eflags.val32 =
@ -495,7 +495,7 @@ BX_CPU_C::CMP_ALIb(bxInstruction_c *i)
"pushfl \n\t"
"popl %0"
: "=g" (flags32)
: "q" (op1_8), "g" (op2_8)
: "q" (op1_8), "mq" (op2_8)
: "cc"
);
BX_CPU_THIS_PTR eflags.val32 =
@ -675,7 +675,7 @@ BX_CPU_C::CMP_EbIb(bxInstruction_c *i)
"pushfl \n\t"
"popl %0"
: "=g" (flags32)
: "q" (op1_8), "g" (op2_8)
: "q" (op1_8), "mq" (op2_8)
: "cc"
);
BX_CPU_THIS_PTR eflags.val32 =

24
bochs/cpu/logical8.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: logical8.cc,v 1.11 2002-09-22 22:22:16 kevinlawton Exp $
// $Id: logical8.cc,v 1.12 2002-09-23 00:40:58 kevinlawton Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -305,8 +305,8 @@ BX_CPU_C::AND_EbGb(bxInstruction_c *i)
"andb %3, %1\n\t"
"pushfl \n\t"
"popl %0"
: "=g" (flags32), "=r" (result)
: "1" (op1), "g" (op2)
: "=g" (flags32), "=q" (result)
: "1" (op1), "mq" (op2)
: "cc"
);
BX_CPU_THIS_PTR eflags.val32 =
@ -343,8 +343,8 @@ BX_CPU_C::AND_GbEb(bxInstruction_c *i)
"andb %3, %1\n\t"
"pushfl \n\t"
"popl %0"
: "=g" (flags32), "=r" (result)
: "1" (op1), "g" (op2)
: "=g" (flags32), "=q" (result)
: "1" (op1), "mq" (op2)
: "cc"
);
BX_CPU_THIS_PTR eflags.val32 =
@ -377,8 +377,8 @@ BX_CPU_C::AND_ALIb(bxInstruction_c *i)
"andb %3, %1\n\t"
"pushfl \n\t"
"popl %0"
: "=g" (flags32), "=r" (result)
: "1" (op1), "g" (op2)
: "=g" (flags32), "=q" (result)
: "1" (op1), "mq" (op2)
: "cc"
);
BX_CPU_THIS_PTR eflags.val32 =
@ -423,8 +423,8 @@ BX_CPU_C::AND_EbIb(bxInstruction_c *i)
"andb %3, %1\n\t"
"pushfl \n\t"
"popl %0"
: "=g" (flags32), "=r" (result)
: "1" (op1), "g" (op2)
: "=g" (flags32), "=q" (result)
: "1" (op1), "mq" (op2)
: "cc"
);
BX_CPU_THIS_PTR eflags.val32 =
@ -461,7 +461,7 @@ BX_CPU_C::TEST_EbGb(bxInstruction_c *i)
"pushfl \n\t"
"popl %0"
: "=g" (flags32)
: "r" (op1), "g" (op2)
: "q" (op1), "mq" (op2)
: "cc"
);
BX_CPU_THIS_PTR eflags.val32 =
@ -495,7 +495,7 @@ BX_CPU_C::TEST_ALIb(bxInstruction_c *i)
"pushfl \n\t"
"popl %0"
: "=g" (flags32)
: "r" (op1), "g" (op2)
: "q" (op1), "mq" (op2)
: "cc"
);
BX_CPU_THIS_PTR eflags.val32 =
@ -535,7 +535,7 @@ BX_CPU_C::TEST_EbIb(bxInstruction_c *i)
"pushfl \n\t"
"popl %0"
: "=g" (flags32)
: "r" (op1), "g" (op2)
: "q" (op1), "mq" (op2)
: "cc"
);
BX_CPU_THIS_PTR eflags.val32 =