mirror of https://github.com/bochs-emu/Bochs
- implementation of the PCI device register mechanism
The new function register_pci_handlers() is similar to the register functions for i/o addresses. A PCI device can register the read/write handlers for it's private PCI configuration space. The i/o mapped registers of the host bridge control the access to the configuration registers of each PCI device. You can select the bus, device, function and register address with the confAddr register. The confData register is a window to the configuration space of the selected device. - reset sets the values of the i/o mapped registers to 0 - changed some BX_INFO messages to BX_DEBUG
This commit is contained in:
Volker Ruppert
parent
d5e43f24b4
commit
1bd3646867
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@ -1,8 +1,8 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: pci.cc,v 1.14 2002-05-10 10:56:04 vruppert Exp $
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// $Id: pci.cc,v 1.15 2002-05-30 07:33:48 vruppert Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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// Copyright (C) 2002 MandrakeSoft S.A.
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//
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// MandrakeSoft S.A.
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// 43, rue d'Aboukir
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@ -45,13 +45,28 @@ bx_pci_c bx_pci;
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bx_pci_c::bx_pci_c(void)
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{
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put("PCI");
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settype(PCILOG);
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unsigned i;
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put("PCI");
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settype(PCILOG);
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BX_PCI_THIS num_pci_handles = 0;
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/* set unused elements to appropriate values */
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for (i=0; i < BX_MAX_PCI_DEVICES; i++) {
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BX_PCI_THIS pci_handler[i].read = NULL;
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BX_PCI_THIS pci_handler[i].write = NULL;
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}
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for (i=0; i < 0x100; i++) {
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BX_PCI_THIS pci_handler_id[i] = BX_MAX_PCI_DEVICES; // not assigned
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}
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}
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bx_pci_c::~bx_pci_c(void)
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{
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BX_INFO(("Exit."));
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// nothing for now
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BX_DEBUG(("Exit."));
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}
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@ -73,6 +88,9 @@ bx_pci_c::init(bx_devices_c *d)
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d->register_io_write_handler(this, write_handler, i, "i440FX");
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}
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BX_PCI_THIS register_pci_handlers(this, pci_read_handler, pci_write_handler,
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0x00, "440FX Host bridge");
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for (unsigned i=0; i<256; i++)
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BX_PCI_THIS s.i440fx.array[i] = 0x0;
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}
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@ -87,6 +105,9 @@ bx_pci_c::init(bx_devices_c *d)
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void
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bx_pci_c::reset(void)
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{
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BX_PCI_THIS s.i440fx.confAddr = 0;
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BX_PCI_THIS s.i440fx.confData = 0;
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BX_PCI_THIS s.i440fx.array[0x04] = 0x06;
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BX_PCI_THIS s.i440fx.array[0x05] = 0x00;
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BX_PCI_THIS s.i440fx.array[0x06] = 0x80;
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@ -144,29 +165,23 @@ bx_pci_c::read(Bit32u address, unsigned io_len)
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case 0x0CFE:
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case 0x0CFF:
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{
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Bit32u val440fx, retMask;
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// PMC is bus 0 / device 0 / function 0
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if ((BX_PCI_THIS s.i440fx.confAddr & 0x80FFFF00) == 0x80000000) {
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val440fx = BX_PCI_THIS s.i440fx.confData >> ((address & 0x3)*8);
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Bit32u handle, retval;
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Bit8u devfunc, regnum;
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switch (io_len) {
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case 1:
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retMask = 0xFF; break;
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case 2:
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retMask = 0xFFFF; break;
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case 4:
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retMask = 0xFFFFFFFF; break;
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default:
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retMask = 0xFFFFFFFF; break;
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}
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val440fx = (val440fx & retMask);
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BX_DEBUG(("440FX PMC read register 0x%02x value 0x%08x",
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(Bit8u)(BX_PCI_THIS s.i440fx.confAddr & 0xfc) + (address & 0x3),
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val440fx));
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return val440fx;
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if ((BX_PCI_THIS s.i440fx.confAddr & 0x80FF0000) == 0x80000000) {
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devfunc = (BX_PCI_THIS s.i440fx.confAddr >> 8) & 0xff;
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regnum = (BX_PCI_THIS s.i440fx.confAddr & 0xfc) + (address & 0x03);
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handle = BX_PCI_THIS pci_handler_id[devfunc];
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if ((io_len <= 4) && (handle < BX_MAX_PCI_DEVICES))
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retval = (* BX_PCI_THIS pci_handler[handle].read)
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(BX_PCI_THIS pci_handler[handle].this_ptr, regnum, io_len);
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else
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retval = 0xFFFFFFFF;
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}
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else
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return 0xFFFFFFFF;
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retval = 0xFFFFFFFF;
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BX_PCI_THIS s.i440fx.confData = retval;
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return retval;
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}
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}
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@ -198,20 +213,16 @@ bx_pci_c::write(Bit32u address, Bit32u value, unsigned io_len)
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switch (address) {
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case 0xCF8:
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{
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Bit8u idx440fx;
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// confAddr accepts a dword value only
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if (io_len == 4) {
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BX_PCI_THIS s.i440fx.confAddr = value;
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if ((value & 0x80FFFF00) == 0x80000000) {
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idx440fx = (Bit8u)(value & 0xFC);
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memcpy(&BX_PCI_THIS s.i440fx.confData, &BX_PCI_THIS s.i440fx.array[idx440fx], 4);
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BX_DEBUG(("440FX PMC register 0x%02x selected", idx440fx));
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}
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else {
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BX_PCI_THIS s.i440fx.confData = 0xFFFFFFFF;
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BX_DEBUG(("440FX request for bus 0x%02x device 0x%02x function 0x%02x",
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(value >> 16) & 0xFF, (value >> 11) & 0x1F, (value >> 8) & 0x07));
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}
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if ((value & 0x80FFFF00) == 0x80000000) {
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BX_DEBUG(("440FX PMC register 0x%02x selected", value & 0xfc));
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}
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else if ((value & 0x80000000) == 0x80000000) {
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BX_DEBUG(("440FX request for bus 0x%02x device 0x%02x function 0x%02x",
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(value >> 16) & 0xFF, (value >> 11) & 0x1F, (value >> 8) & 0x07));
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}
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}
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}
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break;
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@ -221,32 +232,22 @@ bx_pci_c::write(Bit32u address, Bit32u value, unsigned io_len)
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case 0xCFE:
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case 0xCFF:
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{
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Bit8u max_len, idx440fx;
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Bit32u handle;
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Bit8u devfunc, regnum;
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idx440fx = (Bit8u)((BX_PCI_THIS s.i440fx.confAddr & 0xFC) + (address & 0x3));
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max_len = 4 - (address & 0x3);
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if (io_len < max_len) max_len = io_len;
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if ((BX_PCI_THIS s.i440fx.confAddr & 0x80FFFF00) == 0x80000000) {
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for (unsigned i=0; i<max_len; i++) {
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switch (idx440fx+i) {
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case 0x00:
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case 0x01:
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case 0x02:
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case 0x03:
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case 0x06:
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case 0x08:
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case 0x09:
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case 0x0a:
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case 0x0b:
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case 0x0e:
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break;
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default:
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BX_PCI_THIS s.i440fx.array[idx440fx+i] = (value >> (i*8)) & 0xFF;
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BX_DEBUG(("440FX PMC write register 0x%02x value 0x%02x",
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idx440fx, (value >> (i*8)) & 0xFF));
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if ((BX_PCI_THIS s.i440fx.confAddr & 0x80FF0000) == 0x80000000) {
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devfunc = (BX_PCI_THIS s.i440fx.confAddr >> 8) & 0xff;
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regnum = (BX_PCI_THIS s.i440fx.confAddr & 0xfc) + (address & 0x03);
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handle = BX_PCI_THIS pci_handler_id[devfunc];
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if ((io_len <= 4) && (handle < BX_MAX_PCI_DEVICES)) {
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if (((regnum>=4) && (regnum<=7)) || (regnum==12) || (regnum==13) || (regnum>14)) {
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(* BX_PCI_THIS pci_handler[handle].write)
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(BX_PCI_THIS pci_handler[handle].this_ptr, regnum, value, io_len);
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BX_PCI_THIS s.i440fx.confData = value << (8 * (address & 0x03));
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}
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else
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BX_DEBUG(("read only register, write ignored"));
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}
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memcpy(&BX_PCI_THIS s.i440fx.confData, &BX_PCI_THIS s.i440fx.array[idx440fx], 4);
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}
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}
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break;
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@ -257,6 +258,76 @@ bx_pci_c::write(Bit32u address, Bit32u value, unsigned io_len)
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}
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// static pci configuration space read callback handler
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// redirects to non-static class handler to avoid virtual functions
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Bit32u
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bx_pci_c::pci_read_handler(void *this_ptr, Bit8u address, unsigned io_len)
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{
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#if !BX_USE_PCI_SMF
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bx_pci_c *class_ptr = (bx_pci_c *) this_ptr;
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return( class_ptr->pci_read(address, io_len) );
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}
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Bit32u
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bx_pci_c::pci_read(Bit8u address, unsigned io_len)
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{
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#else
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UNUSED(this_ptr);
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#endif // !BX_USE_PCI_SMF
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Bit32u val440fx = 0;
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if (io_len <= 4) {
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memcpy(&val440fx, &BX_PCI_THIS s.i440fx.array[address], io_len);
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BX_DEBUG(("440FX PMC read register 0x%02x value 0x%08x", address, val440fx));
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return val440fx;
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}
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else
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return(0xffffffff);
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}
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// static pci configuration space write callback handler
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// redirects to non-static class handler to avoid virtual functions
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void
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bx_pci_c::pci_write_handler(void *this_ptr, Bit8u address, Bit32u value, unsigned io_len)
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{
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#if !BX_USE_PCI_SMF
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bx_pci_c *class_ptr = (bx_pci_c *) this_ptr;
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class_ptr->pci_write(address, value, io_len);
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}
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void
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bx_pci_c::pci_write(Bit8u address, Bit32u value, unsigned io_len)
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{
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#else
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UNUSED(this_ptr);
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#endif // !BX_USE_PCI_SMF
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Bit8u value8;
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if (io_len <= 4) {
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for (unsigned i=0; i<io_len; i++) {
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value8 = (value >> (i*8)) & 0xFF;
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switch (address+i) {
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case 0x06:
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case 0x0c:
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break;
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default:
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BX_PCI_THIS s.i440fx.array[address+i] = value8;
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BX_DEBUG(("440FX PMC write register 0x%02x value 0x%02x", address,
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value8));
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}
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}
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}
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}
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Bit32u
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bx_pci_c::mapRead (Bit32u val)
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{
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@ -383,16 +454,16 @@ bx_pci_c::print_i440fx_state()
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{
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int i;
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BX_INFO(( "i440fxConfAddr:0x%08x", BX_PCI_THIS s.i440fx.confAddr ));
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BX_INFO(( "i440fxConfData:0x%08x", BX_PCI_THIS s.i440fx.confData ));
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BX_DEBUG(( "i440fxConfAddr:0x%08x", BX_PCI_THIS s.i440fx.confAddr ));
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BX_DEBUG(( "i440fxConfData:0x%08x", BX_PCI_THIS s.i440fx.confData ));
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#ifdef DUMP_FULL_I440FX
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for (i=0; i<256; i++) {
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BX_INFO(( "i440fxArray%02x:0x%02x", i, BX_PCI_THIS s.i440fx.array[i] ));
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BX_DEBUG(( "i440fxArray%02x:0x%02x", i, BX_PCI_THIS s.i440fx.array[i] ));
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}
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#else /* DUMP_FULL_I440FX */
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for (i=0x59; i<0x60; i++) {
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BX_INFO(( "i440fxArray%02x:0x%02x", i, BX_PCI_THIS s.i440fx.array[i] ));
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BX_DEBUG(( "i440fxArray%02x:0x%02x", i, BX_PCI_THIS s.i440fx.array[i] ));
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}
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#endif /* DUMP_FULL_I440FX */
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}
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@ -415,3 +486,32 @@ bx_pci_c::i440fx_fetch_ptr(Bit32u addr)
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else
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return (&BX_PCI_THIS devices->mem->vector[addr]);
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}
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Boolean
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bx_pci_c::register_pci_handlers( void *this_ptr, bx_pci_read_handler_t f1,
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bx_pci_write_handler_t f2, Bit8u devfunc,
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const char *name)
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{
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unsigned handle;
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/* first check if device/function is available */
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if (BX_PCI_THIS pci_handler_id[devfunc] == BX_MAX_PCI_DEVICES) {
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if (BX_PCI_THIS num_pci_handles >= BX_MAX_PCI_DEVICES) {
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BX_INFO(("too many PCI devices installed."));
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BX_PANIC((" try increasing BX_MAX_PCI_DEVICES"));
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return false;
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}
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handle = BX_PCI_THIS num_pci_handles++;
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BX_PCI_THIS pci_handler[handle].read = f1;
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BX_PCI_THIS pci_handler[handle].write = f2;
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BX_PCI_THIS pci_handler[handle].this_ptr = this_ptr;
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BX_PCI_THIS pci_handler_id[devfunc] = handle;
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BX_INFO(("%s present at device %d, function %d", name, devfunc >> 3,
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devfunc & 0x07));
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return true; // device/function mapped successfully
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}
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else {
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return false; // device/function not available, return false.
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}
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}
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@ -1,8 +1,8 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: pci.h,v 1.5 2001-11-14 01:39:22 bdenney Exp $
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// $Id: pci.h,v 1.6 2002-05-30 07:33:48 vruppert Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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// Copyright (C) 2002 MandrakeSoft S.A.
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//
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// MandrakeSoft S.A.
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// 43, rue d'Aboukir
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@ -27,6 +27,11 @@
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#if BX_PCI_SUPPORT
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#define BX_MAX_PCI_DEVICES 20
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typedef Bit32u (*bx_pci_read_handler_t)(void *, Bit8u, unsigned);
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typedef void (*bx_pci_write_handler_t)(void *, Bit8u, Bit32u, unsigned);
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#if BX_USE_PCI_SMF
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# define BX_PCI_SMF static
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# define BX_PCI_THIS bx_pci.
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@ -52,6 +57,9 @@ public:
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~bx_pci_c(void);
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BX_PCI_SMF void init(bx_devices_c *);
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BX_PCI_SMF void reset(void);
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Boolean register_pci_handlers(void *this_ptr, bx_pci_read_handler_t f1,
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bx_pci_write_handler_t f2, Bit8u devfunc,
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const char *name);
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BX_PCI_SMF void print_i440fx_state( );
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BX_PCI_SMF Bit32u rd_memType (Bit32u addr);
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BX_PCI_SMF Bit32u wr_memType (Bit32u addr);
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@ -64,11 +72,23 @@ public:
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private:
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bx_devices_c *devices;
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Bit8u pci_handler_id[0x100]; // 256 devices/functions
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struct {
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bx_pci_read_handler_t read;
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bx_pci_write_handler_t write;
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void *this_ptr;
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} pci_handler[BX_MAX_PCI_DEVICES];
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unsigned num_pci_handles;
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static Bit32u read_handler(void *this_ptr, Bit32u address, unsigned io_len);
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static void write_handler(void *this_ptr, Bit32u address, Bit32u value, unsigned io_len);
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static Bit32u pci_read_handler(void *this_ptr, Bit8u address, unsigned io_len);
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static void pci_write_handler(void *this_ptr, Bit8u address, Bit32u value, unsigned io_len);
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#if !BX_USE_PCI_SMF
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Bit32u read(Bit32u address, unsigned io_len);
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void write(Bit32u address, Bit32u value, unsigned io_len);
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Bit32u pci_read(Bit8u address, unsigned io_len);
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void pci_write(Bit8u address, Bit32u value, unsigned io_len);
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#endif
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BX_PCI_SMF Bit32u mapRead (Bit32u val);
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BX_PCI_SMF Bit32u mapWrite (Bit32u val);
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