2005-08-10 23:04:19 +04:00
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TODO (know issues in CPU model):
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-------------------------------
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[!] The following 3DNow! instructions still not implemented:
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PF2IW_PqQq
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PFNACC_PqQq
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PFPNACC_PqQq
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PFCMPGE_PqQq
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PFCMPGT_PqQq
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PFCMPEQ_PqQq
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PFMIN_PqQq
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PFMAX_PqQq
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PFRCP_PqQq
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PFRSQRT_PqQq
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PFSUB_PqQq
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PFSUBR_PqQq
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PFADD_PqQq
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PFACC_PqQq,
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PFMUL_PqQq
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PFRCPIT1_PqQq
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PFRSQIT1_PqQq
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PFRCPIT2_PqQq
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[!] CPUID does not report 3DNow! instruction set
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2006-01-11 21:22:12 +03:00
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[!] Some of APIC functionality still not implemented, for example
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2008-12-12 00:00:01 +03:00
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- LVT pins handling
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2006-01-11 21:22:12 +03:00
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- Filter interrupts according processor priority (PPR)
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2005-08-10 23:04:19 +04:00
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2005-10-14 02:53:03 +04:00
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[!] REP NOP is PAUSE (on P4/XEON)
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When running in SMP mode, this means that we are in a spin loop.
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This processor should yield to the other one, as we are anyhow waiting
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for a lock, and any other processor is responsible for this.
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2007-01-29 00:27:31 +03:00
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2008-04-08 21:59:51 +04:00
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[!] 32-bit linear address wrap when executing in legacy mode might be
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2008-04-16 09:41:43 +04:00
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not implemented correctly for system memory accesses (like descriptor
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2008-04-08 21:59:51 +04:00
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tables and etc)
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2010-04-09 00:08:05 +04:00
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[!] 16-bit address size wrap might be not implemented correctly for
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instructons with multiple memory accesses.
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2008-02-03 00:46:54 +03:00
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[!] AMD and Intel x86_64 implementations are different.
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2009-10-02 20:09:08 +04:00
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Currently Bochs emulation is according to Intel version.
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2007-04-10 00:28:15 +04:00
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Do we need to support both ?
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[!] More flexible CPUID - vendor and etc
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2007-09-20 21:33:35 +04:00
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2009-01-31 14:34:51 +03:00
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[!] VMX:
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- Dual-monitor treatment of SMIs and SMM not implemented yet
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- VMENTER to not-active state not supported yet
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2010-03-16 17:51:20 +03:00
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[!] SSE4A, SMX, SVM, AVX
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