67 lines
1.9 KiB
C
67 lines
1.9 KiB
C
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#ifndef BX_SSE_EXTENSIONS_H
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#define BX_SSE_EXTENSIONS_H
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/* XMM REGISTER */
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typedef Bit32u Float32;
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typedef Bit64u Float64;
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typedef union bx_xmm_reg_t {
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Bit8s s8[16];
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Bit16s s16[8];
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Bit32s s32[4];
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Bit64s s64[2];
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Bit8u u8[16];
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Bit16u u16[8];
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Bit32u u32[4];
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Bit64u u64[2];
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Float32 f32[4];
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Float64 f64[2];
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} BxPackedXmmRegister;
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#ifdef BX_SUPPORT_X86_64
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# define BX_XMM_REGISTERS 16
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#else
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# define BX_XMM_REGISTERS 8
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#endif
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/* MXCSR REGISTER */
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/* 31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16
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* ==|==|=====|==|==|==|==|==|==|==|==|==|==|==|== (reserved)
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* 0| 0| 0| 0| 0| 0| 0| 0| 0| 0| 0| 0| 0| 0| 0| 0
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*
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* 15|14|13|12|11|10| 9| 8| 7| 6| 5| 4| 3| 2| 1| 0
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* ==|==|=====|==|==|==|==|==|==|==|==|==|==|==|==
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* FZ| R C |PM|UM|OM|ZM|DM|IM|DZ|PE|UE|OE|ZE|DE|IE
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*/
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/* MXCSR REGISTER FIELDS DESCRIPTION */
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/*
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* IE 0 Invalid-Operation Exception 0
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* DE 1 Denormalized-Operand Exception 0
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* ZE 2 Zero-Divide Exception 0
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* OE 3 Overflow Exception 0
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* UE 4 Underflow Exception 0
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* PE 5 Precision Exception 0
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* DZ 6 Denormals are Zeros 0
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* IM 7 Invalid-Operation Exception Mask 1
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* DM 8 Denormalized-Operand Exception Mask 1
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* ZM 9 Zero-Divide Exception Mask 1
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* OM 10 Overflow Exception Mask 1
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* UM 11 Underflow Exception Mask 1
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* PM 12 Precision Exception Mask 1
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* RC 13-14 Floating-Point Rounding Control 00
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* FZ 15 Flush-to-Zero for Masked Underflow 0
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*/
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struct bx_mxcsr_t {
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Bit32u mxcsr; /* define bitfields accessors later */
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};
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#define MXCSR_MASK 0x00FF /* reset reserved bits */
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#define MXCSR_RESET 0x1F80 /* reset value of the MXCSR register */
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#endif
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