427 lines
12 KiB
C
427 lines
12 KiB
C
/* vim: tabstop=4 shiftwidth=4 noexpandtab
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* This file is part of ToaruOS and is released under the terms
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* of the NCSA / University of Illinois License - see LICENSE.md
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* Copyright (C) 2017 Kevin Lange
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*/
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#include <module.h>
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#include <logging.h>
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#include <printf.h>
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#include <pci.h>
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#include <mem.h>
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#include <list.h>
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#include <pipe.h>
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#include <ipv4.h>
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#include <mod/net.h>
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static uint32_t e1000_device_pci = 0x00000000;
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static int e1000_irq = 0;
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static uintptr_t mem_base = 0;
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static int has_eeprom = 0;
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static uint8_t mac[6];
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static int rx_index = 0;
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static int tx_index = 0;
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static list_t * net_queue = NULL;
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static spin_lock_t net_queue_lock = { 0 };
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static list_t * rx_wait;
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static uint32_t mmio_read32(uintptr_t addr) {
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return *((volatile uint32_t*)(addr));
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}
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static void mmio_write32(uintptr_t addr, uint32_t val) {
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(*((volatile uint32_t*)(addr))) = val;
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}
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static void write_command(uint16_t addr, uint32_t val) {
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mmio_write32(mem_base + addr, val);
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}
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static uint32_t read_command(uint16_t addr) {
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return mmio_read32(mem_base + addr);
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}
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#define E1000_NUM_RX_DESC 32
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#define E1000_NUM_TX_DESC 8
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struct rx_desc {
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volatile uint64_t addr;
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volatile uint16_t length;
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volatile uint16_t checksum;
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volatile uint8_t status;
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volatile uint8_t errors;
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volatile uint16_t special;
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} __attribute__((packed)); /* this looks like it should pack fine as-is */
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struct tx_desc {
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volatile uint64_t addr;
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volatile uint16_t length;
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volatile uint8_t cso;
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volatile uint8_t cmd;
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volatile uint8_t status;
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volatile uint8_t css;
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volatile uint16_t special;
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} __attribute__((packed));
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static uint8_t * rx_virt[E1000_NUM_RX_DESC];
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static uint8_t * tx_virt[E1000_NUM_TX_DESC];
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static struct rx_desc * rx;
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static struct tx_desc * tx;
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static void enqueue_packet(void * buffer) {
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spin_lock(net_queue_lock);
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list_insert(net_queue, buffer);
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spin_unlock(net_queue_lock);
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}
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static struct ethernet_packet * dequeue_packet(void) {
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while (!net_queue->length) {
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sleep_on(rx_wait);
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}
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spin_lock(net_queue_lock);
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node_t * n = list_dequeue(net_queue);
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void* value = n->value;
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free(n);
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spin_unlock(net_queue_lock);
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return value;
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}
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static uint8_t* get_mac() {
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return mac;
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}
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#define E1000_REG_CTRL 0x0000
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#define E1000_REG_STATUS 0x0008
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#define E1000_REG_EEPROM 0x0014
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#define E1000_REG_CTRL_EXT 0x0018
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#define E1000_REG_RCTRL 0x0100
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#define E1000_REG_RXDESCLO 0x2800
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#define E1000_REG_RXDESCHI 0x2804
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#define E1000_REG_RXDESCLEN 0x2808
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#define E1000_REG_RXDESCHEAD 0x2810
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#define E1000_REG_RXDESCTAIL 0x2818
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#define E1000_REG_TCTRL 0x0400
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#define E1000_REG_TXDESCLO 0x3800
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#define E1000_REG_TXDESCHI 0x3804
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#define E1000_REG_TXDESCLEN 0x3808
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#define E1000_REG_TXDESCHEAD 0x3810
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#define E1000_REG_TXDESCTAIL 0x3818
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#define RCTL_EN (1 << 1) /* Receiver Enable */
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#define RCTL_SBP (1 << 2) /* Store Bad Packets */
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#define RCTL_UPE (1 << 3) /* Unicast Promiscuous Enabled */
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#define RCTL_MPE (1 << 4) /* Multicast Promiscuous Enabled */
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#define RCTL_LPE (1 << 5) /* Long Packet Reception Enable */
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#define RCTL_LBM_NONE (0 << 6) /* No Loopback */
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#define RCTL_LBM_PHY (3 << 6) /* PHY or external SerDesc loopback */
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#define RTCL_RDMTS_HALF (0 << 8) /* Free Buffer Threshold is 1/2 of RDLEN */
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#define RTCL_RDMTS_QUARTER (1 << 8) /* Free Buffer Threshold is 1/4 of RDLEN */
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#define RTCL_RDMTS_EIGHTH (2 << 8) /* Free Buffer Threshold is 1/8 of RDLEN */
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#define RCTL_MO_36 (0 << 12) /* Multicast Offset - bits 47:36 */
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#define RCTL_MO_35 (1 << 12) /* Multicast Offset - bits 46:35 */
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#define RCTL_MO_34 (2 << 12) /* Multicast Offset - bits 45:34 */
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#define RCTL_MO_32 (3 << 12) /* Multicast Offset - bits 43:32 */
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#define RCTL_BAM (1 << 15) /* Broadcast Accept Mode */
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#define RCTL_VFE (1 << 18) /* VLAN Filter Enable */
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#define RCTL_CFIEN (1 << 19) /* Canonical Form Indicator Enable */
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#define RCTL_CFI (1 << 20) /* Canonical Form Indicator Bit Value */
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#define RCTL_DPF (1 << 22) /* Discard Pause Frames */
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#define RCTL_PMCF (1 << 23) /* Pass MAC Control Frames */
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#define RCTL_SECRC (1 << 26) /* Strip Ethernet CRC */
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#define RCTL_BSIZE_256 (3 << 16)
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#define RCTL_BSIZE_512 (2 << 16)
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#define RCTL_BSIZE_1024 (1 << 16)
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#define RCTL_BSIZE_2048 (0 << 16)
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#define RCTL_BSIZE_4096 ((3 << 16) | (1 << 25))
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#define RCTL_BSIZE_8192 ((2 << 16) | (1 << 25))
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#define RCTL_BSIZE_16384 ((1 << 16) | (1 << 25))
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#define TCTL_EN (1 << 1) /* Transmit Enable */
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#define TCTL_PSP (1 << 3) /* Pad Short Packets */
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#define TCTL_CT_SHIFT 4 /* Collision Threshold */
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#define TCTL_COLD_SHIFT 12 /* Collision Distance */
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#define TCTL_SWXOFF (1 << 22) /* Software XOFF Transmission */
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#define TCTL_RTLC (1 << 24) /* Re-transmit on Late Collision */
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#define CMD_EOP (1 << 0) /* End of Packet */
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#define CMD_IFCS (1 << 1) /* Insert FCS */
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#define CMD_IC (1 << 2) /* Insert Checksum */
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#define CMD_RS (1 << 3) /* Report Status */
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#define CMD_RPS (1 << 4) /* Report Packet Sent */
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#define CMD_VLE (1 << 6) /* VLAN Packet Enable */
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#define CMD_IDE (1 << 7) /* Interrupt Delay Enable */
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static int eeprom_detect(void) {
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write_command(E1000_REG_EEPROM, 1);
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for (int i = 0; i < 100000 && !has_eeprom; ++i) {
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uint32_t val = read_command(E1000_REG_EEPROM);
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if (val & 0x10) has_eeprom = 1;
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}
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return 0;
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}
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static uint16_t eeprom_read(uint8_t addr) {
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uint32_t temp = 0;
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write_command(E1000_REG_EEPROM, 1 | ((uint32_t)(addr) << 8));
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while (!((temp = read_command(E1000_REG_EEPROM)) & (1 << 4)));
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return (uint16_t)((temp >> 16) & 0xFFFF);
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}
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//static list_t * net_queue = NULL;
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//static spin_lock_t net_queue_lock = { 0 };
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//static list_t * rx_wait;
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static void find_e1000(uint32_t device, uint16_t vendorid, uint16_t deviceid, void * extra) {
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if ((vendorid == 0x8086) && (deviceid == 0x100e)) {
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*((uint32_t *)extra) = device;
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}
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}
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static void read_mac(void) {
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if (has_eeprom) {
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uint32_t t;
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t = eeprom_read(0);
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mac[0] = t & 0xFF;
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mac[1] = t >> 8;
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t = eeprom_read(1);
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mac[2] = t & 0xFF;
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mac[3] = t >> 8;
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t = eeprom_read(2);
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mac[4] = t & 0xFF;
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mac[5] = t >> 8;
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} else {
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uint8_t * mac_addr = (uint8_t *)(mem_base + 0x5400);
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for (int i = 0; i < 6; ++i) {
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mac[i] = mac_addr[i];
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}
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}
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}
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static int irq_handler(struct regs *r) {
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uint32_t status = read_command(0xc0);
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irq_ack(e1000_irq);
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if (!status) return 0;
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if (status & 0x04) {
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/* Start link */
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debug_print(NOTICE, "start link");
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} else if (status & 0x10) {
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/* ?? */
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} else if (status & ((1 << 6) | (1 << 7))) {
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/* receive packet */
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do {
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rx_index = read_command(E1000_REG_RXDESCTAIL);
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if (rx_index == (int)read_command(E1000_REG_RXDESCHEAD)) return 1;
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rx_index = (rx_index + 1) % E1000_NUM_RX_DESC;
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if (rx[rx_index].status & 0x01) {
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uint8_t * pbuf = (uint8_t *)rx_virt[rx_index];
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uint16_t plen = rx[rx_index].length;
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void * packet = malloc(plen);
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memcpy(packet, pbuf, plen);
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rx[rx_index].status = 0;
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enqueue_packet(packet);
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write_command(E1000_REG_RXDESCTAIL, rx_index);
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} else {
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break;
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}
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} while (1);
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wakeup_queue(rx_wait);
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}
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return 1;
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}
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static void send_packet(uint8_t* payload, size_t payload_size) {
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tx_index = read_command(E1000_REG_TXDESCTAIL);
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memcpy(tx_virt[tx_index], payload, payload_size);
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tx[tx_index].length = payload_size;
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tx[tx_index].cmd = CMD_EOP | CMD_IFCS | CMD_RS; //| CMD_RPS;
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tx[tx_index].status = 0;
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tx_index = (tx_index + 1) % E1000_NUM_TX_DESC;
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write_command(E1000_REG_TXDESCTAIL, tx_index);
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}
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static void init_rx(void) {
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uintptr_t phys;
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rx = (void*)kvmalloc_p(sizeof(struct rx_desc) * E1000_NUM_RX_DESC + 16, &phys);
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for (int i = 0; i < E1000_NUM_RX_DESC; ++i) {
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rx_virt[i] = (void*)kvmalloc_p(8192 + 16, (uint32_t *)&rx[i].addr);
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rx[i].status = 0;
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}
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write_command(E1000_REG_RXDESCLO, phys);
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write_command(E1000_REG_RXDESCHI, 0);
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write_command(E1000_REG_RXDESCLEN, E1000_NUM_RX_DESC * sizeof(struct rx_desc));
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write_command(E1000_REG_RXDESCHEAD, 0);
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write_command(E1000_REG_RXDESCTAIL, E1000_NUM_RX_DESC - 1);
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rx_index = 0;
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write_command(E1000_REG_RCTRL,
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RCTL_EN |
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(read_command(E1000_REG_RCTRL) & (~((1 << 17) | (1 << 16)))));
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}
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static void init_tx(void) {
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uintptr_t phys;
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tx = (void*)kvmalloc_p(sizeof(struct tx_desc) * E1000_NUM_TX_DESC + 16, &phys);
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for (int i = 0; i < E1000_NUM_TX_DESC; ++i) {
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tx_virt[i] = (void*)kvmalloc_p(8192, (uint32_t *)&tx[i].addr);
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debug_print(WARNING, "tx[%d] 0x%x → 0x%x", i, tx_virt[i], (uint32_t)tx[i].addr);
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tx[i].status = 0;
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tx[i].cmd = (1 << 0);
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}
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write_command(E1000_REG_TXDESCLO, phys);
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write_command(E1000_REG_TXDESCHI, 0);
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write_command(E1000_REG_TXDESCLEN, E1000_NUM_TX_DESC * sizeof(struct tx_desc));
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write_command(E1000_REG_TXDESCHEAD, 0);
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write_command(E1000_REG_TXDESCTAIL, 0);
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tx_index = 0;
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write_command(E1000_REG_TCTRL,
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TCTL_EN |
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TCTL_PSP |
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read_command(E1000_REG_TCTRL));
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}
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static void e1000_init(void * data, char * name) {
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/* This seems to always be memory mapped on important devices. */
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mem_base = pci_read_field(e1000_device_pci, PCI_BAR0, 4) & 0xFFFFFFF0;
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for (size_t x = 0; x < 0x10000; x += 0x1000) {
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uintptr_t addr = (mem_base & 0xFFFFF000) + x;
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dma_frame(get_page(addr, 1, kernel_directory), 0, 1, addr);
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}
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#if 1
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uint16_t command_reg = pci_read_field(e1000_device_pci, PCI_COMMAND, 2);
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if (command_reg & (1 << 2)) {
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debug_print(NOTICE, "Bus mastering already enabled.\n");
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}
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command_reg |= (1 << 2);
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command_reg |= (1 << 0);
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pci_write_field(e1000_device_pci, PCI_COMMAND, 2, command_reg);
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#endif
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debug_print(NOTICE, "mem base: 0x%x", mem_base);
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eeprom_detect();
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debug_print(NOTICE, "has_eeprom = %d", has_eeprom);
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read_mac();
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debug_print(NOTICE, "device mac %2x:%2x:%2x:%2x:%2x:%2x", mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
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/* initialize */
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write_command(E1000_REG_CTRL, (1 << 26));
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/* wait */
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unsigned long s, ss;
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relative_time(0, 10, &s, &ss);
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sleep_until((process_t *)current_process, s, ss);
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switch_task(0);
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debug_print(NOTICE, "back from sleep");
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/* setup */
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write_command(E1000_REG_CTRL, (1 << 5) | (1 << 6));
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uint32_t status = read_command(E1000_REG_CTRL);
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status &= ~(1 << 3);
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status &= ~(1 << 31);
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status &= ~(1 << 7);
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write_command(E1000_REG_CTRL, status);
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write_command(0x0028, 0);
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write_command(0x002c, 0);
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write_command(0x0030, 0);
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write_command(0x0170, 0);
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status = read_command(E1000_REG_CTRL);
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status &= ~(1 << 30);
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write_command(E1000_REG_CTRL, status);
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net_queue = list_create();
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rx_wait = list_create();
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e1000_irq = pci_read_field(e1000_device_pci, PCI_INTERRUPT_LINE, 1);
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irq_install_handler(e1000_irq, irq_handler);
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debug_print(NOTICE, "Binding interrupt %d", e1000_irq);
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for (int i = 0; i < 128; ++i) {
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write_command(0x5200 + i * 4, 0);
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}
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for (int i = 0; i < 64; ++i) {
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write_command(0x4000 + i * 4, 0);
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}
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#if 0
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write_command(0x5400, *(uint32_t*)(&mac[0]));
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write_command(0x5404, *(uint16_t*)(&mac[4]));
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write_command(0x5404, read_command(0x5404) | (1 << 31));
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#endif
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write_command(E1000_REG_RCTRL, (1 << 4));
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init_rx();
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init_tx();
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//write_command(0x00D0, read_command(0x00D0) | (1 << 2) | (1 << 6) | (1 << 7) | (1 << 1) | (1 << 0));
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write_command(0x00D0, 0xFF);
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read_command(0xc0);
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init_netif_funcs(get_mac, dequeue_packet, send_packet, "Intel E1000");
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create_kernel_tasklet(net_handler, "[eth]", NULL);
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}
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static int init(void) {
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pci_scan(&find_e1000, -1, &e1000_device_pci);
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if (!e1000_device_pci) {
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debug_print(WARNING, "No e1000 device found.");
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return 1;
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}
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create_kernel_tasklet(e1000_init, "[e1000]", NULL);
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return 0;
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}
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static int fini(void) {
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return 0;
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}
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MODULE_DEF(e1000, init, fini);
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MODULE_DEPENDS(net);
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