2021-05-31 04:47:02 +03:00
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/**
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* @file kernel/misc/pci.c
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* @brief PCI configuration and scanning.
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2018-03-16 15:56:19 +03:00
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*
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2021-05-31 04:47:02 +03:00
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* Functions for dealing with PCI devices through configuration mode #1
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* (CPU port I/O methods), including scanning and modifying device
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* configuration bytes.
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*
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* This used to have methods for dealing with ISA bridge IRQ remapping,
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* but it has been removed for the moment.
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*
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* TODO: Implement MSI configuration?
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2021-11-26 05:31:10 +03:00
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*
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* @copyright
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* This file is part of ToaruOS and is released under the terms
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* of the NCSA / University of Illinois License - see LICENSE.md
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* Copyright (C) 2011-2021 K. Lange
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2018-03-16 15:56:19 +03:00
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*/
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2021-05-31 04:47:02 +03:00
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#include <stdint.h>
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#include <kernel/string.h>
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2018-03-19 05:38:11 +03:00
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#include <kernel/pci.h>
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2021-09-09 06:22:20 +03:00
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#include <kernel/printf.h>
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2018-03-19 05:38:11 +03:00
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2022-01-23 04:36:46 +03:00
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#include <kernel/mmu.h>
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#ifdef __x86_64__
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2021-05-31 04:47:02 +03:00
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#include <kernel/arch/x86_64/ports.h>
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2022-01-23 04:36:46 +03:00
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#endif
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static uintptr_t pcie_addr(uint32_t device, int field) {
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return (pci_extract_bus(device) << 20) | (pci_extract_slot(device) << 15) | (pci_extract_func(device) << 12) | (field);
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}
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2021-05-31 04:47:02 +03:00
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2022-02-06 15:10:20 +03:00
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uintptr_t pcie_ecam_phys = 0x3f000000;
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2021-05-31 04:47:02 +03:00
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/**
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* @brief Write to a PCI device configuration space field.
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*/
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2018-03-16 15:56:19 +03:00
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void pci_write_field(uint32_t device, int field, int size, uint32_t value) {
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2022-01-23 04:36:46 +03:00
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#ifdef __x86_64__
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2018-03-16 15:56:19 +03:00
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outportl(PCI_ADDRESS_PORT, pci_get_addr(device, field));
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outportl(PCI_VALUE_PORT, value);
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2022-01-23 04:36:46 +03:00
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#else
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/* ECAM space */
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if (size == 4) {
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2022-02-06 15:10:20 +03:00
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*(volatile uint32_t*)mmu_map_from_physical(pcie_ecam_phys + pcie_addr(device,field)) = value;
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2022-01-23 04:36:46 +03:00
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return;
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} else if (size == 2) {
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2022-02-06 15:10:20 +03:00
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*(volatile uint16_t*)mmu_map_from_physical(pcie_ecam_phys + pcie_addr(device,field)) = value;
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2022-01-23 04:36:46 +03:00
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return;
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} else if (size == 1) {
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2022-02-06 15:10:20 +03:00
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*(volatile uint8_t*)mmu_map_from_physical(pcie_ecam_phys + pcie_addr(device,field)) = value;
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2022-01-23 04:36:46 +03:00
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return;
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}
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dprintf("rejected invalid field write\n");
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#endif
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2018-03-16 15:56:19 +03:00
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}
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2021-05-31 04:47:02 +03:00
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/**
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* @brief Read from a PCI device configuration space field.
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*/
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2018-03-16 15:56:19 +03:00
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uint32_t pci_read_field(uint32_t device, int field, int size) {
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2022-01-23 04:36:46 +03:00
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#ifdef __x86_64__
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2018-03-16 15:56:19 +03:00
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outportl(PCI_ADDRESS_PORT, pci_get_addr(device, field));
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if (size == 4) {
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uint32_t t = inportl(PCI_VALUE_PORT);
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return t;
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} else if (size == 2) {
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uint16_t t = inports(PCI_VALUE_PORT + (field & 2));
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return t;
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} else if (size == 1) {
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uint8_t t = inportb(PCI_VALUE_PORT + (field & 3));
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return t;
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}
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2022-01-23 04:36:46 +03:00
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#else
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uintptr_t field_addr = pcie_addr(device,field);
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if (size == 4) {
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2022-02-06 15:10:20 +03:00
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return *(volatile uint32_t*)mmu_map_from_physical(pcie_ecam_phys + field_addr);
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2022-01-23 04:36:46 +03:00
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} else if (size == 2) {
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2022-02-06 15:10:20 +03:00
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return *(volatile uint16_t*)mmu_map_from_physical(pcie_ecam_phys + field_addr);
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2022-01-23 04:36:46 +03:00
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} else if (size == 1) {
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2022-02-06 15:10:20 +03:00
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return *(volatile uint8_t*)mmu_map_from_physical(pcie_ecam_phys + field_addr);
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2022-01-23 04:36:46 +03:00
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}
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#endif
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2018-03-16 15:56:19 +03:00
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return 0xFFFF;
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}
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2021-05-31 04:47:02 +03:00
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/**
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* @brief Obtain the device type from the class and subclass fields.
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*/
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2018-03-16 15:56:19 +03:00
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uint16_t pci_find_type(uint32_t dev) {
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return (pci_read_field(dev, PCI_CLASS, 1) << 8) | pci_read_field(dev, PCI_SUBCLASS, 1);
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}
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2021-05-31 04:47:02 +03:00
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static void pci_scan_hit(pci_func_t f, uint32_t dev, void * extra) {
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2018-03-16 15:56:19 +03:00
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int dev_vend = (int)pci_read_field(dev, PCI_VENDOR_ID, 2);
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int dev_dvid = (int)pci_read_field(dev, PCI_DEVICE_ID, 2);
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f(dev, dev_vend, dev_dvid, extra);
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}
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void pci_scan_func(pci_func_t f, int type, int bus, int slot, int func, void * extra) {
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uint32_t dev = pci_box_device(bus, slot, func);
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if (type == -1 || type == pci_find_type(dev)) {
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pci_scan_hit(f, dev, extra);
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}
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if (pci_find_type(dev) == PCI_TYPE_BRIDGE) {
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pci_scan_bus(f, type, pci_read_field(dev, PCI_SECONDARY_BUS, 1), extra);
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}
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}
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void pci_scan_slot(pci_func_t f, int type, int bus, int slot, void * extra) {
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uint32_t dev = pci_box_device(bus, slot, 0);
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if (pci_read_field(dev, PCI_VENDOR_ID, 2) == PCI_NONE) {
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return;
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}
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pci_scan_func(f, type, bus, slot, 0, extra);
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if (!pci_read_field(dev, PCI_HEADER_TYPE, 1)) {
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return;
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}
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for (int func = 1; func < 8; func++) {
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uint32_t dev = pci_box_device(bus, slot, func);
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if (pci_read_field(dev, PCI_VENDOR_ID, 2) != PCI_NONE) {
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pci_scan_func(f, type, bus, slot, func, extra);
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}
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}
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}
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void pci_scan_bus(pci_func_t f, int type, int bus, void * extra) {
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for (int slot = 0; slot < 32; ++slot) {
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pci_scan_slot(f, type, bus, slot, extra);
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}
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}
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2021-05-31 04:47:02 +03:00
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/**
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* @brief Scan PCI buses for devices, calling the given function for each device.
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*
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* Used by drivers to implement device discovery, runs a callback function for ever
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* device found. A device consists of a bus, slot, and function. Also performs
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* recursive scans of bridges.
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*/
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2018-03-16 15:56:19 +03:00
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void pci_scan(pci_func_t f, int type, void * extra) {
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if ((pci_read_field(0, PCI_HEADER_TYPE, 1) & 0x80) == 0) {
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pci_scan_bus(f,type,0,extra);
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return;
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}
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2021-06-15 15:18:14 +03:00
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int hit = 0;
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2018-03-16 15:56:19 +03:00
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for (int func = 0; func < 8; ++func) {
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uint32_t dev = pci_box_device(0, 0, func);
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if (pci_read_field(dev, PCI_VENDOR_ID, 2) != PCI_NONE) {
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2021-06-15 15:18:14 +03:00
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hit = 1;
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2018-03-16 15:56:19 +03:00
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pci_scan_bus(f, type, func, extra);
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} else {
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break;
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}
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}
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2021-06-15 15:18:14 +03:00
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if (!hit) {
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for (int bus = 0; bus < 256; ++bus) {
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for (int slot = 0; slot < 32; ++slot) {
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pci_scan_slot(f,type,bus,slot,extra);
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}
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}
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}
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2018-03-16 15:56:19 +03:00
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}
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2018-07-21 10:57:36 +03:00
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int pci_get_interrupt(uint32_t device) {
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2021-09-09 06:22:20 +03:00
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return pci_read_field(device, PCI_INTERRUPT_LINE, 1);
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2018-07-21 10:57:36 +03:00
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}
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