David Karoly
83f755b5d8
kernel/arm: add memory barriers for page table ops
Introduce memory barriers according to ARMARM,
section G.5.3 TLB maintenance operations and barriers
Sequence for mapping memory in (both L1 and L2):
* DSB
* Invalidate i-cache (TODO)
* Insert new entry in page directory / page table
* DSB
* ISB
Sequence for mapping memory out:
* Remove page table entry
* DSB
* Invalidate TLB entry
* DSB
* ISB
Sequence for updating a page table entry:
* Update page table entry
* DSB
* Invalidate TLB entry
* Invalidate branch predictor (TODO)
* DSB
* ISB
Note: i-cache invalidation and branch predictor invalidation is
not implemented yet as this commit focuses on implementing memory
barriers.
Change-Id: I192fa80f6b43117236a4be6fa8c988afca90e015
Reviewed-on: https://review.haiku-os.org/c/haiku/+/5241
Tested-by: Commit checker robot <no-reply+buildbot@haiku-os.org>
Reviewed-by: Fredrik Holmqvist <fredrik.holmqvist@gmail.com>
2022-04-28 19:57:49 +00:00
..
2020-10-08 08:23:31 +00:00
2021-04-10 20:28:43 +00:00
2019-05-24 14:21:37 -04:00
2020-03-10 13:14:09 +00:00
2022-04-22 14:25:48 +00:00
2021-11-18 16:24:04 -05:00
2019-03-26 20:06:09 -04:00
2022-03-22 11:38:06 -04:00
2022-04-21 18:30:40 +00:00
2020-04-12 16:55:52 +00:00
2021-08-20 12:43:16 +00:00
2021-11-23 13:50:45 -05:00
2022-04-28 19:57:49 +00:00
2022-04-21 15:50:32 +00:00
2020-09-01 18:14:57 +00:00
2021-01-03 20:51:37 +00:00
2021-01-27 19:53:11 +00:00
2021-08-15 11:47:17 +02:00
2021-03-14 09:10:18 +00:00
2021-11-17 18:45:58 -05:00
2021-03-18 08:19:55 +00:00
2022-04-25 20:57:20 +00:00
2022-04-23 19:55:31 +00:00
2021-10-26 16:47:50 -04:00
2022-04-25 19:47:26 +00:00
2019-08-30 18:27:35 -04:00
2022-02-18 21:27:47 +00:00
2020-04-20 14:56:59 +00:00